added assert_equal to read/write test

hw/unit_tests/cache/cachesim.cpp

@@ -51,17 +51,21 @@ void CacheSim::reset() {
   this->step();
   cache_->reset = 0;
   this->step();
+
   dram_rsp_vec_.clear();
+  //clear req and rsp vecs
   
 }
 
 void CacheSim::step() {
+  //toggle clock
   cache_->clk = 0;
   this->eval();
 
   cache_->clk = 1;
   this->eval();
 
+  //handle core and dram reqs and rsps
   this->eval_reqs();
   this->eval_rsps();
   this->eval_dram_bus();
@@ -76,33 +80,19 @@ void CacheSim::eval() {
 }
 
 void CacheSim::run(){
-//#ifndef NDEBUG
+#ifndef NDEBUG
   std::cout << timestamp << ": [sim] run()" << std::endl;
-
-  // reset the device
-  this->reset();
-
-//#endif
-
+#endif
   this->step();
-  int valid = 15; 
-  // execute program
 
-  while (!core_req_vec_.empty()) {
-
-    for(int i = 0; i < 10; ++i){
-      
-      this->step();
-    }
-}
-/*
-  while(valid > 10){ 
+  int valid = 300; 
+  
+  while (valid > -1) {
       this->step();
       if(!cache_->core_req_valid && !cache_->core_rsp_valid){
-        valid--;
+        valid--; 
       }
   }
-  */
 }
 
 void CacheSim::clear_req(){
@@ -149,7 +139,6 @@ void CacheSim::eval_reqs(){
    
   } else {
     clear_req();
-
   }
 }
 
@@ -240,6 +229,21 @@ void CacheSim::eval_dram_bus() {
   cache_->dram_req_ready = ~dram_stalled;
 }
 
+bool CacheSim::assert_equal(unsigned int* data, unsigned int tag){
+  int check = 0;
+  unsigned int *rsp = core_rsp_vec_.at(tag);
+  for (int i = 0; i < 4; ++i){
+    for (int j = 0; j < 4; ++j){
+      if (data[i] == rsp[j]){
+        check++;
+      }
+    }
+  }
+
+  return check; 
+
+}
+
 //DEBUG
 
 void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){

hw/unit_tests/cache/cachesim.h

@@ -32,7 +32,7 @@ typedef struct {
   unsigned byteen;
   unsigned *addr;
   unsigned *data;
-  unsigned tag;
+  unsigned int tag;
 } core_req_t;
 
 class CacheSim {
@@ -51,9 +51,7 @@ public:
   void run();  //run until all reqs are empty
   void clear_req(); 
   void send_req(core_req_t *req);
-
-  void set_core_req();
-  void set_core_req2();
+  bool assert_equal(unsigned int* data, unsigned int tag);
 
   //display funcs
 

hw/unit_tests/cache/testbench.cpp

@@ -24,7 +24,6 @@ int main(int argc, char **argv)
   RAM ram;
 	CacheSim cachesim;
   cachesim.attach_ram(&ram);
-  cachesim.reset();
 
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
@@ -47,14 +46,21 @@ int main(int argc, char **argv)
   read->addr = addr;
   read->data = addr; 
   read->tag = 0xff;
+  
+	// reset the device
+  cachesim.reset();
 
   //queue reqs
   cachesim.send_req(write);
   cachesim.send_req(read);
 
   cachesim.run(); 
-  for(int i = 0; i < 100; ++i){
-    cachesim.step();
+
+  bool check = cachesim.assert_equal(data, write->tag);
+  if(check){
+    std::cout << "PASSED" << std::endl;
+  } else {
+    std::cout << "FAILED" << std::endl;
   }
 
 	return 0;