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Point Sampling Tex Unit Update
This commit is contained in:
Krishna Yalamarthy
parent
b8022822bb
commit
41d7d8e7d5
5 changed files with 124 additions and 66 deletions
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@ -1,5 +1,5 @@
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2021-03-16 09:55:41.298661
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// Generated at 2021-03-18 16:51:17.003120
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#ifndef VX_USER_CONFIG
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#define VX_USER_CONFIG
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@ -7,7 +7,7 @@
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#endif
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2021-03-16 09:55:41.301258
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// Generated at 2021-03-18 16:51:17.005371
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// Translated from VX_config.vh:
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@ -251,30 +251,33 @@
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#define CSR_NC 0xFC2
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////////// Texture Unit CSRs /////////////
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#define CSR_TEX_BEGIN 0xFD0
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// Unit 1
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#define CSR_TEX0_ADDR CSR_TEX_BEGIN
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#define CSR_TEX0_FORMAT CSR_TEX_BEGIN + 0x1
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#define CSR_TEX0_WIDTH CSR_TEX_BEGIN + 0x2
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#define CSR_TEX0_HEIGHT CSR_TEX_BEGIN + 0x3
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#define CSR_TEX0_PITCH CSR_TEX_BEGIN + 0x4
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#define CSR_TEX0_WRAP_U CSR_TEX_BEGIN + 0x5
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#define CSR_TEX0_WRAP_V CSR_TEX_BEGIN + 0x6
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#define CSR_TEX0_MIN_FILTER CSR_TEX_BEGIN + 0x7
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#define CSR_TEX0_MAX_FILTER CSR_TEX_BEGIN + 0x8
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#define CSR_TEX0_ADDR CSR_TEX_BEGIN
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#define CSR_TEX0_FORMAT CSR_TEX_BEGIN + 0x1
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#define CSR_TEX0_WIDTH CSR_TEX_BEGIN + 0x2
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#define CSR_TEX0_HEIGHT CSR_TEX_BEGIN + 0x3
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#define CSR_TEX0_PITCH CSR_TEX_BEGIN + 0x4
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#define CSR_TEX0_WRAP_U CSR_TEX_BEGIN + 0x5
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#define CSR_TEX0_WRAP_V CSR_TEX_BEGIN + 0x6
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#define CSR_TEX0_MIN_FILTER CSR_TEX_BEGIN + 0x7
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#define CSR_TEX0_MAX_FILTER CSR_TEX_BEGIN + 0x8
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// Unit 2
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#define CSR_TEX1_ADDR CSR_TEX_BEGIN + 0x9
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#define CSR_TEX1_FORMAT CSR_TEX_BEGIN + 0xA
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#define CSR_TEX1_WIDTH CSR_TEX_BEGIN + 0xB
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#define CSR_TEX1_HEIGHT CSR_TEX_BEGIN + 0xC
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#define CSR_TEX1_PITCH CSR_TEX_BEGIN + 0xD
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#define CSR_TEX1_WRAP_U CSR_TEX_BEGIN + 0xE
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#define CSR_TEX1_WRAP_V CSR_TEX_BEGIN + 0xF
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#define CSR_TEX1_MIN_FILTER CSR_TEX_BEGIN + 0x10
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#define CSR_TEX1_MAX_FILTER CSR_TEX_BEGIN + 0x11
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#define CSR_TEX1_ADDR CSR_TEX_BEGIN + 0x9
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#define CSR_TEX1_FORMAT CSR_TEX_BEGIN + 0xA
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#define CSR_TEX1_WIDTH CSR_TEX_BEGIN + 0xB
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#define CSR_TEX1_HEIGHT CSR_TEX_BEGIN + 0xC
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#define CSR_TEX1_PITCH CSR_TEX_BEGIN + 0xD
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#define CSR_TEX1_WRAP_U CSR_TEX_BEGIN + 0xE
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#define CSR_TEX1_WRAP_V CSR_TEX_BEGIN + 0xF
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#define CSR_TEX1_MIN_FILTER CSR_TEX_BEGIN + 0x10
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#define CSR_TEX1_MAX_FILTER CSR_TEX_BEGIN + 0x11
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#define CSR_TEX_END CSR_TEX1_MAX_FILTER
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of LSU Request Queue
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@ -26,7 +26,7 @@
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`define CSR_ADDR_BITS 12
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`define CSR_WIDTH 12
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`define CSR_WIDTH 32
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///////////////////////////////////////////////////////////////////////////////
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@ -113,10 +113,10 @@ module VX_gpu_unit #(
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assign tex_req_if.wb = gpu_req_if.wb;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
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assign tex_req_if.v[i] = gpu_req_if.rs2_data[i];
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assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
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assign tex_req_if.v[i] = gpu_req_if.rs2_data[i];
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assign tex_req_if.lod[i] = gpu_req_if.rs3_data[i][31:8];
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assign tex_req_if.t[i] = gpu_req_if.rs3_data[i][7:0];
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assign tex_req_if.t[i] = gpu_req_if.rs3_data[i][7:0];
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end
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VX_tex_unit #(
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@ -2,11 +2,39 @@
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`include "VX_define.vh"
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module VX_tex_pt_addr #(
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parameter FRAC_BITS = 20,
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parameter INT_BITS = 32 - FRAC_BITS
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) (
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input wire clk,
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input wire reset,
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);
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input wire valid_in,
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output wire ready_out,
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input wire [`CSR_WIDTH-1:0] tex_addr,
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input wire [`CSR_WIDTH-1:0] tex_width,
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input wire [`CSR_WIDTH-1:0] tex_height,
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input wire [31:0] tex_u,
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input wire [31:0] tex_v,
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output wire [31:0] pt_addr,
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output wire valid_out,
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input wire ready_in
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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reg [31:0] x_offset;
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reg [31:0] y_offset;
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assign x_offset = tex_u >> (32'(FRAC_BITS) - tex_width);
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assign y_offset = tex_v >> (32'(FRAC_BITS) - tex_height);
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assign pt_addr = (tex_addr << (32 - `CSR_WIDTH)) + x_offset + (y_offset << tex_width);
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assign valid_out = valid_in;
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assign ready_out = ready_in;
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// Need to fill in
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endmodule
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@ -41,10 +41,7 @@ module VX_tex_unit #(
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reg [`CSR_WIDTH-1:0] tex_min_filter [`NUM_TEX_UNITS-1: 0];
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reg [`CSR_WIDTH-1:0] tex_max_filter [`NUM_TEX_UNITS-1: 0];
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`UNUSED_VAR (tex_addr)
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`UNUSED_VAR (tex_format)
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`UNUSED_VAR (tex_width)
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`UNUSED_VAR (tex_height)
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`UNUSED_VAR (tex_stride)
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`UNUSED_VAR (tex_wrap_u)
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`UNUSED_VAR (tex_wrap_v)
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@ -80,39 +77,7 @@ module VX_tex_unit #(
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end
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// texture response
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`UNUSED_VAR (tex_req_if.u)
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`UNUSED_VAR (tex_req_if.v)
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`UNUSED_VAR (tex_req_if.lod)
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`UNUSED_VAR (tex_req_if.t)
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assign stall_in = stall_out;
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assign rsp_valid = tex_req_if.valid;
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assign rsp_wid = tex_req_if.wid;
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assign rsp_tmask = tex_req_if.tmask;
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assign rsp_PC = tex_req_if.PC;
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assign rsp_rd = tex_req_if.rd;
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assign rsp_wb = tex_req_if.wb;
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assign rsp_data = {`NUM_THREADS{32'hFF0000FF}}; // dummy blue value
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/*//point sampling texel address computation
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tex_req_if.u[i] = gpu_req_if.rs1_data[i];
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assign tex_req_if.v[i] = gpu_req_if.rs2_data[i];
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assign tex_req_if.lod[i] = gpu_req_if.rs3_data[i][31:8];
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assign tex_req_if.t[i] = gpu_req_if.rs3_data[i][7:0];
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VX_tex_pt_addr #(
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) tex_pt_addr (
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.clk (clk),
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.reset (reset),
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);
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end*/
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// fifo/wait buffer for fragments and also to dcache
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// texture unit <-> dcache
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VX_lsu_req_if lsu_req_if();
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@ -129,8 +94,65 @@ module VX_tex_unit #(
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.ld_commit_if (ld_commit_if)
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);
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// output
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assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
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//point sampling - texel address computation
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wire [`NUM_THREADS-1:0] pt_addr_valid;
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wire [`NUM_THREADS-1:0] pt_addr_ready;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [`CSR_WIDTH-1:0] tex_addr_select;
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wire [`CSR_WIDTH-1:0] tex_width_select;
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wire [`CSR_WIDTH-1:0] tex_height_select;
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assign tex_addr_select = (tex_req_if.t[i] == 'b1) ? tex_addr[1] : tex_addr[0];
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assign tex_width_select = (tex_req_if.t[i] == 'b1) ? tex_width[1] : tex_width[0];
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assign tex_height_select = (tex_req_if.t[i] == 'b1) ? tex_height[1] : tex_height[0];
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VX_tex_pt_addr #(
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.FRAC_BITS(28)
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) tex_pt_addr (
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.clk (clk),
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.reset (reset),
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.valid_in (tex_req_if.valid),
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.ready_out (pt_addr_ready[i]),
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.tex_addr (tex_addr_select),
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.tex_width (tex_width_select),
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.tex_height (tex_height_select),
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.tex_u (tex_req_if.u[i]),
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.tex_v (tex_req_if.v[i]),
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.pt_addr (lsu_req_if.base_addr[i]),
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.valid_out (pt_addr_valid[i]),
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.ready_in (lsu_req_if.ready)
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);
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end
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assign tex_req_if.ready = (& pt_addr_ready);
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assign lsu_req_if.valid = (& pt_addr_valid);
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assign lsu_req_if.wid = tex_req_if.wid;
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assign lsu_req_if.tmask = tex_req_if.tmask;
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assign lsu_req_if.PC = tex_req_if.PC;
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assign lsu_req_if.rd = tex_req_if.rd;
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assign lsu_req_if.wb = tex_req_if.wb;
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assign lsu_req_if.offset = 32'h0000;
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assign lsu_req_if.op_type = `OP_BITS'({1'b0, 3'b000}); //func3 for word load??
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assign lsu_req_if.store_data = {`NUM_THREADS{32'h0000}};
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// wait buffer for fragments / replace with cache/state fragment fifo for bilerp
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// no filtering for point sampling -> directly from dcache to output response
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assign rsp_valid = ld_commit_if.valid;
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assign rsp_wid = ld_commit_if.wid;
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assign rsp_tmask = ld_commit_if.tmask;
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assign rsp_PC = ld_commit_if.PC;
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assign rsp_rd = ld_commit_if.rd;
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assign rsp_wb = ld_commit_if.wb;
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assign rsp_data = ld_commit_if.data;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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@ -143,8 +165,13 @@ module VX_tex_unit #(
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.data_out ({tex_rsp_if.valid, tex_rsp_if.wid, tex_rsp_if.tmask, tex_rsp_if.PC, tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.data})
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);
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// output
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assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
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// can accept new request?
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assign tex_req_if.ready = ~stall_in;
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assign stall_in = stall_out;
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assign ld_commit_if.ready = ~stall_in;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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