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Using verilog For-loops + Passing all tests

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This commit is contained in:
felsabbagh3 2019-03-30 22:55:13 -04:00
parent 52a839f84d
commit 4aac33b298
11 changed files with 1622 additions and 439 deletions
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47
rtl/VX_decode.v
View file

@ -137,49 +137,24 @@ module VX_decode(
// $display("Decode: curr_pc: %h", in_curr_PC);
// end
// genvar index;
genvar index;
// generate
// for (index=0; index < `NT; index=index+1)
// begin: gen_code_label
// VX_register_file vx_register_file(
// .clk(clk),
// .in_valid(in_wb_valid[index]),
// .in_write_register(write_register),
// .in_rd(in_rd),
// .in_data(in_write_data[index]),
// .in_src1(out_rs1),
// .in_src2(out_rs2),
// .out_src1_data(rd1_register[index]),
// .out_src2_data(rd2_register[index])
// );
// end
// endgenerate
VX_register_file vx_register_file_0(
generate
for (index=0; index < `NT; index=index+1)
begin: gen_code_label
VX_register_file vx_register_file(
.clk(clk),
.in_valid(in_wb_valid[0]),
.in_valid(in_wb_valid[index]),
.in_write_register(write_register),
.in_rd(in_rd),
.in_data(in_write_data[0]),
.in_data(in_write_data[index]),
.in_src1(out_rs1),
.in_src2(out_rs2),
.out_src1_data(rd1_register[0]),
.out_src2_data(rd2_register[0])
);
VX_register_file vx_register_file_1(
.clk(clk),
.in_valid(in_wb_valid[1]),
.in_write_register(write_register),
.in_rd(in_rd),
.in_data(in_write_data[1]),
.in_src1(out_rs1),
.in_src2(out_rs2),
.out_src1_data(rd1_register[1]),
.out_src2_data(rd2_register[1])
.out_src1_data(rd1_register[index]),
.out_src2_data(rd2_register[index])
);
end
endgenerate
assign curr_opcode = in_instruction[6:0];

89
rtl/VX_execute.v
View file

@ -47,78 +47,25 @@ module VX_execute (
// VX_alu vx_alu(
// .in_reg_data (in_reg_data),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result)
// );
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
VX_alu vx_alu(
// .in_reg_data (in_reg_data[1:0]),
.in_1 (in_a_reg_data[index_out_reg]),
.in_2 (in_b_reg_data[index_out_reg]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result[index_out_reg])
);
end
endgenerate
// genvar index;
// reg[5:0] index_2;
// generate
// for (index=0; index < `NT; index=index+1)
// begin: gen_code_label
// assign index_2 = index * 2;
// VX_alu vx_alu(
// .in_reg_data (in_reg_data[(index_2+1):(index_2)]),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result[index])
// );
// end
// endgenerate
// genvar index_out_reg;
// generate
// for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
// begin
// VX_alu vx_alu_0(
// // .in_reg_data (in_reg_data[1:0]),
// .in_1 (in_a_reg_data[index_out_reg]),
// .in_2 (in_b_reg_data[index_out_reg]),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result[index_out_reg])
// );
// end
// endgenerate
VX_alu vx_alu_0(
.in_1 (in_a_reg_data[0]),
.in_2 (in_b_reg_data[0]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result[0])
);
VX_alu vx_alu_1(
.in_1 (in_a_reg_data[1]),
.in_2 (in_b_reg_data[1]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_csr_data (in_csr_data),
.in_curr_PC (in_curr_PC),
.out_alu_result(out_alu_result[1])
);
assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
assign out_jal = in_jal;

1
rtl/VX_fetch.v
View file

@ -52,7 +52,6 @@ module VX_fetch (
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
valid[ini_cur_th] = 0; // Thread 1 active
valid[0] = 1;
// valid[1] = 0;
stall_reg = 0;
delay_reg = 0;
old = 0;

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rtl/obj_dir/VVortex
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1701
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load diff

48
rtl/obj_dir/VVortex.h
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@ -100,18 +100,24 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__fetch_valid[5],0,0);
@ -140,8 +146,11 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[5],0,0);
@ -158,6 +167,8 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[5],31,0);
};
struct {
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
@ -169,12 +180,21 @@ VL_MODULE(VVortex) {
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[5],0,0);
@ -221,6 +241,8 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[5],31,0);
};
struct {
VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[5],31,0);
@ -230,8 +252,6 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[5],31,0);
};
struct {
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[5],31,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);

BIN
rtl/obj_dir/VVortex__ALL.a
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BIN
rtl/obj_dir/VVortex__ALLcls.o
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22
rtl/obj_dir/VVortex__verFiles.dat
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@ -4,23 +4,23 @@ S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/lo
S 2862 12889318286 1553966962 0 1553966962 0 "VX_alu.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 5040 12889318287 1553995422 0 1553995422 0 "VX_d_e_reg.v"
S 11888 12889419225 1553995767 0 1553995767 0 "VX_decode.v"
S 11230 12889419225 1554000860 0 1554000860 0 "VX_decode.v"
S 1532 12889419227 1553998396 0 1553998396 0 "VX_define.v"
S 4077 12889318289 1553997299 0 1553997299 0 "VX_e_m_reg.v"
S 4908 12889318290 1553997136 0 1553997136 0 "VX_execute.v"
S 3288 12889318290 1554000824 0 1554000824 0 "VX_execute.v"
S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v"
S 4042 12889419228 1553998456 0 1553998456 0 "VX_fetch.v"
S 4020 12889419228 1554000776 0 1554000776 0 "VX_fetch.v"
S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 3002 12889084513 1553997670 0 1553997670 0 "VX_memory.v"
S 1003 12889419229 1553930745 0 1553930745 0 "VX_register_file.v"
S 1173 12889419230 1553930874 0 1553930874 0 "VX_writeback.v"
S 16452 12889419231 1553997933 0 1553997933 0 "Vortex.v"
T 276821 12889432530 1553998459 0 1553998459 0 "obj_dir/VVortex.cpp"
T 14673 12889432529 1553998459 0 1553998459 0 "obj_dir/VVortex.h"
T 1800 12889432532 1553998459 0 1553998459 0 "obj_dir/VVortex.mk"
T 530 12889432528 1553998459 0 1553998459 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889432527 1553998459 0 1553998459 0 "obj_dir/VVortex__Syms.h"
T 464 12889432533 1553998459 0 1553998459 0 "obj_dir/VVortex__ver.d"
T 0 0 1553998459 0 1553998459 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889432531 1553998459 0 1553998459 0 "obj_dir/VVortex_classes.mk"
T 347293 12889432530 1554000904 0 1554000904 0 "obj_dir/VVortex.cpp"
T 17090 12889432529 1554000904 0 1554000904 0 "obj_dir/VVortex.h"
T 1800 12889432532 1554000904 0 1554000904 0 "obj_dir/VVortex.mk"
T 530 12889432528 1554000904 0 1554000904 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889432527 1554000904 0 1554000904 0 "obj_dir/VVortex__Syms.h"
T 464 12889432533 1554000904 0 1554000904 0 "obj_dir/VVortex__ver.d"
T 0 0 1554000904 0 1554000904 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889432531 1554000904 0 1554000904 0 "obj_dir/VVortex_classes.mk"

153
rtl/obj_dir/debug.txt
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@ -98567,6 +98567,9 @@ RF: Writing 00008000 to 1
RF: Writing 00007e00 to 1
(800000cc) 00007e00 * b6db6db7 = 00001200
(800000cc) 00007e00 * b6db6db7 = 00001200
(800000cc) 00007e00 * b6db6db7 = 00001200
(800000cc) 00007e00 * b6db6db7 = 00001200
(800000cc) 00007e00 * b6db6db7 = 00001200
----
******
[800000c4] WB Data: b6db7000 {babebabe}, to register: 2 [1 0]
@ -98640,6 +98643,9 @@ RF: Writing 00008000 to 1
RF: Writing 00007fc0 to 1
(800000f0) 00007fc0 * b6db6db7 = 00001240
(800000f0) 00007fc0 * b6db6db7 = 00001240
(800000f0) 00007fc0 * b6db6db7 = 00001240
(800000f0) 00007fc0 * b6db6db7 = 00001240
(800000f0) 00007fc0 * b6db6db7 = 00001240
----
******
[800000e8] WB Data: b6db7000 {babebabe}, to register: 2 [1 0]
@ -98699,6 +98705,9 @@ RF: Writing 00000021 to 28
******
(8000010c) 00000000 * 00000000 = 00000000
(8000010c) 00000000 * 00000000 = 00000000
(8000010c) 00000000 * 00000000 = 00000000
(8000010c) 00000000 * 00000000 = 00000000
(8000010c) 00000000 * 00000000 = 00000000
----
******
[80000104] WB Data: 00000000 {babebabe}, to register: 1 [1 0]
@ -98751,6 +98760,9 @@ RF: Writing 00000002 to 28
******
(80000124) 00000001 * 00000001 = 00000001
(80000124) 00000001 * 00000001 = 00000001
(80000124) 00000001 * 00000001 = 00000001
(80000124) 00000001 * 00000001 = 00000001
(80000124) 00000001 * 00000001 = 00000001
----
******
[8000011c] WB Data: 00000001 {babebabe}, to register: 1 [1 0]
@ -98803,6 +98815,9 @@ RF: Writing 00000003 to 28
******
(8000013c) 00000003 * 00000007 = 00000015
(8000013c) 00000003 * 00000007 = 00000015
(8000013c) 00000003 * 00000007 = 00000015
(8000013c) 00000003 * 00000007 = 00000015
(8000013c) 00000003 * 00000007 = 00000015
----
******
[80000134] WB Data: 00000003 {babebabe}, to register: 1 [1 0]
@ -98855,6 +98870,9 @@ RF: Writing 00000004 to 28
******
(80000154) 00000000 * ffff8000 = 00000000
(80000154) 00000000 * ffff8000 = 00000000
(80000154) 00000000 * ffff8000 = 00000000
(80000154) 00000000 * ffff8000 = 00000000
(80000154) 00000000 * ffff8000 = 00000000
----
******
[8000014c] WB Data: 00000000 {babebabe}, to register: 1 [1 0]
@ -98907,6 +98925,9 @@ RF: Writing 00000005 to 28
******
(8000016c) 80000000 * 00000000 = 00000000
(8000016c) 80000000 * 00000000 = 00000000
(8000016c) 80000000 * 00000000 = 00000000
(8000016c) 80000000 * 00000000 = 00000000
(8000016c) 80000000 * 00000000 = 00000000
----
******
[80000164] WB Data: 80000000 {babebabe}, to register: 1 [1 0]
@ -98959,6 +98980,9 @@ RF: Writing 00000006 to 28
******
(80000184) 80000000 * ffff8000 = 00000000
(80000184) 80000000 * ffff8000 = 00000000
(80000184) 80000000 * ffff8000 = 00000000
(80000184) 80000000 * ffff8000 = 00000000
(80000184) 80000000 * ffff8000 = 00000000
----
******
[8000017c] WB Data: 80000000 {babebabe}, to register: 1 [1 0]
@ -99025,6 +99049,9 @@ RF: Writing aaaab000 to 1
RF: Writing aaaaaaab to 1
(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
(800001a4) aaaaaaab * 0002fe7d = 0000ff7f
----
******
[8000019c] WB Data: 00030000 {babebabe}, to register: 2 [1 0]
@ -99098,6 +99125,9 @@ RF: Writing 00030000 to 1
RF: Writing 0002fe7d to 1
(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
(800001c8) 0002fe7d * aaaaaaab = 0000ff7f
----
******
[800001c0] WB Data: aaaab000 {babebabe}, to register: 2 [1 0]
@ -99157,6 +99187,9 @@ RF: Writing 0000001f to 28
******
(800001e4) ff000000 * ff000000 = 00000000
(800001e4) ff000000 * ff000000 = 00000000
(800001e4) ff000000 * ff000000 = 00000000
(800001e4) ff000000 * ff000000 = 00000000
(800001e4) ff000000 * ff000000 = 00000000
----
******
[800001dc] WB Data: ff000000 {babebabe}, to register: 1 [1 0]
@ -99209,6 +99242,9 @@ RF: Writing 00000022 to 28
******
(800001fc) ffffffff * ffffffff = 00000001
(800001fc) ffffffff * ffffffff = 00000001
(800001fc) ffffffff * ffffffff = 00000001
(800001fc) ffffffff * ffffffff = 00000001
(800001fc) ffffffff * ffffffff = 00000001
----
******
[800001f4] WB Data: ffffffff {babebabe}, to register: 1 [1 0]
@ -99261,6 +99297,9 @@ RF: Writing 00000023 to 28
******
(80000214) ffffffff * 00000001 = ffffffff
(80000214) ffffffff * 00000001 = ffffffff
(80000214) ffffffff * 00000001 = ffffffff
(80000214) ffffffff * 00000001 = ffffffff
(80000214) ffffffff * 00000001 = ffffffff
----
******
[8000020c] WB Data: ffffffff {babebabe}, to register: 1 [1 0]
@ -99313,6 +99352,9 @@ RF: Writing 00000024 to 28
******
(8000022c) 00000001 * ffffffff = ffffffff
(8000022c) 00000001 * ffffffff = ffffffff
(8000022c) 00000001 * ffffffff = ffffffff
(8000022c) 00000001 * ffffffff = ffffffff
(8000022c) 00000001 * ffffffff = ffffffff
----
******
[80000224] WB Data: 00000001 {babebabe}, to register: 1 [1 0]
@ -99365,6 +99407,9 @@ RF: Writing 00000025 to 28
******
(80000244) 0000000d * 0000000b = 0000008f
(80000244) 0000000d * 0000000b = 0000008f
(80000244) 0000000d * 0000000b = 0000008f
(80000244) 0000000d * 0000000b = 0000008f
(80000244) 0000000d * 0000000b = 0000008f
----
******
[8000023c] WB Data: 0000000d {babebabe}, to register: 1 [1 0]
@ -99417,6 +99462,9 @@ RF: Writing 00000008 to 28
******
(8000025c) 0000000e * 0000000b = 0000009a
(8000025c) 0000000e * 0000000b = 0000009a
(8000025c) 0000000e * 0000000b = 0000009a
(8000025c) 0000000e * 0000000b = 0000009a
(8000025c) 0000000e * 0000000b = 0000009a
----
******
[80000254] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -99464,6 +99512,9 @@ RF: Writing 00000009 to 28
******
(80000270) 0000000d * 0000000d = 000000a9
(80000270) 0000000d * 0000000d = 000000a9
(80000270) 0000000d * 0000000d = 000000a9
(80000270) 0000000d * 0000000d = 000000a9
(80000270) 0000000d * 0000000d = 000000a9
----
******
@ -99521,6 +99572,9 @@ RF: Writing 0000000a to 28
RF: Writing 00000000 to 4
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
----
******
[80000284] WB Data: 0000000d {babebabe}, to register: 1 [1 0]
@ -99580,6 +99634,9 @@ RF: Writing 00000002 to 5
******
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
(8000028c) 0000000d * 0000000b = 0000008f
----
******
[80000284] WB Data: 0000000d {babebabe}, to register: 1 [1 0]
@ -99675,6 +99732,9 @@ RF: Writing 0000000b to 28
RF: Writing 00000000 to 4
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
----
******
[800002b0] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -99740,6 +99800,9 @@ RF: Writing 00000002 to 5
******
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
(800002b8) 0000000e * 0000000b = 0000009a
----
******
[800002b0] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -99841,6 +99904,9 @@ RF: Writing 0000000c to 28
RF: Writing 00000000 to 4
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
----
******
[800002e0] WB Data: 0000000f {babebabe}, to register: 1 [1 0]
@ -99912,6 +99978,9 @@ RF: Writing 00000002 to 5
******
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
(800002e8) 0000000f * 0000000b = 000000a5
----
******
[800002e0] WB Data: 0000000f {babebabe}, to register: 1 [1 0]
@ -100019,6 +100088,9 @@ RF: Writing 0000000d to 28
RF: Writing 00000000 to 4
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
----
******
[80000314] WB Data: 0000000d {babebabe}, to register: 1 [1 0]
@ -100071,6 +100143,9 @@ RF: Writing 00000002 to 5
******
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
(8000031c) 0000000d * 0000000b = 0000008f
----
******
[80000314] WB Data: 0000000d {babebabe}, to register: 1 [1 0]
@ -100166,6 +100241,9 @@ RF: Writing 00000000 to 4
RF: Writing 0000000e to 1
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
----
******
[80000340] WB Data: 0000000b {babebabe}, to register: 2 [1 0]
@ -100224,6 +100302,9 @@ RF: Writing 00000002 to 5
RF: Writing 0000000e to 1
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
(80000348) 0000000e * 0000000b = 0000009a
----
******
[80000340] WB Data: 0000000b {babebabe}, to register: 2 [1 0]
@ -100325,6 +100406,9 @@ RF: Writing 0000000f to 1
RF: Writing 0000000b to 2
(80000378) 0000000f * 0000000b = 000000a5
(80000378) 00000000 * 0000000b = 00000000
(80000378) 00000000 * 0000000b = 00000000
(80000378) 00000000 * 0000000b = 00000000
(80000378) 00000000 * 0000000b = 00000000
----
******
[80000370] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -100389,6 +100473,9 @@ RF: Writing 0000000f to 1
RF: Writing 0000000b to 2
(80000378) 0000000f * 0000000b = 000000a5
(80000378) 00000000 * 0000000b = 00000000
(80000378) 00000000 * 0000000b = 00000000
(80000378) 00000000 * 0000000b = 00000000
(80000378) 00000000 * 0000000b = 00000000
----
******
[80000370] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -100482,6 +100569,9 @@ RF: Writing 00000000 to 4
RF: Writing 0000000d to 1
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
----
******
[8000039c] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -100540,6 +100630,9 @@ RF: Writing 00000002 to 5
RF: Writing 0000000d to 1
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
(800003a4) 0000000d * 0000000b = 0000008f
----
******
[8000039c] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -100640,6 +100733,9 @@ RF: Writing 0000000e to 1
******
(800003d4) 0000000e * 0000000b = 0000009a
(800003d4) 00000000 * 0000000b = 00000000
(800003d4) 00000000 * 0000000b = 00000000
(800003d4) 00000000 * 0000000b = 00000000
(800003d4) 00000000 * 0000000b = 00000000
----
******
[800003cc] WB Data: 0000000b {babebabe}, to register: 2 [1 0]
@ -100704,6 +100800,9 @@ RF: Writing 0000000e to 1
******
(800003d4) 0000000e * 0000000b = 0000009a
(800003d4) 00000000 * 0000000b = 00000000
(800003d4) 00000000 * 0000000b = 00000000
(800003d4) 00000000 * 0000000b = 00000000
(800003d4) 00000000 * 0000000b = 00000000
----
******
[800003cc] WB Data: 0000000b {babebabe}, to register: 2 [1 0]
@ -100804,6 +100903,9 @@ RF: Writing 0000000f to 1
******
(80000404) 0000000f * 0000000b = 000000a5
(80000404) 00000000 * 0000000b = 00000000
(80000404) 00000000 * 0000000b = 00000000
(80000404) 00000000 * 0000000b = 00000000
(80000404) 00000000 * 0000000b = 00000000
----
******
[800003fc] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -100868,6 +100970,9 @@ RF: Writing 0000000f to 1
******
(80000404) 0000000f * 0000000b = 000000a5
(80000404) 00000000 * 0000000b = 00000000
(80000404) 00000000 * 0000000b = 00000000
(80000404) 00000000 * 0000000b = 00000000
(80000404) 00000000 * 0000000b = 00000000
----
******
[800003fc] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -100955,6 +101060,9 @@ RF: Writing 00000013 to 28
RF: Writing 00000000 to 4
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
----
******
[80000424] WB Data: 0000000b {babebabe}, to register: 2 [1 0]
@ -101007,6 +101115,9 @@ RF: Writing 00000002 to 5
******
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
(8000042c) 0000000d * 0000000b = 0000008f
----
******
[80000424] WB Data: 0000000b {babebabe}, to register: 2 [1 0]
@ -101102,6 +101213,9 @@ RF: Writing 00000000 to 4
RF: Writing 0000000b to 2
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
----
******
[80000450] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -101160,6 +101274,9 @@ RF: Writing 00000002 to 5
RF: Writing 0000000b to 2
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
(80000458) 0000000e * 0000000b = 0000009a
----
******
[80000450] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -101261,6 +101378,9 @@ RF: Writing 0000000b to 2
RF: Writing 0000000f to 1
(80000488) 0000000f * 0000000b = 000000a5
(80000488) 0000000f * 00000000 = 00000000
(80000488) 0000000f * 00000000 = 00000000
(80000488) 0000000f * 00000000 = 00000000
(80000488) 0000000f * 00000000 = 00000000
----
******
[80000480] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -101325,6 +101445,9 @@ RF: Writing 0000000b to 2
RF: Writing 0000000f to 1
(80000488) 0000000f * 0000000b = 000000a5
(80000488) 0000000f * 00000000 = 00000000
(80000488) 0000000f * 00000000 = 00000000
(80000488) 0000000f * 00000000 = 00000000
(80000488) 0000000f * 00000000 = 00000000
----
******
[80000480] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -101418,6 +101541,9 @@ RF: Writing 00000000 to 4
RF: Writing 0000000b to 2
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
----
******
[800004ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -101476,6 +101602,9 @@ RF: Writing 00000002 to 5
RF: Writing 0000000b to 2
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
(800004b4) 0000000d * 0000000b = 0000008f
----
******
[800004ac] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -101576,6 +101705,9 @@ RF: Writing 0000000b to 2
******
(800004e4) 0000000e * 0000000b = 0000009a
(800004e4) 0000000e * 00000000 = 00000000
(800004e4) 0000000e * 00000000 = 00000000
(800004e4) 0000000e * 00000000 = 00000000
(800004e4) 0000000e * 00000000 = 00000000
----
******
[800004dc] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -101640,6 +101772,9 @@ RF: Writing 0000000b to 2
******
(800004e4) 0000000e * 0000000b = 0000009a
(800004e4) 0000000e * 00000000 = 00000000
(800004e4) 0000000e * 00000000 = 00000000
(800004e4) 0000000e * 00000000 = 00000000
(800004e4) 0000000e * 00000000 = 00000000
----
******
[800004dc] WB Data: 0000000e {babebabe}, to register: 1 [1 0]
@ -101740,6 +101875,9 @@ RF: Writing 0000000b to 2
******
(80000514) 0000000f * 0000000b = 000000a5
(80000514) 0000000f * 00000000 = 00000000
(80000514) 0000000f * 00000000 = 00000000
(80000514) 0000000f * 00000000 = 00000000
(80000514) 0000000f * 00000000 = 00000000
----
******
[8000050c] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -101804,6 +101942,9 @@ RF: Writing 0000000b to 2
******
(80000514) 0000000f * 0000000b = 000000a5
(80000514) 0000000f * 00000000 = 00000000
(80000514) 0000000f * 00000000 = 00000000
(80000514) 0000000f * 00000000 = 00000000
(80000514) 0000000f * 00000000 = 00000000
----
******
[8000050c] WB Data: 00000000 {babebabe}, to register: 0 [1 0]
@ -101879,6 +102020,9 @@ RF: Writing 00000019 to 28
******
(80000534) 00000000 * 0000001f = 00000000
(80000534) 00000000 * 0000001f = 00000000
(80000534) 00000000 * 0000001f = 00000000
(80000534) 00000000 * 0000001f = 00000000
(80000534) 00000000 * 0000001f = 00000000
----
******
@ -101924,6 +102068,9 @@ RF: Writing 0000001a to 28
******
(80000548) 00000020 * 00000000 = 00000000
(80000548) 00000020 * 00000000 = 00000000
(80000548) 00000020 * 00000000 = 00000000
(80000548) 00000020 * 00000000 = 00000000
(80000548) 00000020 * 00000000 = 00000000
----
******
@ -101964,6 +102111,9 @@ RF: Writing 0000001b to 28
******
(80000558) 00000000 * 00000000 = 00000000
(80000558) 00000000 * 00000000 = 00000000
(80000558) 00000000 * 00000000 = 00000000
(80000558) 00000000 * 00000000 = 00000000
(80000558) 00000000 * 00000000 = 00000000
----
******
@ -102012,6 +102162,9 @@ RF: Writing 0000001c to 28
******
(80000570) 00000021 * 00000022 = 00000462
(80000570) 00000021 * 00000022 = 00000462
(80000570) 00000021 * 00000022 = 00000462
(80000570) 00000021 * 00000022 = 00000462
(80000570) 00000021 * 00000022 = 00000462
----
******
[80000568] WB Data: 00000021 {babebabe}, to register: 1 [1 0]

BIN
rtl/obj_dir/test_bench.o
View file

Binary file not shown.