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two different versions of bypass connection

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This commit is contained in:
sij814 2024-09-19 13:21:14 -07:00
parent 48f86a48f6
commit 4fff940e42
1 changed files with 39 additions and 1 deletions
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40
hw/rtl/cache/VX_cache_wrap_l3.sv vendored
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@ -108,8 +108,9 @@ module VX_cache_wrap_l3 import VX_gpu_pkg::*; #(
) mem_bus_cache_if[NUM_MEM_PORTS]();
if (NC_OR_BYPASS) begin
`RESET_RELAY (nc_bypass_reset, reset);
// Slicing version
for (genvar i = 0; i < NUM_MEM_PORTS; ++i) begin
localparam SLICE_BEGIN = i * NUM_REQS_P;
@ -148,6 +149,43 @@ module VX_cache_wrap_l3 import VX_gpu_pkg::*; #(
);
end
// Connect everything
/*
for (genvar i = 0; i < NUM_MEM_PORTS; ++i) begin
VX_cache_bypass #(
.NUM_REQS (NUM_REQS),
.TAG_SEL_IDX (TAG_SEL_IDX),
.PASSTHRU (PASSTHRU),
.NC_ENABLE (PASSTHRU ? 0 : NC_ENABLE),
.WORD_SIZE (WORD_SIZE),
.LINE_SIZE (LINE_SIZE),
.CORE_ADDR_WIDTH (`CS_WORD_ADDR_WIDTH),
.CORE_TAG_WIDTH (TAG_WIDTH),
.MEM_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH),
.MEM_TAG_IN_WIDTH (CACHE_MEM_TAG_WIDTH),
.MEM_TAG_OUT_WIDTH (MEM_TAG_WIDTH),
.UUID_WIDTH (UUID_WIDTH),
.CORE_OUT_BUF (CORE_OUT_BUF),
.MEM_OUT_BUF (MEM_OUT_BUF)
) cache_bypass (
.clk (clk),
.reset (nc_bypass_reset),
.core_bus_in_if (core_bus_if),
.core_bus_out_if(core_bus_cache_if),
.mem_bus_in_if (mem_bus_cache_if[i]),
.mem_bus_out_if (mem_bus_if[i])
);
end
*/
end else begin
for (genvar i = 0; i < NUM_REQS; ++i) begin