cleanup multi-dimensional array to improve synthesis compatibility

hw/rtl/core/VX_operands.sv

@@ -69,7 +69,7 @@ module VX_operands import VX_gpu_pkg::*; #(
     wire pipe_valid_st2, pipe_ready_st2;
     wire [META_DATAW-1:0] pipe_data, pipe_data_st1, pipe_data_st2;
 
-    reg [NUM_SRC_OPDS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] src_data_st2, src_data_m_st2;
+    reg [NUM_SRC_OPDS-1:0][(`NUM_THREADS * `XLEN)-1:0] src_data_st2, src_data_m_st2;
 
     reg [NUM_SRC_OPDS-1:0] data_fetched_st1;
 

hw/rtl/fpu/VX_fpu_fpnew.sv

@@ -90,7 +90,7 @@ module VX_fpu_fpnew
 
     reg [TAG_WIDTH-1:0] fpu_tag_in, fpu_tag_out;
 
-    reg [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands;
+    logic [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands;
 
     wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result;
     fpnew_pkg::status_t fpu_status;

hw/rtl/libs/VX_mem_coalescer.sv

@@ -154,23 +154,27 @@ module VX_mem_coalescer #(
 
     wire [NUM_REQS-1:0] current_pmask = in_req_mask & addr_matches_r;
 
-    reg [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_SIZE-1:0] req_byteen_merged;
+    wire [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_SIZE-1:0] req_byteen_merged;
-    reg [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_WIDTH-1:0] req_data_merged;
+    wire [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_WIDTH-1:0] req_data_merged;
 
+    for (genvar i = 0; i < OUT_REQS; ++i) begin : g_data_merged
+        reg [DATA_RATIO-1:0][DATA_IN_SIZE-1:0] byteen_merged;
+        reg [DATA_RATIO-1:0][DATA_IN_WIDTH-1:0] data_merged;
         always @(*) begin
-        req_byteen_merged = '0;
+            byteen_merged = '0;
-        req_data_merged = 'x;
+            data_merged = 'x;
-        for (integer i = 0; i < OUT_REQS; ++i) begin
             for (integer j = 0; j < DATA_RATIO; ++j) begin
                 for (integer k = 0; k < DATA_IN_SIZE; ++k) begin
                     // perform byte-level merge since each thread may have different bytes enabled
                     if (current_pmask[i * DATA_RATIO + j] && in_req_byteen[DATA_RATIO * i + j][k]) begin
-                        req_byteen_merged[i][in_addr_offset[DATA_RATIO * i + j]][k] = 1'b1;
+                        byteen_merged[in_addr_offset[DATA_RATIO * i + j]][k] = 1'b1;
-                        req_data_merged[i][in_addr_offset[DATA_RATIO * i + j]][k * 8 +: 8] = in_req_data[DATA_RATIO * i + j][k * 8 +: 8];
+                        data_merged[in_addr_offset[DATA_RATIO * i + j]][k * 8 +: 8] = in_req_data[DATA_RATIO * i + j][k * 8 +: 8];
                     end
                 end
             end
         end
+        assign req_byteen_merged[i] = byteen_merged;
+        assign req_data_merged[i]   = data_merged;
     end
 
     wire is_last_batch = ~(| (in_req_mask & ~addr_matches_r & req_rem_mask_r));

hw/rtl/libs/VX_mem_scheduler.sv

@@ -459,8 +459,8 @@ module VX_mem_scheduler #(
 
     end else begin : g_rsp_full
 
-        reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
+        reg [(CORE_BATCHES * CORE_CHANNELS * WORD_WIDTH)-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
-        reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store_n; // use flattened array for BRAM synthesis compatibility
+        reg [(CORE_BATCHES * CORE_CHANNELS * WORD_WIDTH)-1:0] rsp_store_n; // use flattened array for BRAM synthesis compatibility
         reg [CORE_REQS-1:0] rsp_orig_mask [CORE_QUEUE_SIZE-1:0];
 
         always @(*) begin

hw/rtl/libs/VX_pe_serializer.sv

@@ -105,7 +105,7 @@ module VX_pe_serializer #(
             end
         end
 
-        reg [BATCH_SIZE-1:0][NUM_PES-1:0][DATA_OUT_WIDTH-1:0] data_out_r, data_out_n;
+        reg [BATCH_SIZE-1:0][(NUM_PES * DATA_OUT_WIDTH)-1:0] data_out_r, data_out_n;
 
         always @(*) begin
             data_out_n = data_out_r;