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minor update

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This commit is contained in:
Blaise Tine 2024-09-09 06:10:56 -07:00
parent b56aa00f4f
commit 63840a20da
4 changed files with 12 additions and 11 deletions
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3
hw/rtl/core/VX_schedule.sv
View file

@ -334,7 +334,8 @@ module VX_schedule import VX_gpu_pkg::*; #(
wire [`UUID_WIDTH-1:0] instr_uuid;
`ifndef NDEBUG
VX_uuid_gen #(
.CORE_ID (CORE_ID)
.CORE_ID (CORE_ID),
.UUID_WIDTH (`UUID_WIDTH)
) uuid_gen (
.clk (clk),
.reset (reset),

7
hw/rtl/core/VX_uuid_gen.sv
View file

@ -14,15 +14,16 @@
`include "VX_define.vh"
module VX_uuid_gen import VX_gpu_pkg::*; #(
parameter CORE_ID = 0
parameter CORE_ID = 0,
parameter UUID_WIDTH = 48
) (
input wire clk,
input wire reset,
input wire incr,
input wire [`NW_WIDTH-1:0] wid,
output wire [`UUID_WIDTH-1:0] uuid
output wire [UUID_WIDTH-1:0] uuid
);
localparam GNW_WIDTH = `UUID_WIDTH - 32;
localparam GNW_WIDTH = UUID_WIDTH - 32;
reg [31:0] uuid_cntrs [0:`NUM_WARPS-1];
reg [`NUM_WARPS-1:0] has_uuid_cntrs;

2
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -90,7 +90,7 @@ module VX_generic_arbiter #(
end
`RUNTIME_ASSERT ((~(| requests) || (grant_valid && (requests[grant_index] != 0) && (grant_onehot == (NUM_REQS'(1) << grant_index)))), ("%t: invalid arbiter grant!", $time))
`RUNTIME_ASSERT (((~(| requests) != 1) || (grant_valid && (requests[grant_index] != 0) && (grant_onehot == (NUM_REQS'(1) << grant_index)))), ("%t: invalid arbiter grant!", $time))
endmodule
`TRACING_ON

11
hw/rtl/libs/VX_mem_scheduler.sv
View file

@ -96,9 +96,8 @@ module VX_mem_scheduler #(
`STATIC_ASSERT (`IS_DIVISBLE(CORE_REQS * WORD_SIZE, LINE_SIZE), ("invalid parameter"))
`STATIC_ASSERT ((TAG_WIDTH >= UUID_WIDTH), ("invalid parameter"))
`STATIC_ASSERT ((0 == RSP_PARTIAL) || (1 == RSP_PARTIAL), ("invalid parameter"))
`RUNTIME_ASSERT((~core_req_valid || core_req_mask != 0), ("%t: invalid request mask", $time))
wire ibuf_push;
wire ibuf_pop;
wire [CORE_QUEUE_ADDRW-1:0] ibuf_waddr;
@ -435,7 +434,7 @@ module VX_mem_scheduler #(
end
end
if (RSP_PARTIAL == 1) begin
if (RSP_PARTIAL != 0) begin
reg [CORE_QUEUE_SIZE-1:0] rsp_sop_r;
@ -462,14 +461,14 @@ module VX_mem_scheduler #(
end else begin
reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store_n;
reg [CORE_BATCHES-1:00][CORE_CHANNELS-1:0][WORD_WIDTH-1:0] rsp_store_n;
reg [CORE_REQS-1:0] rsp_orig_mask [CORE_QUEUE_SIZE-1:0];
always @(*) begin
rsp_store_n = rsp_store[ibuf_raddr];
for (integer i = 0; i < CORE_CHANNELS; ++i) begin
if ((CORE_CHANNELS == 1) || mem_rsp_mask_s[i]) begin
rsp_store_n[(rsp_batch_idx * CORE_CHANNELS + i) * WORD_WIDTH +: WORD_WIDTH] = mem_rsp_data_s[i];
rsp_store_n[rsp_batch_idx][i] = mem_rsp_data_s[i];
end
end
end
@ -490,7 +489,7 @@ module VX_mem_scheduler #(
for (genvar r = 0; r < CORE_REQS; ++r) begin
localparam i = r / CORE_CHANNELS;
localparam j = r % CORE_CHANNELS;
assign crsp_data[r] = rsp_store_n[(i * CORE_CHANNELS + j) * WORD_WIDTH +: WORD_WIDTH];
assign crsp_data[r] = rsp_store_n[i][j];
end
assign mem_rsp_ready_s = crsp_ready || ~rsp_complete;