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scope taps annotation

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This commit is contained in:
Blaise Tine 2024-09-19 23:33:23 -07:00
parent d2db612bb4
commit 63cce35c1a
10 changed files with 72 additions and 33 deletions
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3
ci/regression.sh.in
View file

@ -306,7 +306,8 @@ debug()
CONFIGS="-O0 -DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=xrt --cores=2 --clusters=2 --l2cache --debug=1 --perf=1 --app=demo --args="-n1"
CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --debug=1 --perf=1 --app=demo --args="-n1"
./ci/blackbox.sh --driver=opae --scope --app=demo --args="-n1"
./ci/blackbox.sh --driver=xrt --scope --app=demo --args="-n1"
echo "debugging tests done!"
}

3
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -1016,7 +1016,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
VX_scope_tap #(
.SCOPE_ID (0),
.TRIGGERW (24),
.PROBEW (431)
.PROBEW (431),
.DEPTH (4096)
) scope_tap (
.clk(clk),
.reset(scope_reset_w[0]),

26
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -310,15 +310,35 @@ module VX_afu_wrap #(
interrupt, \
vx_busy_wait, \
vx_busy, \
vx_reset \
vx_reset, \
m_axi_mem_awvalid_a, \
m_axi_mem_awready_a, \
m_axi_mem_wvalid_a, \
m_axi_mem_wready_a, \
m_axi_mem_bvalid_a, \
m_axi_mem_bready_a, \
m_axi_mem_arvalid_a, \
m_axi_mem_arready_a, \
m_axi_mem_rvalid_a, \
m_axi_mem_rready_a, \
dcr_wr_valid \
}
`define PROBES { \
vx_pending_writes \
vx_pending_writes, \
m_axi_mem_awaddr_u, \
m_axi_mem_awid_a, \
m_axi_mem_bid_a, \
m_axi_mem_araddr_u, \
m_axi_mem_arid_a, \
m_axi_mem_rid_a, \
dcr_wr_addr, \
dcr_wr_data \
}
VX_scope_tap #(
.SCOPE_ID (0),
.TRIGGERW ($bits(`TRIGGERS)),
.PROBEW ($bits(`PROBES))
.PROBEW ($bits(`PROBES)),
.DEPTH (4096)
) scope_tap (
.clk (clk),
.reset (scope_reset_w[0]),

11
hw/rtl/core/VX_fetch.sv
View file

@ -41,7 +41,11 @@ module VX_fetch import VX_gpu_pkg::*; #(
wire [`UUID_WIDTH-1:0] rsp_uuid;
wire [`NW_WIDTH-1:0] req_tag, rsp_tag;
wire schedule_fire = schedule_if.valid && schedule_if.ready;
wire icache_req_fire = icache_req_valid && icache_req_ready;
wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
`UNUSED_VAR (schedule_fire)
`UNUSED_VAR (icache_rsp_fire)
assign req_tag = schedule_if.data.wid;
@ -133,14 +137,13 @@ module VX_fetch import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_FETCH
`ifdef SCOPE
wire schedule_fire = schedule_if.valid && schedule_if.ready;
wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
VX_scope_tap #(
.SCOPE_ID (1),
.TRIGGERW (4),
.PROBEW (`UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `PC_BITS +
.PROBEW (`UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `PC_BITS +
ICACHE_TAG_WIDTH + ICACHE_WORD_SIZE + ICACHE_ADDR_WIDTH +
(ICACHE_WORD_SIZE*8) + ICACHE_TAG_WIDTH)
(ICACHE_WORD_SIZE * 8) + ICACHE_TAG_WIDTH),
.DEPTH (4096)
) scope_tap (
.clk (clk),
.reset (scope_reset),

19
hw/rtl/core/VX_issue_slice.sv
View file

@ -36,6 +36,11 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
VX_scoreboard_if scoreboard_if();
VX_operands_if operands_if();
wire operands_if_fire = operands_if.valid && operands_if.ready;
wire writeback_if_valid = writeback_if.valid;
`UNUSED_VAR (operands_if_fire)
`UNUSED_VAR (writeback_if_valid)
VX_ibuffer #(
.INSTANCE_ID ($sformatf("%s-ibuffer", INSTANCE_ID))
) ibuffer (
@ -90,24 +95,20 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_ISSUE
`ifdef SCOPE
wire operands_if_fire = operands_if.valid && operands_if.ready;
wire operands_if_not_ready = ~operands_if.ready;
wire writeback_if_valid = writeback_if.valid;
VX_scope_tap #(
.SCOPE_ID (2),
.TRIGGERW (4),
.PROBEW (`UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS +
.TRIGGERW (2),
.PROBEW (`UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS +
1 + `NR_BITS + (`NUM_THREADS * 3 * `XLEN) +
`UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1)
`UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1),
.DEPTH (4096)
) scope_tap (
.clk (clk),
.reset (scope_reset),
.start (1'b0),
.stop (1'b0),
.triggers ({
reset,
operands_if_fire,
operands_if_not_ready,
writeback_if_valid
}),
.probes ({
@ -145,7 +146,7 @@ module VX_issue_slice import VX_gpu_pkg::*; #(
`ifdef DBG_TRACE_PIPELINE
always @(posedge clk) begin
if (operands_if.valid && operands_if.ready) begin
if (operands_if_fire) begin
`TRACE(1, ("%t: %s: wid=%0d, PC=0x%0h, ex=", $time, INSTANCE_ID, wis_to_wid(operands_if.data.wis, ISSUE_ID), {operands_if.data.PC, 1'b0}))
trace_ex_type(1, operands_if.data.ex_type);
`TRACE(1, (", op="))

22
hw/rtl/core/VX_lsu_slice.sv
View file

@ -536,17 +536,31 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_LSU
`ifdef SCOPE
`define TRIGGERS { \
mem_req_fire, \
mem_rsp_fire \
}
`define PROBES { \
mem_req_rw, \
full_addr, \
mem_req_byteen, \
mem_req_data, \
execute_if.data.uuid, \
rsp_data, \
rsp_uuid \
}
VX_scope_tap #(
.SCOPE_ID (3),
.TRIGGERW (3),
.PROBEW (1 + NUM_LANES*(`XLEN + LSU_WORD_SIZE + LSU_WORD_SIZE*8) + `UUID_WIDTH + NUM_LANES*LSU_WORD_SIZE*8 + `UUID_WIDTH)
.TRIGGERW (2),
.PROBEW (1 + NUM_LANES * (`XLEN + LSU_WORD_SIZE + LSU_WORD_SIZE * 8) + `UUID_WIDTH + NUM_LANES * LSU_WORD_SIZE * 8 + `UUID_WIDTH),
.DEPTH (4096)
) scope_tap (
.clk (clk),
.reset (scope_reset),
.start (1'b0),
.stop (1'b0),
.triggers({reset, mem_req_fire, mem_rsp_fire}),
.probes ({mem_req_rw, full_addr, mem_req_byteen, mem_req_data, execute_if.data.uuid, rsp_data, rsp_uuid}),
.triggers(`TRIGGERS),
.probes (`PROBES),
.bus_in (scope_bus_in),
.bus_out(scope_bus_out)
);

10
hw/rtl/libs/VX_scope_tap.sv
View file

@ -19,7 +19,7 @@ module VX_scope_tap #(
parameter SCOPE_IDW = 8, // scope identifier width
parameter TRIGGERW = 0, // trigger signals width
parameter PROBEW = 0, // probe signal width
parameter SIZE = 256, // trace buffer size
parameter DEPTH = 256, // trace buffer depth
parameter IDLE_CTRW = 16 // idle time between triggers counter width
) (
input wire clk,
@ -35,7 +35,7 @@ module VX_scope_tap #(
localparam TX_DATA_BITS = `LOG2UP(TX_DATAW);
localparam DATAW = PROBEW + TRIGGERW;
localparam DATA_BITS = `LOG2UP(DATAW);
localparam ADDRW = `CLOG2(SIZE);
localparam ADDRW = `CLOG2(DEPTH);
localparam TRIGGER_ENABLE = (TRIGGERW != 0);
localparam MAX_IDLE_CTR = (2 ** IDLE_CTRW) - 1;
@ -64,8 +64,8 @@ module VX_scope_tap #(
localparam GET_TYPE_DATA = 2'd3;
localparam GET_TYPE_BITS = 2;
`NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [SIZE-1:0];
`NO_RW_RAM_CHECK reg [IDLE_CTRW-1:0] delta_store [SIZE-1:0];
`NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [DEPTH-1:0];
`NO_RW_RAM_CHECK reg [IDLE_CTRW-1:0] delta_store [DEPTH-1:0];
reg [TRIGGERW-1:0] prev_triggers;
reg [IDLE_CTRW-1:0] delta;
@ -216,7 +216,7 @@ module VX_scope_tap #(
ctrl_state <= CTRL_STATE_IDLE;
cmd_start <= 0;
start_delay <= '0;
waddr_end <= ADDRW'(SIZE-1);
waddr_end <= ADDRW'(DEPTH-1);
bus_out_r <= 0;
end else begin
bus_out_r <= 0;

5
runtime/xrt/vortex.cpp
View file

@ -757,7 +757,7 @@ private:
if (pOff) {
*pOff = offset;
}
printf("get_bank_info(addr=0x%lx, bank=%d, offset=0x%lx\n", addr, index, offset);
//printf("get_bank_info(addr=0x%lx, bank=%d, offset=0x%lx\n", addr, index, offset);
return 0;
}
@ -792,8 +792,7 @@ private:
if (pOff) {
*pOff = offset;
}
printf("get_bank_info(addr=0x%lx, bank=%d, offset=0x%lx\n", addr, index,
offset);
//printf("get_bank_info(addr=0x%lx, bank=%d, offset=0x%lx\n", addr, index, offset);
return 0;
}

2
tests/unittest/common.mk
View file

@ -2,7 +2,7 @@
ROOT_DIR := $(realpath ../../..)
CXXFLAGS += -std=c++11 -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -I$(VORTEX_HOME)/runtime/common
CXXFLAGS += -I$(VORTEX_HOME)/sim/common
# Debugging
ifdef DEBUG

4
tests/unittest/vx_malloc/main.cpp
View file

@ -1,4 +1,4 @@
#include <malloc.h>
#include <mem_alloc.h>
#include <stdio.h>
#define RT_CHECK(_expr) \
@ -12,7 +12,7 @@
static uint64_t minAddress = 0;
static uint64_t maxAddress = 0xffffffff;
static uint32_t pageAlign = 4096;
static uint32_t pageAlign = 4096;
static uint32_t blockAlign = 64;
int main() {