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https://github.com/vortexgpgpu/vortex.git
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adding scope support to xrtsim
This commit is contained in:
Blaise Tine
parent
2d7f9eae0a
commit
d2db612bb4
8 changed files with 155 additions and 109 deletions
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -24,7 +24,7 @@
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`define SCOPE_IO_SWITCH(__count) \
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wire scope_bus_in_w [__count]; \
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wire scope_bus_out_w [__count]; \
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`RESET_RELAY_EX(scope_reset_w, scope_reset, __count, 4); \
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`RESET_RELAY_EX(scope_reset_w, scope_reset, __count, `MAX_FANOUT); \
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VX_scope_switch #( \
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.N (__count) \
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) scope_switch ( \
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@ -175,7 +175,6 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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cmd_scope_reading <= 1;
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scope_bus_ctr <= 63;
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end
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scope_bus_in <= 0;
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if (cp2af_sRxPort.c0.mmioWrValid
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&& (MMIO_SCOPE_WRITE == mmio_req_hdr.address)) begin
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cmd_scope_wdata <= 64'(cp2af_sRxPort.c0.data);
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@ -189,6 +188,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_writing <= 0;
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scope_bus_in <= 0;
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end
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end
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if (cmd_scope_reading) begin
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@ -132,13 +132,16 @@ module VX_afu_ctrl #(
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ADDR_BITS = 8;
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localparam
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WSTATE_IDLE = 2'd0,
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WSTATE_ADDR = 2'd0,
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WSTATE_DATA = 2'd1,
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WSTATE_RESP = 2'd2;
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WSTATE_RESP = 2'd2,
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WSTATE_WIDTH = 2;
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localparam
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RSTATE_IDLE = 2'd0,
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RSTATE_DATA = 2'd1;
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RSTATE_ADDR = 2'd0,
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RSTATE_DATA = 2'd1,
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RSTATE_RESP = 2'd2,
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RSTATE_WIDTH = 2;
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// device caps
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wire [63:0] dev_caps = {16'b0,
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@ -152,16 +155,18 @@ module VX_afu_ctrl #(
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2'(`CLOG2(`XLEN)-4),
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30'(`MISA_STD)};
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reg [1:0] wstate;
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reg [WSTATE_WIDTH-1:0] wstate;
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reg [ADDR_BITS-1:0] waddr;
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wire [31:0] wmask;
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wire s_axi_aw_fire;
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wire s_axi_w_fire;
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wire s_axi_b_fire;
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reg [1:0] rstate;
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logic [RSTATE_WIDTH-1:0] rstate;
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reg [31:0] rdata;
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wire [ADDR_BITS-1:0] raddr;
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reg [ADDR_BITS-1:0] raddr;
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wire s_axi_ar_fire;
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wire s_axi_r_fire;
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reg ap_reset_r;
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reg ap_start_r;
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@ -174,15 +179,19 @@ module VX_afu_ctrl #(
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reg [31:0] dcrv_r;
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reg dcr_wr_valid_r;
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logic wready_stall;
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logic rvalid_stall;
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`ifdef SCOPE
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reg [63:0] scope_bus_wdata;
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reg [63:0] scope_bus_rdata;
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reg [63:0] scope_bus_wdata, scope_bus_rdata;
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reg [5:0] scope_bus_ctr;
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reg cmd_scope_reading;
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reg cmd_scope_writing;
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reg cmd_scope_writing, cmd_scope_reading;
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reg scope_bus_out_r;
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reg scope_rdata_valid;
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reg is_scope_waddr, is_scope_raddr;
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always @(posedge clk) begin
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if (reset) begin
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@ -190,18 +199,33 @@ module VX_afu_ctrl #(
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cmd_scope_writing <= 0;
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scope_bus_ctr <= '0;
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scope_bus_out_r <= 0;
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is_scope_waddr <= 0;
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is_scope_raddr <= 0;
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scope_bus_rdata <= '0;
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scope_rdata_valid <= 0;
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end else begin
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if (s_axi_aw_fire) begin
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is_scope_waddr <= (s_axi_awaddr[ADDR_BITS-1:0] == ADDR_SCP_0)
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|| (s_axi_awaddr[ADDR_BITS-1:0] == ADDR_SCP_1);
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end
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if (s_axi_ar_fire) begin
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is_scope_raddr <= (s_axi_araddr[ADDR_BITS-1:0] == ADDR_SCP_0)
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|| (s_axi_araddr[ADDR_BITS-1:0] == ADDR_SCP_1);
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end
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if (s_axi_w_fire && waddr == ADDR_SCP_0) begin
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scope_bus_wdata[31:0] <= (s_axi_wdata & wmask) | (scope_bus_wdata[31:0] & ~wmask);
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end
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if (s_axi_w_fire && waddr == ADDR_SCP_1) begin
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scope_bus_wdata[63:32] <= (s_axi_wdata & wmask) | (scope_bus_wdata[63:32] & ~wmask);
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cmd_scope_writing <= 1;
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scope_rdata_valid <= 0;
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scope_bus_out_r <= 1;
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scope_bus_ctr <= 63;
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end
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if (scope_bus_in) begin
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cmd_scope_reading <= 1;
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scope_bus_rdata <= '0;
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scope_bus_ctr <= 63;
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end
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if (cmd_scope_reading) begin
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@ -209,6 +233,7 @@ module VX_afu_ctrl #(
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_reading <= 0;
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scope_rdata_valid <= 1;
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end
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end
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if (cmd_scope_writing) begin
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@ -216,6 +241,7 @@ module VX_afu_ctrl #(
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_writing <= 0;
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scope_bus_out_r <= '0;
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end
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end
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end
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@ -223,40 +249,51 @@ module VX_afu_ctrl #(
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assign scope_bus_out = scope_bus_out_r;
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assign wready_stall = is_scope_waddr && cmd_scope_writing;
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assign rvalid_stall = is_scope_raddr && ~scope_rdata_valid;
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`else
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assign wready_stall = 0;
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assign rvalid_stall = 0;
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`endif
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// AXI Write
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// AXI Write Request
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assign s_axi_awready = (wstate == WSTATE_ADDR);
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assign s_axi_wready = (wstate == WSTATE_DATA) && ~wready_stall;
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assign s_axi_awready = (wstate == WSTATE_IDLE);
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assign s_axi_wready = (wstate == WSTATE_DATA);
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// AXI Write Response
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assign s_axi_bvalid = (wstate == WSTATE_RESP);
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assign s_axi_bresp = 2'b00; // OKAY
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assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready;
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assign s_axi_w_fire = s_axi_wvalid && s_axi_wready;
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for (genvar i = 0; i < 4; ++i) begin : g_wmask
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assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}};
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end
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assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready;
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assign s_axi_w_fire = s_axi_wvalid && s_axi_wready;
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assign s_axi_b_fire = s_axi_bvalid && s_axi_bready;
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// wstate
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always @(posedge clk) begin
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if (reset) begin
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wstate <= WSTATE_IDLE;
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wstate <= WSTATE_ADDR;
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end else begin
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case (wstate)
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WSTATE_IDLE: wstate <= s_axi_awvalid ? WSTATE_DATA : WSTATE_IDLE;
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WSTATE_DATA: wstate <= s_axi_wvalid ? WSTATE_RESP : WSTATE_DATA;
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WSTATE_RESP: wstate <= s_axi_bready ? WSTATE_IDLE : WSTATE_RESP;
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default: wstate <= WSTATE_IDLE;
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WSTATE_ADDR: wstate <= s_axi_aw_fire ? WSTATE_DATA : WSTATE_ADDR;
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WSTATE_DATA: wstate <= s_axi_w_fire ? WSTATE_RESP : WSTATE_DATA;
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WSTATE_RESP: wstate <= s_axi_b_fire ? WSTATE_ADDR : WSTATE_RESP;
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default: wstate <= WSTATE_ADDR;
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endcase
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end
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end
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// waddr
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always @(posedge clk) begin
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if (s_axi_aw_fire)
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if (s_axi_aw_fire) begin
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waddr <= s_axi_awaddr[ADDR_BITS-1:0];
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end
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end
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// wdata
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@ -335,73 +372,80 @@ module VX_afu_ctrl #(
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end
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end
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// AXI Read
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// AXI Read Request
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assign s_axi_arready = (rstate == RSTATE_ADDR);
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assign s_axi_arready = (rstate == RSTATE_IDLE);
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assign s_axi_rvalid = (rstate == RSTATE_DATA);
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// AXI Read Response
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assign s_axi_rvalid = (rstate == RSTATE_RESP);
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assign s_axi_rdata = rdata;
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assign s_axi_rresp = 2'b00; // OKAY
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assign s_axi_ar_fire = s_axi_arvalid && s_axi_arready;
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assign raddr = s_axi_araddr[ADDR_BITS-1:0];
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assign s_axi_r_fire = s_axi_rvalid && s_axi_rready;
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// rstate
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always @(posedge clk) begin
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if (reset) begin
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rstate <= RSTATE_IDLE;
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rstate <= RSTATE_ADDR;
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end else begin
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case (rstate)
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RSTATE_IDLE: rstate <= s_axi_arvalid ? RSTATE_DATA : RSTATE_IDLE;
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RSTATE_DATA: rstate <= (s_axi_rready & s_axi_rvalid) ? RSTATE_IDLE : RSTATE_DATA;
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default: rstate <= RSTATE_IDLE;
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RSTATE_ADDR: rstate <= s_axi_ar_fire ? RSTATE_DATA : RSTATE_ADDR;
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RSTATE_DATA: rstate <= (~rvalid_stall) ? RSTATE_RESP : RSTATE_DATA;
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RSTATE_RESP: rstate <= s_axi_r_fire ? RSTATE_ADDR : RSTATE_RESP;
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default: rstate <= RSTATE_ADDR;
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endcase
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end
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end
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// raddr
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always @(posedge clk) begin
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if (s_axi_ar_fire) begin
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raddr <= s_axi_araddr[ADDR_BITS-1:0];
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end
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end
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// rdata
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always @(posedge clk) begin
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if (s_axi_ar_fire) begin
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rdata <= '0;
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case (raddr)
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ADDR_AP_CTRL: begin
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rdata[0] <= ap_start_r;
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rdata[1] <= ap_done;
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rdata[2] <= ap_idle;
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rdata[3] <= ap_ready;
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rdata[7] <= auto_restart_r;
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end
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ADDR_GIE: begin
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rdata <= 32'(gie_r);
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end
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ADDR_IER: begin
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rdata <= 32'(ier_r);
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end
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ADDR_ISR: begin
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rdata <= 32'(isr_r);
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end
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ADDR_DEV_0: begin
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rdata <= dev_caps[31:0];
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end
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ADDR_DEV_1: begin
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rdata <= dev_caps[63:32];
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end
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ADDR_ISA_0: begin
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rdata <= isa_caps[31:0];
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end
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ADDR_ISA_1: begin
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rdata <= isa_caps[63:32];
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end
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`ifdef SCOPE
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ADDR_SCP_0: begin
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rdata <= scope_bus_rdata[31:0];
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end
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ADDR_SCP_1: begin
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rdata <= scope_bus_rdata[63:32];
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end
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`endif
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default:;
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endcase
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end
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rdata <= '0;
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case (raddr)
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ADDR_AP_CTRL: begin
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rdata[0] <= ap_start_r;
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rdata[1] <= ap_done;
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rdata[2] <= ap_idle;
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rdata[3] <= ap_ready;
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rdata[7] <= auto_restart_r;
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end
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ADDR_GIE: begin
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rdata <= 32'(gie_r);
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end
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ADDR_IER: begin
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rdata <= 32'(ier_r);
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end
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ADDR_ISR: begin
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rdata <= 32'(isr_r);
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end
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ADDR_DEV_0: begin
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rdata <= dev_caps[31:0];
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end
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ADDR_DEV_1: begin
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rdata <= dev_caps[63:32];
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end
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ADDR_ISA_0: begin
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rdata <= isa_caps[31:0];
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end
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ADDR_ISA_1: begin
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rdata <= isa_caps[63:32];
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end
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`ifdef SCOPE
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ADDR_SCP_0: begin
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rdata <= scope_bus_rdata[31:0];
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end
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ADDR_SCP_1: begin
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rdata <= scope_bus_rdata[63:32];
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end
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`endif
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default:;
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endcase
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end
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assign ap_reset = ap_reset_r;
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@ -194,11 +194,10 @@ public:
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return device->api_.fpgaReadMMIO64(device->fpga_, 0, MMIO_SCOPE_READ, value);
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};
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int ret = vx_scope_start(&callback, this, 0, -1);
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if (ret != 0) {
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CHECK_ERR(vx_scope_start(&callback, this, 0, -1), {
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api_.fpgaClose(fpga_);
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return ret;
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}
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return err;
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});
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}
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#endif
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return 0;
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@ -375,11 +375,9 @@ public:
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*value = (((uint64_t)value_hi) << 32) | value_lo;
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return 0;
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};
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int ret = vx_scope_start(&callback, device, 0, -1);
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if (ret != 0) {
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delete device;
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return ret;
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}
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CHECK_ERR(vx_scope_start(&callback, this, 0, -1), {
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return err;
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});
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}
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#endif
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@ -217,6 +217,8 @@ public:
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}
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int mem_write(uint32_t bank_id, uint64_t addr, uint64_t size, const void* data) {
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std::lock_guard<std::mutex> guard(mutex_);
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if (bank_id >= M_AXI_MEM_NUM_BANKS)
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return -1;
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uint64_t base_addr = uint64_t(bank_id) * MEM_BANK_SIZE + addr;
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@ -230,6 +232,8 @@ public:
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}
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int mem_read(uint32_t bank_id, uint64_t addr, uint64_t size, void* data) {
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std::lock_guard<std::mutex> guard(mutex_);
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if (bank_id >= M_AXI_MEM_NUM_BANKS)
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return -1;
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uint64_t base_addr = uint64_t(bank_id) * MEM_BANK_SIZE + addr;
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@ -246,56 +250,57 @@ public:
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std::lock_guard<std::mutex> guard(mutex_);
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// write address
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//printf("%0ld: [sim] register_write: address=0x%x\n", timestamp, offset);
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device_->s_axi_ctrl_awvalid = 1;
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device_->s_axi_ctrl_awaddr = offset;
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auto s_axi_ctrl_awready = device_->s_axi_ctrl_awready;
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do {
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while (!device_->s_axi_ctrl_awready)
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this->tick();
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} while (!(s_axi_ctrl_awready || device_->s_axi_ctrl_awready));
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this->tick();
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device_->s_axi_ctrl_awvalid = 0;
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// write data
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//printf("%0ld: [sim] register_write: data=0x%x\n", timestamp, value);
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device_->s_axi_ctrl_wvalid = 1;
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device_->s_axi_ctrl_wdata = value;
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device_->s_axi_ctrl_wstrb = 0xf;
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auto s_axi_ctrl_wready = device_->s_axi_ctrl_wready;
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do {
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while (!device_->s_axi_ctrl_wready)
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this->tick();
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} while (!(s_axi_ctrl_wready || device_->s_axi_ctrl_wready));
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this->tick();
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device_->s_axi_ctrl_wvalid = 0;
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// write response
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device_->s_axi_ctrl_bready = 1;
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auto s_axi_ctrl_bvalid = device_->s_axi_ctrl_bvalid;
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//printf("%0ld: [sim] register_write: response\n", timestamp);
|
||||
do {
|
||||
this->tick();
|
||||
} while (!(s_axi_ctrl_bvalid || device_->s_axi_ctrl_bvalid));
|
||||
} while (!device_->s_axi_ctrl_bvalid);
|
||||
device_->s_axi_ctrl_bready = 1;
|
||||
this->tick();
|
||||
device_->s_axi_ctrl_bready = 0;
|
||||
|
||||
//printf("%0ld: [sim] register_write: done\n", timestamp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int register_read(uint32_t offset, uint32_t* value) {
|
||||
std::lock_guard<std::mutex> guard(mutex_);
|
||||
|
||||
// read address
|
||||
//printf("%0ld: [sim] register_read: address=0x%x\n", timestamp, offset);
|
||||
device_->s_axi_ctrl_arvalid = 1;
|
||||
device_->s_axi_ctrl_araddr = offset;
|
||||
auto s_axi_ctrl_arready = device_->s_axi_ctrl_arready;
|
||||
do {
|
||||
while (!device_->s_axi_ctrl_arready)
|
||||
this->tick();
|
||||
} while (!(s_axi_ctrl_arready || device_->s_axi_ctrl_arready));
|
||||
this->tick();
|
||||
device_->s_axi_ctrl_arvalid = 0;
|
||||
|
||||
// read data
|
||||
device_->s_axi_ctrl_rready = 1;
|
||||
auto s_axi_ctrl_rvalid = device_->s_axi_ctrl_rvalid;
|
||||
// read response
|
||||
//printf("%0ld: [sim] register_read: response\n", timestamp);
|
||||
do {
|
||||
this->tick();
|
||||
} while (!(s_axi_ctrl_rvalid || device_->s_axi_ctrl_rvalid));
|
||||
} while (!device_->s_axi_ctrl_rvalid);
|
||||
*value = device_->s_axi_ctrl_rdata;
|
||||
device_->s_axi_ctrl_rready = 1;
|
||||
this->tick();
|
||||
device_->s_axi_ctrl_rready = 0;
|
||||
|
||||
//printf("%0ld: [sim] register_read: done (value=0x%x)\n", timestamp, *value);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -102,9 +102,9 @@ run-opae: $(PROJECT) $(KERNEL_SRCS)
|
|||
|
||||
run-xrt: $(PROJECT) $(KERNEL_SRCS)
|
||||
ifeq ($(TARGET), hw)
|
||||
XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_PATH)/lib:$(VORTEX_RT_PATH):$(LLVM_VORTEX)/lib:$(LD_LIBRARY_PATH) $(POCL_CC_FLAGS) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
SCOPE_JSON_PATH=$(VORTEX_RT_PATH)/scope.json XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_PATH)/lib:$(VORTEX_RT_PATH):$(LLVM_VORTEX)/lib:$(LD_LIBRARY_PATH) $(POCL_CC_FLAGS) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
else
|
||||
XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_PATH)/lib:$(VORTEX_RT_PATH):$(LLVM_VORTEX)/lib:$(LD_LIBRARY_PATH) $(POCL_CC_FLAGS) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
SCOPE_JSON_PATH=$(VORTEX_RT_PATH)/scope.json XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_PATH)/lib:$(VORTEX_RT_PATH):$(LLVM_VORTEX)/lib:$(LD_LIBRARY_PATH) $(POCL_CC_FLAGS) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
endif
|
||||
|
||||
.depend: $(SRCS)
|
||||
|
|
|
|||
|
|
@ -99,9 +99,9 @@ run-opae: $(PROJECT) kernel.vxbin
|
|||
|
||||
run-xrt: $(PROJECT) kernel.vxbin
|
||||
ifeq ($(TARGET), hw)
|
||||
XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH):$(LD_LIBRARY_PATH) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
SCOPE_JSON_PATH=$(VORTEX_RT_PATH)/scope.json XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH):$(LD_LIBRARY_PATH) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
else
|
||||
XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH):$(LD_LIBRARY_PATH) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
SCOPE_JSON_PATH=$(VORTEX_RT_PATH)/scope.json XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(VORTEX_RT_PATH)/xrt/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=$(XRT_DEVICE_INDEX) XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH):$(LD_LIBRARY_PATH) VORTEX_DRIVER=xrt ./$(PROJECT) $(OPTS)
|
||||
endif
|
||||
|
||||
.depend: $(SRCS)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue