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renamed memory and cache request interfaces

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This commit is contained in:
Blaise Tine 2023-06-22 09:53:03 -04:00
parent e8e3ce6a4d
commit cf77b7d85c
30 changed files with 698 additions and 1073 deletions
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86
hw/rtl/VX_cluster.sv
View file

@ -61,8 +61,7 @@ module VX_cluster #(
`endif
// Memory
VX_mem_req_if.master mem_req_if,
VX_mem_rsp_if.slave mem_rsp_if,
VX_mem_bus_if.master mem_bus_if,
// simulation helper signals
output wire sim_ebreak,
@ -106,17 +105,11 @@ module VX_cluster #(
`PERF_RASTER_ADD (perf_raster_if, perf_raster_unit_if, `NUM_RASTER_UNITS);
`endif
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (RCACHE_NUM_REQS),
.WORD_SIZE (RCACHE_WORD_SIZE),
.TAG_WIDTH (RCACHE_TAG_WIDTH)
) rcache_req_if[`NUM_RASTER_UNITS]();
VX_cache_rsp_if #(
.NUM_REQS (RCACHE_NUM_REQS),
.WORD_SIZE (RCACHE_WORD_SIZE),
.TAG_WIDTH (RCACHE_TAG_WIDTH)
) rcache_rsp_if[`NUM_RASTER_UNITS]();
) rcache_bus_if[`NUM_RASTER_UNITS]();
VX_raster_req_if #(
.NUM_LANES (`NUM_THREADS)
@ -153,8 +146,7 @@ module VX_cluster #(
`endif
.dcr_write_if (raster_dcr_write_if),
.raster_req_if (raster_req_if[i]),
.cache_req_if (rcache_req_if[i]),
.cache_rsp_if (rcache_rsp_if[i])
.cache_bus_if (rcache_bus_if[i])
);
end
@ -185,17 +177,11 @@ module VX_cluster #(
`PERF_ROP_ADD (perf_rop_if, perf_rop_unit_if, `NUM_ROP_UNITS);
`endif
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (OCACHE_NUM_REQS),
.WORD_SIZE (OCACHE_WORD_SIZE),
.TAG_WIDTH (OCACHE_TAG_WIDTH)
) ocache_req_if[`NUM_ROP_UNITS]();
VX_cache_rsp_if #(
.NUM_REQS (OCACHE_NUM_REQS),
.WORD_SIZE (OCACHE_WORD_SIZE),
.TAG_WIDTH (OCACHE_TAG_WIDTH)
) ocache_rsp_if[`NUM_ROP_UNITS]();
) ocache_bus_if[`NUM_ROP_UNITS]();
VX_rop_req_if #(
.NUM_LANES (`NUM_THREADS)
@ -243,8 +229,7 @@ module VX_cluster #(
`endif
.dcr_write_if (rop_dcr_write_if),
.rop_req_if (rop_req_if[i]),
.cache_req_if (ocache_req_if[i]),
.cache_rsp_if (ocache_rsp_if[i])
.cache_bus_if (ocache_bus_if[i])
);
end
@ -257,17 +242,11 @@ module VX_cluster #(
`PERF_TEX_ADD (perf_tex_if, perf_tex_unit_if, `NUM_TEX_UNITS);
`endif
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (TCACHE_NUM_REQS),
.WORD_SIZE (TCACHE_WORD_SIZE),
.TAG_WIDTH (TCACHE_TAG_WIDTH)
) tcache_req_if[`NUM_TEX_UNITS]();
VX_cache_rsp_if #(
.NUM_REQS (TCACHE_NUM_REQS),
.WORD_SIZE (TCACHE_WORD_SIZE),
.TAG_WIDTH (TCACHE_TAG_WIDTH)
) tcache_rsp_if[`NUM_TEX_UNITS]();
) tcache_bus_if[`NUM_TEX_UNITS]();
VX_tex_req_if #(
.NUM_LANES (`NUM_THREADS),
@ -332,8 +311,7 @@ module VX_cluster #(
.dcr_write_if (tex_dcr_write_if),
.tex_req_if (tex_req_if[i]),
.tex_rsp_if (tex_rsp_if[i]),
.cache_req_if (tcache_req_if[i]),
.cache_rsp_if (tcache_rsp_if[i])
.cache_bus_if (tcache_bus_if[i])
);
end
@ -398,29 +376,17 @@ module VX_cluster #(
`endif
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_ARB_TAG_WIDTH)
) per_socket_dcache_req_if[`NUM_SOCKETS]();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_ARB_TAG_WIDTH)
) per_socket_dcache_rsp_if[`NUM_SOCKETS]();
) per_socket_dcache_bus_if[`NUM_SOCKETS]();
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH)
) per_socket_icache_req_if[`NUM_SOCKETS]();
VX_cache_rsp_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH)
) per_socket_icache_rsp_if[`NUM_SOCKETS]();
) per_socket_icache_bus_if[`NUM_SOCKETS]();
`RESET_RELAY (mem_unit_reset, reset);
@ -434,38 +400,32 @@ module VX_cluster #(
.perf_memsys_if (perf_memsys_if),
`endif
.dcache_req_if (per_socket_dcache_req_if),
.dcache_rsp_if (per_socket_dcache_rsp_if),
.dcache_bus_if (per_socket_dcache_bus_if),
.icache_req_if (per_socket_icache_req_if),
.icache_rsp_if (per_socket_icache_rsp_if),
.icache_bus_if (per_socket_icache_bus_if),
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
.perf_tcache_if (perf_tcache_if),
`endif
.tcache_req_if (tcache_req_if),
.tcache_rsp_if (tcache_rsp_if),
.tcache_bus_if (tcache_bus_if),
`endif
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
.perf_rcache_if (perf_rcache_if),
`endif
.rcache_req_if (rcache_req_if),
.rcache_rsp_if (rcache_rsp_if),
.rcache_bus_if (rcache_bus_if),
`endif
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
.perf_ocache_if (perf_ocache_if),
`endif
.ocache_req_if (ocache_req_if),
.ocache_rsp_if (ocache_rsp_if),
.ocache_bus_if (ocache_bus_if),
`endif
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
.mem_bus_if (mem_bus_if)
);
///////////////////////////////////////////////////////////////////////////
@ -505,11 +465,9 @@ module VX_cluster #(
.dcr_write_if (socket_dcr_write_if),
.dcache_req_if (per_socket_dcache_req_if[i]),
.dcache_rsp_if (per_socket_dcache_rsp_if[i]),
.dcache_bus_if (per_socket_dcache_bus_if[i]),
.icache_req_if (per_socket_icache_req_if[i]),
.icache_rsp_if (per_socket_icache_rsp_if[i]),
.icache_bus_if (per_socket_icache_bus_if[i]),
`ifdef EXT_F_ENABLE
.fpu_req_if (per_socket_fpu_req_if[i]),

129
hw/rtl/VX_define.vh
View file

@ -317,82 +317,71 @@
///////////////////////////////////////////////////////////////////////////////
`define ASSIGN_VX_MEM_REQ_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.rw = src.rw; \
assign dst.byteen = src.byteen; \
assign dst.addr = src.addr; \
assign dst.data = src.data; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_MEM_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_rw = src.req_rw; \
assign dst.req_byteen = src.req_byteen; \
assign dst.req_addr = src.req_addr; \
assign dst.req_data = src.req_data; \
assign dst.req_tag = src.req_tag; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data = dst.rsp_data; \
assign src.rsp_tag = dst.rsp_tag; \
assign dst.rsp_ready = src.rsp_ready
`define ASSIGN_VX_MEM_RSP_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.data = src.data; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_MEM_REQ_IF_X(dst, src, TD, TS) \
assign dst.valid = src.valid; \
assign dst.rw = src.rw; \
assign dst.byteen = src.byteen; \
assign dst.addr = src.addr; \
assign dst.data = src.data; \
`define ASSIGN_VX_MEM_BUS_IF_X(dst, src, TD, TS) \
assign dst.req_valid = src.req_valid; \
assign dst.req_rw = src.req_rw; \
assign dst.req_byteen = src.req_byteen; \
assign dst.req_addr = src.req_addr; \
assign dst.req_data = src.req_data; \
if (TD != TS) \
assign dst.tag = {src.tag, {(TD-TS){1'b0}}}; \
assign dst.req_tag = {src.req_tag, {(TD-TS){1'b0}}}; \
else \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
assign dst.req_tag = src.req_tag; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data = dst.rsp_data; \
assign src.rsp_tag = dst.rsp_tag[TD-1 -: TS]; \
assign dst.rsp_ready = src.rsp_ready
`define ASSIGN_VX_CACHE_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_rw = src.req_rw; \
assign dst.req_byteen = src.req_byteen; \
assign dst.req_addr = src.req_addr; \
assign dst.req_data = src.req_data; \
assign dst.req_tag = src.req_tag; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data = dst.rsp_data; \
assign src.rsp_tag = dst.rsp_tag; \
assign dst.rsp_ready = src.rsp_ready
`define ASSIGN_VX_MEM_RSP_IF_X(dst, src, TD, TS) \
assign dst.valid = src.valid; \
assign dst.data = src.data; \
assign dst.tag = src.tag[TS-1 -: TD]; \
assign src.ready = dst.ready
`define ASSIGN_VX_CACHE_BUS_IF_XTAG(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_rw = src.req_rw; \
assign dst.req_byteen = src.req_byteen; \
assign dst.req_addr = src.req_addr; \
assign dst.req_data = src.req_data; \
assign src.req_ready = dst.req_ready; \
assign src.rsp_valid = dst.rsp_valid; \
assign src.rsp_data = dst.rsp_data; \
assign dst.rsp_ready = src.rsp_ready
`define ASSIGN_VX_CACHE_REQ_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.rw = src.rw; \
assign dst.byteen = src.byteen; \
assign dst.addr = src.addr; \
assign dst.data = src.data; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_CACHE_RSP_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.data = src.data; \
assign dst.tag = src.tag; \
assign src.ready = dst.ready
`define ASSIGN_VX_CACHE_REQ_IF_XTAG(dst, src) \
assign dst.valid = src.valid; \
assign dst.rw = src.rw; \
assign dst.byteen = src.byteen; \
assign dst.addr = src.addr; \
assign dst.data = src.data; \
assign src.ready = dst.ready
`define ASSIGN_VX_CACHE_RSP_IF_XTAG(dst, src) \
assign dst.valid = src.valid; \
assign dst.data = src.data; \
assign src.ready = dst.ready
`define CACHE_REQ_TO_MEM(dst, src, i) \
assign dst[i].valid = src.valid[i]; \
assign dst[i].rw = src.rw[i]; \
assign dst[i].byteen = src.byteen[i]; \
assign dst[i].addr = src.addr[i]; \
assign dst[i].data = src.data[i]; \
assign dst[i].tag = src.tag[i]; \
assign src.ready[i] = dst[i].ready
`define CACHE_RSP_FROM_MEM(dst, src, i) \
assign dst.valid[i] = src[i].valid; \
assign dst.data[i] = src[i].data; \
assign dst.tag[i] = src[i].tag; \
assign src[i].ready = dst.ready[i]
`define CACHE_BUS_TO_MEM(dst, src, i) \
assign dst[i].req_valid = src.req_valid[i]; \
assign dst[i].req_rw = src.req_rw[i]; \
assign dst[i].req_byteen = src.req_byteen[i]; \
assign dst[i].req_addr = src.req_addr[i]; \
assign dst[i].req_data = src.req_data[i]; \
assign dst[i].req_tag = src.req_tag[i]; \
assign src.req_ready[i] = dst[i].req_ready; \
assign src.rsp_valid[i] = dst[i].rsp_valid; \
assign src.rsp_data[i] = dst[i].rsp_data; \
assign src.rsp_tag[i] = dst[i].rsp_tag; \
assign dst[i].rsp_ready = src.rsp_ready[i]
`define ASSIGN_VX_RASTER_REQ_IF(dst, src) \
assign dst.valid = src.valid; \

6
hw/rtl/VX_gbar_unit.sv
View file

@ -31,11 +31,11 @@ module VX_gbar_unit #(
end
if (gbar_bus_if.req_valid) begin
if (active_barrier_count[NC_WIDTH-1:0] == gbar_bus_if.req_size_m1) begin
barrier_masks[gbar_bus_if.req_id] <= '0;
rsp_valid <= 1;
barrier_masks[gbar_bus_if.req_id] <= '0;
rsp_bar_id <= gbar_bus_if.req_id;
rsp_valid <= 1;
end else begin
barrier_masks[gbar_bus_if.req_id][gbar_bus_if.req_core_id] <= 1;
barrier_masks[gbar_bus_if.req_id][gbar_bus_if.req_core_id] <= 1;
end
end
end

43
hw/rtl/VX_mem_arb.sv
View file

@ -14,17 +14,8 @@ module VX_mem_arb #(
input wire clk,
input wire reset,
// input requests
VX_mem_req_if.slave req_in_if [NUM_REQS],
// input responses
VX_mem_rsp_if.master rsp_in_if [NUM_REQS],
// output request
VX_mem_req_if.master req_out_if,
// output response
VX_mem_rsp_if.slave rsp_out_if
VX_mem_bus_if.slave bus_in_if [NUM_REQS],
VX_mem_bus_if.master bus_out_if
);
localparam LOG_NUM_REQS = `CLOG2(NUM_REQS);
@ -44,14 +35,14 @@ module VX_mem_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_insert (
.data_in (req_in_if[i].tag),
.data_in (bus_in_if[i].req_tag),
.sel_in (`UP(LOG_NUM_REQS)'(i)),
.data_out (req_tag_in)
);
assign req_valid_in[i] = req_in_if[i].valid;
assign req_data_in[i] = {req_tag_in, req_in_if[i].addr, req_in_if[i].rw, req_in_if[i].byteen, req_in_if[i].data};
assign req_in_if[i].ready = req_ready_in[i];
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign req_data_in[i] = {req_tag_in, bus_in_if[i].req_addr, bus_in_if[i].req_rw, bus_in_if[i].req_byteen, bus_in_if[i].req_data};
assign bus_in_if[i].req_ready = req_ready_in[i];
end
VX_stream_arb #(
@ -66,9 +57,9 @@ module VX_mem_arb #(
.valid_in (req_valid_in),
.ready_in (req_ready_in),
.data_in (req_data_in),
.data_out ({req_out_if.tag, req_out_if.addr, req_out_if.rw, req_out_if.byteen, req_out_if.data}),
.valid_out (req_out_if.valid),
.ready_out (req_out_if.ready)
.data_out ({bus_out_if.req_tag, bus_out_if.req_addr, bus_out_if.req_rw, bus_out_if.req_byteen, bus_out_if.req_data}),
.valid_out (bus_out_if.req_valid),
.ready_out (bus_out_if.req_ready)
);
///////////////////////////////////////////////////////////////////////////
@ -79,7 +70,7 @@ module VX_mem_arb #(
wire [`UP(LOG_NUM_REQS)-1:0] rsp_sel;
if (NUM_REQS > 1) begin
assign rsp_sel = rsp_out_if.tag[TAG_SEL_IDX +: LOG_NUM_REQS];
assign rsp_sel = bus_out_if.rsp_tag[TAG_SEL_IDX +: LOG_NUM_REQS];
end else begin
assign rsp_sel = '0;
end
@ -91,7 +82,7 @@ module VX_mem_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_remove (
.data_in (rsp_out_if.tag),
.data_in (bus_out_if.rsp_tag),
.data_out (rsp_tag_out)
);
@ -104,18 +95,18 @@ module VX_mem_arb #(
.clk (clk),
.reset (reset),
.sel_in (rsp_sel),
.valid_in (rsp_out_if.valid),
.ready_in (rsp_out_if.ready),
.data_in ({rsp_tag_out, rsp_out_if.data}),
.valid_in (bus_out_if.rsp_valid),
.ready_in (bus_out_if.rsp_ready),
.data_in ({rsp_tag_out, bus_out_if.rsp_data}),
.data_out (rsp_data_in),
.valid_out (rsp_valid_in),
.ready_out (rsp_ready_in)
);
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign rsp_in_if[i].valid = rsp_valid_in[i];
assign {rsp_in_if[i].tag, rsp_in_if[i].data} = rsp_data_in[i];
assign rsp_ready_in[i] = rsp_in_if[i].ready;
assign bus_in_if[i].rsp_valid = rsp_valid_in[i];
assign {bus_in_if[i].rsp_tag, bus_in_if[i].rsp_data} = rsp_data_in[i];
assign rsp_ready_in[i] = bus_in_if[i].rsp_ready;
end
endmodule

184
hw/rtl/VX_mem_unit.sv
View file

@ -15,38 +15,32 @@ module VX_mem_unit # (
VX_perf_memsys_if.master perf_memsys_if,
`endif
VX_cache_req_if.slave icache_req_if [`NUM_SOCKETS],
VX_cache_rsp_if.master icache_rsp_if [`NUM_SOCKETS],
VX_cache_bus_if.slave icache_bus_if [`NUM_SOCKETS],
VX_cache_req_if.slave dcache_req_if [`NUM_SOCKETS],
VX_cache_rsp_if.master dcache_rsp_if [`NUM_SOCKETS],
VX_cache_bus_if.slave dcache_bus_if [`NUM_SOCKETS],
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_tcache_if,
`endif
VX_cache_req_if.slave tcache_req_if [`NUM_TEX_UNITS],
VX_cache_rsp_if.master tcache_rsp_if [`NUM_TEX_UNITS],
VX_cache_bus_if.slave tcache_bus_if [`NUM_TEX_UNITS],
`endif
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_rcache_if,
`endif
VX_cache_req_if.slave rcache_req_if [`NUM_RASTER_UNITS],
VX_cache_rsp_if.master rcache_rsp_if [`NUM_RASTER_UNITS],
VX_cache_bus_if.slave rcache_bus_if [`NUM_RASTER_UNITS],
`endif
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_ocache_if,
`endif
VX_cache_req_if.slave ocache_req_if [`NUM_ROP_UNITS],
VX_cache_rsp_if.master ocache_rsp_if [`NUM_ROP_UNITS],
VX_cache_bus_if.slave ocache_bus_if [`NUM_ROP_UNITS],
`endif
VX_mem_req_if.master mem_req_if,
VX_mem_rsp_if.slave mem_rsp_if
VX_mem_bus_if.master mem_bus_if
);
`ifdef PERF_ENABLE
@ -58,15 +52,10 @@ module VX_mem_unit # (
/////////////////////////////// I-Cache ///////////////////////////////////
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (ICACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (ICACHE_MEM_TAG_WIDTH)
) icache_mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (ICACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (ICACHE_MEM_TAG_WIDTH)
) icache_mem_rsp_if();
) icache_mem_bus_if();
`RESET_RELAY (icache_reset, reset);
@ -97,35 +86,22 @@ module VX_mem_unit # (
`endif
.clk (clk),
.reset (icache_reset),
.core_req_if (icache_req_if),
.core_rsp_if (icache_rsp_if),
.mem_req_if (icache_mem_req_if),
.mem_rsp_if (icache_mem_rsp_if)
.core_bus_if (icache_bus_if),
.mem_bus_if (icache_mem_bus_if)
);
/////////////////////////////// D-Cache ///////////////////////////////////
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (DCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (DCACHE_MEM_TAG_WIDTH)
) dcache_mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (DCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (DCACHE_MEM_TAG_WIDTH)
) dcache_mem_rsp_if();
) dcache_mem_bus_if();
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
) dcache_switch_req_if [`NUM_SOCKETS]();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
) dcache_switch_rsp_if [`NUM_SOCKETS]();
) dcache_switch_bus_if [`NUM_SOCKETS]();
`RESET_RELAY (dcache_reset, reset);
@ -159,10 +135,8 @@ module VX_mem_unit # (
.clk (clk),
.reset (dcache_reset),
.core_req_if (dcache_switch_req_if),
.core_rsp_if (dcache_switch_rsp_if),
.mem_req_if (dcache_mem_req_if),
.mem_rsp_if (dcache_mem_rsp_if)
.core_bus_if (dcache_switch_bus_if),
.mem_bus_if (dcache_mem_bus_if)
);
////////////////////////////// Shared Memory //////////////////////////////
@ -170,17 +144,11 @@ module VX_mem_unit # (
`ifdef SM_ENABLE
for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
) smem_switch_out_req_if[2]();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
) smem_switch_out_rsp_if[2]();
) smem_switch_out_bus_if[2]();
`RESET_RELAY (dcache_smem_switch_reset, reset);
@ -196,14 +164,11 @@ module VX_mem_unit # (
) smem_switch (
.clk (clk),
.reset (dcache_smem_switch_reset),
.req_in_if (dcache_req_if[i]),
.rsp_in_if (dcache_rsp_if[i]),
.req_out_if (smem_switch_out_req_if),
.rsp_out_if (smem_switch_out_rsp_if)
.bus_in_if (dcache_bus_if[i]),
.bus_out_if (smem_switch_out_bus_if)
);
`ASSIGN_VX_CACHE_REQ_IF (dcache_switch_req_if[i], smem_switch_out_req_if[0]);
`ASSIGN_VX_CACHE_RSP_IF (smem_switch_out_rsp_if[0], dcache_switch_rsp_if[i]);
`ASSIGN_VX_CACHE_BUS_IF (dcache_switch_bus_if[i], smem_switch_out_bus_if[0]);
// shared memory address mapping:
// [core_idx][warp_idx][word_idx][thread_idx] <= [core_idx][warp_idx][thread_idx][bank_offset..word_idx]
@ -217,14 +182,14 @@ module VX_mem_unit # (
for (genvar j = 0; j < DCACHE_NUM_REQS; ++j) begin
if (`NT_BITS != 0) begin
assign smem_req_addr[j][0 +: `NT_BITS] = smem_switch_out_req_if[1].addr[j][BANK_ADDR_OFFSET +: `NT_BITS];
assign smem_req_addr[j][0 +: `NT_BITS] = smem_switch_out_bus_if[1].req_addr[j][BANK_ADDR_OFFSET +: `NT_BITS];
end
assign smem_req_addr[j][`NT_BITS +: WORD_SEL_BITS] = smem_switch_out_req_if[1].addr[j][0 +: WORD_SEL_BITS];
assign smem_req_addr[j][`NT_BITS +: WORD_SEL_BITS] = smem_switch_out_bus_if[1].req_addr[j][0 +: WORD_SEL_BITS];
if (`NW_BITS != 0) begin
assign smem_req_addr[j][(`NT_BITS + WORD_SEL_BITS) +: `NW_BITS] = smem_switch_out_req_if[1].addr[j][(BANK_ADDR_OFFSET + `NT_BITS) +: `NW_BITS];
assign smem_req_addr[j][(`NT_BITS + WORD_SEL_BITS) +: `NW_BITS] = smem_switch_out_bus_if[1].req_addr[j][(BANK_ADDR_OFFSET + `NT_BITS) +: `NW_BITS];
end
if (SOCKET_BITS != 0) begin
assign smem_req_addr[j][(`NT_BITS + WORD_SEL_BITS + `NW_BITS) +: SOCKET_BITS] = smem_switch_out_req_if[1].addr[j][(BANK_ADDR_OFFSET + `NT_BITS + `NW_BITS) +: SOCKET_BITS];
assign smem_req_addr[j][(`NT_BITS + WORD_SEL_BITS + `NW_BITS) +: SOCKET_BITS] = smem_switch_out_bus_if[1].req_addr[j][(BANK_ADDR_OFFSET + `NT_BITS + `NW_BITS) +: SOCKET_BITS];
end
end
@ -249,27 +214,26 @@ module VX_mem_unit # (
`endif
// Core request
.req_valid (smem_switch_out_req_if[1].valid),
.req_rw (smem_switch_out_req_if[1].rw),
.req_byteen (smem_switch_out_req_if[1].byteen),
.req_valid (smem_switch_out_bus_if[1].req_valid),
.req_rw (smem_switch_out_bus_if[1].req_rw),
.req_byteen (smem_switch_out_bus_if[1].req_byteen),
.req_addr (smem_req_addr),
.req_data (smem_switch_out_req_if[1].data),
.req_tag (smem_switch_out_req_if[1].tag),
.req_ready (smem_switch_out_req_if[1].ready),
.req_data (smem_switch_out_bus_if[1].req_data),
.req_tag (smem_switch_out_bus_if[1].req_tag),
.req_ready (smem_switch_out_bus_if[1].req_ready),
// Core response
.rsp_valid (smem_switch_out_rsp_if[1].valid),
.rsp_data (smem_switch_out_rsp_if[1].data),
.rsp_tag (smem_switch_out_rsp_if[1].tag),
.rsp_ready (smem_switch_out_rsp_if[1].ready)
.rsp_valid (smem_switch_out_bus_if[1].rsp_valid),
.rsp_data (smem_switch_out_bus_if[1].rsp_data),
.rsp_tag (smem_switch_out_bus_if[1].rsp_tag),
.rsp_ready (smem_switch_out_bus_if[1].rsp_ready)
);
end
`else
for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
`ASSIGN_VX_CACHE_REQ_IF (dcache_switch_req_if[i], dcache_req_if[i]);
`ASSIGN_VX_CACHE_RSP_IF (dcache_rsp_if[i], dcache_switch_rsp_if[i]);
`ASSIGN_VX_CACHE_BUS_IF (dcache_switch_bus_if[i], dcache_bus_if[i]);
end
`endif
@ -278,15 +242,10 @@ module VX_mem_unit # (
`ifdef EXT_TEX_ENABLE
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (TCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (TCACHE_MEM_TAG_WIDTH)
) tcache_mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (TCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (TCACHE_MEM_TAG_WIDTH)
) tcache_mem_rsp_if();
) tcache_mem_bus_if();
`RESET_RELAY (tcache_reset, reset);
@ -319,10 +278,8 @@ module VX_mem_unit # (
`endif
.clk (clk),
.reset (tcache_reset),
.core_req_if (tcache_req_if),
.core_rsp_if (tcache_rsp_if),
.mem_req_if (tcache_mem_req_if),
.mem_rsp_if (tcache_mem_rsp_if)
.core_bus_if (tcache_bus_if),
.mem_bus_if (tcache_mem_bus_if)
);
`endif
@ -331,15 +288,10 @@ module VX_mem_unit # (
`ifdef EXT_ROP_ENABLE
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (OCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (OCACHE_MEM_TAG_WIDTH)
) ocache_mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (OCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (OCACHE_MEM_TAG_WIDTH)
) ocache_mem_rsp_if();
) ocache_mem_bus_if();
`RESET_RELAY (ocache_reset, reset);
@ -373,10 +325,8 @@ module VX_mem_unit # (
.clk (clk),
.reset (ocache_reset),
.core_req_if (ocache_req_if),
.core_rsp_if (ocache_rsp_if),
.mem_req_if (ocache_mem_req_if),
.mem_rsp_if (ocache_mem_rsp_if)
.core_bus_if (ocache_bus_if),
.mem_bus_if (ocache_mem_bus_if)
);
`endif
@ -385,15 +335,10 @@ module VX_mem_unit # (
`ifdef EXT_RASTER_ENABLE
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (RCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (RCACHE_MEM_TAG_WIDTH)
) rcache_mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (RCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (RCACHE_MEM_TAG_WIDTH)
) rcache_mem_rsp_if();
) rcache_mem_bus_if();
`RESET_RELAY (rcache_reset, reset);
@ -426,25 +371,18 @@ module VX_mem_unit # (
`endif
.clk (clk),
.reset (rcache_reset),
.core_req_if (rcache_req_if),
.core_rsp_if (rcache_rsp_if),
.mem_req_if (rcache_mem_req_if),
.mem_rsp_if (rcache_mem_rsp_if)
.core_bus_if (rcache_bus_if),
.mem_bus_if (rcache_mem_bus_if)
);
`endif
/////////////////////////////// L2-Cache //////////////////////////////////
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (L2_WORD_SIZE * 8),
.TAG_WIDTH (L2_TAG_WIDTH)
) l2_mem_req_if[L2_NUM_REQS]();
VX_mem_rsp_if #(
.DATA_WIDTH (L2_WORD_SIZE * 8),
.TAG_WIDTH (L2_TAG_WIDTH)
) l2_mem_rsp_if[L2_NUM_REQS]();
) l2_mem_bus_if[L2_NUM_REQS]();
localparam I_MEM_ARB_IDX = 0;
localparam D_MEM_ARB_IDX = I_MEM_ARB_IDX + 1;
@ -455,25 +393,19 @@ module VX_mem_unit # (
`UNUSED_PARAM (R_MEM_ARB_IDX)
`UNUSED_PARAM (O_MEM_ARB_IDX)
`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[I_MEM_ARB_IDX], icache_mem_req_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_RSP_IF_X (icache_mem_rsp_if, l2_mem_rsp_if[I_MEM_ARB_IDX], ICACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[D_MEM_ARB_IDX], dcache_mem_req_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_RSP_IF_X (dcache_mem_rsp_if, l2_mem_rsp_if[D_MEM_ARB_IDX], DCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[I_MEM_ARB_IDX], icache_mem_bus_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[D_MEM_ARB_IDX], dcache_mem_bus_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
`ifdef EXT_TEX_ENABLE
`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[T_MEM_ARB_IDX], tcache_mem_req_if, L1_MEM_TAG_WIDTH, TCACHE_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_RSP_IF_X (tcache_mem_rsp_if, l2_mem_rsp_if[T_MEM_ARB_IDX], TCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[T_MEM_ARB_IDX], tcache_mem_bus_if, L1_MEM_TAG_WIDTH, TCACHE_MEM_TAG_WIDTH);
`endif
`ifdef EXT_RASTER_ENABLE
`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[R_MEM_ARB_IDX], rcache_mem_req_if, L1_MEM_TAG_WIDTH, RCACHE_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_RSP_IF_X (rcache_mem_rsp_if, l2_mem_rsp_if[R_MEM_ARB_IDX], RCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[R_MEM_ARB_IDX], rcache_mem_bus_if, L1_MEM_TAG_WIDTH, RCACHE_MEM_TAG_WIDTH);
`endif
`ifdef EXT_ROP_ENABLE
`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[O_MEM_ARB_IDX], ocache_mem_req_if, L1_MEM_TAG_WIDTH, OCACHE_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_RSP_IF_X (ocache_mem_rsp_if, l2_mem_rsp_if[O_MEM_ARB_IDX], OCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
`ASSIGN_VX_MEM_BUS_IF_X (l2_mem_bus_if[O_MEM_ARB_IDX], ocache_mem_bus_if, L1_MEM_TAG_WIDTH, OCACHE_MEM_TAG_WIDTH);
`endif
`RESET_RELAY (l2_reset, reset);
@ -505,10 +437,8 @@ module VX_mem_unit # (
`ifdef PERF_ENABLE
.perf_cache_if (perf_l2cache_if),
`endif
.core_req_if (l2_mem_req_if),
.core_rsp_if (l2_mem_rsp_if),
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
.core_bus_if (l2_mem_bus_if),
.mem_bus_if (mem_bus_if)
);
`ifdef PERF_ENABLE

72
hw/rtl/VX_socket.sv
View file

@ -20,11 +20,9 @@ module VX_socket #(
VX_dcr_write_if.slave dcr_write_if,
VX_cache_req_if.master dcache_req_if,
VX_cache_rsp_if.slave dcache_rsp_if,
VX_cache_bus_if.master dcache_bus_if,
VX_cache_req_if.master icache_req_if,
VX_cache_rsp_if.slave icache_rsp_if,
VX_cache_bus_if.master icache_bus_if,
`ifdef EXT_F_ENABLE
VX_fpu_req_if.master fpu_req_if,
@ -171,7 +169,6 @@ module VX_socket #(
);
`ASSIGN_VX_TEX_REQ_IF (tex_req_if, tex_req_tmp_if[0]);
`ASSIGN_VX_TEX_RSP_IF (tex_rsp_tmp_if[0], tex_rsp_if);
`endif
@ -216,35 +213,22 @@ module VX_socket #(
);
`ASSIGN_VX_FPU_REQ_IF (fpu_req_if, fpu_req_tmp_if[0]);
`ASSIGN_VX_FPU_RSP_IF (fpu_rsp_tmp_if[0], fpu_rsp_if);
`endif
///////////////////////////////////////////////////////////////////////////
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) per_core_dcache_req_if[`SOCKET_SIZE]();
) per_core_dcache_bus_if[`SOCKET_SIZE]();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) per_core_dcache_rsp_if[`SOCKET_SIZE]();
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_ARB_TAG_WIDTH)
) dcache_req_tmp_if[1]();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_ARB_TAG_WIDTH)
) dcache_rsp_tmp_if[1]();
) dcache_bus_tmp_if[1]();
`RESET_RELAY (dcache_arb_reset, reset);
@ -261,40 +245,25 @@ module VX_socket #(
) dcache_arb (
.clk (clk),
.reset (dcache_arb_reset),
.req_in_if (per_core_dcache_req_if),
.rsp_in_if (per_core_dcache_rsp_if),
.req_out_if (dcache_req_tmp_if),
.rsp_out_if (dcache_rsp_tmp_if)
.bus_in_if (per_core_dcache_bus_if),
.bus_out_if (dcache_bus_tmp_if)
);
`ASSIGN_VX_CACHE_REQ_IF (dcache_req_if, dcache_req_tmp_if[0]);
`ASSIGN_VX_CACHE_RSP_IF (dcache_rsp_tmp_if[0], dcache_rsp_if);
`ASSIGN_VX_CACHE_BUS_IF (dcache_bus_if, dcache_bus_tmp_if[0]);
///////////////////////////////////////////////////////////////////////////
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_TAG_WIDTH)
) per_core_icache_req_if[`SOCKET_SIZE]();
) per_core_icache_bus_if[`SOCKET_SIZE]();
VX_cache_rsp_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_TAG_WIDTH)
) per_core_icache_rsp_if[`SOCKET_SIZE]();
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH)
) icache_req_tmp_if[1]();
VX_cache_rsp_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH)
) icache_rsp_tmp_if[1]();
) icache_bus_tmp_if[1]();
`RESET_RELAY (icache_arb_reset, reset);
@ -311,14 +280,11 @@ module VX_socket #(
) icache_arb (
.clk (clk),
.reset (icache_arb_reset),
.req_in_if (per_core_icache_req_if),
.rsp_in_if (per_core_icache_rsp_if),
.req_out_if (icache_req_tmp_if),
.rsp_out_if (icache_rsp_tmp_if)
.bus_in_if (per_core_icache_bus_if),
.bus_out_if (icache_bus_tmp_if)
);
`ASSIGN_VX_CACHE_REQ_IF (icache_req_if, icache_req_tmp_if[0]);
`ASSIGN_VX_CACHE_RSP_IF (icache_rsp_tmp_if[0], icache_rsp_if);
`ASSIGN_VX_CACHE_BUS_IF (icache_bus_if, icache_bus_tmp_if[0]);
///////////////////////////////////////////////////////////////////////////
@ -354,11 +320,9 @@ module VX_socket #(
.dcr_write_if (core_dcr_write_if),
.dcache_req_if (per_core_dcache_req_if[i]),
.dcache_rsp_if (per_core_dcache_rsp_if[i]),
.dcache_bus_if (per_core_dcache_bus_if[i]),
.icache_req_if (per_core_icache_req_if[i]),
.icache_rsp_if (per_core_icache_rsp_if[i]),
.icache_bus_if (per_core_icache_bus_if[i]),
`ifdef EXT_F_ENABLE
.fpu_req_if (per_core_fpu_req_if[i]),

55
hw/rtl/Vortex.sv
View file

@ -54,28 +54,23 @@ module Vortex (
VX_perf_cache_if perf_l3cache_if();
`endif
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (L3_MEM_DATA_WIDTH),
.TAG_WIDTH (L3_MEM_TAG_WIDTH)
) mem_req_if();
) mem_bus_if();
VX_mem_rsp_if #(
.DATA_WIDTH (L3_MEM_DATA_WIDTH),
.TAG_WIDTH (L3_MEM_TAG_WIDTH)
) mem_rsp_if();
assign mem_req_valid = mem_bus_if.req_valid;
assign mem_req_rw = mem_bus_if.req_rw;
assign mem_req_byteen= mem_bus_if.req_byteen;
assign mem_req_addr = mem_bus_if.req_addr;
assign mem_req_data = mem_bus_if.req_data;
assign mem_req_tag = mem_bus_if.req_tag;
assign mem_bus_if.req_ready = mem_req_ready;
assign mem_req_valid = mem_req_if.valid;
assign mem_req_rw = mem_req_if.rw;
assign mem_req_byteen= mem_req_if.byteen;
assign mem_req_addr = mem_req_if.addr;
assign mem_req_data = mem_req_if.data;
assign mem_req_tag = mem_req_if.tag;
assign mem_req_if.ready = mem_req_ready;
assign mem_rsp_if.valid = mem_rsp_valid;
assign mem_rsp_if.data = mem_rsp_data;
assign mem_rsp_if.tag = mem_rsp_tag;
assign mem_rsp_ready = mem_rsp_if.ready;
assign mem_bus_if.rsp_valid = mem_rsp_valid;
assign mem_bus_if.rsp_data = mem_rsp_data;
assign mem_bus_if.rsp_tag = mem_rsp_tag;
assign mem_rsp_ready = mem_bus_if.rsp_ready;
wire mem_req_fire = mem_req_valid && mem_req_ready;
wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
@ -124,15 +119,10 @@ module Vortex (
`UNUSED_VAR (per_cluster_sim_ebreak)
`UNUSED_VAR (per_cluster_sim_wb_value)
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (L2_MEM_DATA_WIDTH),
.TAG_WIDTH (L2_MEM_TAG_WIDTH)
) per_cluster_mem_req_if[`NUM_CLUSTERS]();
VX_mem_rsp_if #(
.DATA_WIDTH (L2_MEM_DATA_WIDTH),
.TAG_WIDTH (L2_MEM_TAG_WIDTH)
) per_cluster_mem_rsp_if[`NUM_CLUSTERS]();
) per_cluster_mem_bus_if[`NUM_CLUSTERS]();
VX_dcr_write_if dcr_write_if();
assign dcr_write_if.valid = dcr_wr_valid;
@ -192,8 +182,7 @@ module Vortex (
`endif
`endif
.mem_req_if (per_cluster_mem_req_if[i]),
.mem_rsp_if (per_cluster_mem_rsp_if[i]),
.mem_bus_if (per_cluster_mem_bus_if[i]),
.sim_ebreak (per_cluster_sim_ebreak[i]),
.sim_wb_value (per_cluster_sim_wb_value[i]),
@ -235,10 +224,8 @@ module Vortex (
.perf_cache_if (perf_l3cache_if),
`endif
.core_req_if (per_cluster_mem_req_if),
.core_rsp_if (per_cluster_mem_rsp_if),
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
.core_bus_if (per_cluster_mem_bus_if),
.mem_bus_if (mem_bus_if)
);
`ifdef PERF_ENABLE
@ -284,7 +271,7 @@ module Vortex (
perf_mem_pending_reads <= '0;
end else begin
perf_mem_pending_reads <= $signed(perf_mem_pending_reads) +
`PERF_CTR_BITS'($signed(2'(mem_req_fire && ~mem_req_if.rw) - 2'(mem_rsp_fire)));
`PERF_CTR_BITS'($signed(2'(mem_req_fire && ~mem_bus_if.req_rw) - 2'(mem_rsp_fire)));
end
end
@ -298,10 +285,10 @@ module Vortex (
perf_mem_writes <= '0;
perf_mem_lat <= '0;
end else begin
if (mem_req_fire && ~mem_req_if.rw) begin
if (mem_req_fire && ~mem_bus_if.req_rw) begin
perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'(1);
end
if (mem_req_fire && mem_req_if.rw) begin
if (mem_req_fire && mem_bus_if.req_rw) begin
perf_mem_writes <= perf_mem_writes + `PERF_CTR_BITS'(1);
end
perf_mem_lat <= perf_mem_lat + perf_mem_pending_reads;

98
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -458,16 +458,11 @@ module vortex_afu #(
//--
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH ($bits(t_local_mem_data)),
.ADDR_WIDTH ($bits(t_local_mem_addr)),
.TAG_WIDTH (AVS_REQ_TAGW)
) cci_vx_mem_req_if[1:0]();
VX_mem_rsp_if #(
.DATA_WIDTH ($bits(t_local_mem_data)),
.TAG_WIDTH (AVS_REQ_TAGW)
) cci_vx_mem_rsp_if[1:0]();
) cci_vx_mem_bus_if[1:0]();
VX_mem_adapter #(
.SRC_DATA_WIDTH (CCI_DATA_WIDTH),
@ -495,18 +490,18 @@ module vortex_afu #(
.mem_rsp_tag_in (cci_mem_rsp_tag),
.mem_rsp_ready_in (cci_mem_rsp_ready),
.mem_req_valid_out (cci_vx_mem_req_if[1].valid),
.mem_req_addr_out (cci_vx_mem_req_if[1].addr),
.mem_req_rw_out (cci_vx_mem_req_if[1].rw),
.mem_req_byteen_out (cci_vx_mem_req_if[1].byteen),
.mem_req_data_out (cci_vx_mem_req_if[1].data),
.mem_req_tag_out (cci_vx_mem_req_if[1].tag),
.mem_req_ready_out (cci_vx_mem_req_if[1].ready),
.mem_req_valid_out (cci_vx_mem_bus_if[1].req_valid),
.mem_req_addr_out (cci_vx_mem_bus_if[1].req_addr),
.mem_req_rw_out (cci_vx_mem_bus_if[1].req_rw),
.mem_req_byteen_out (cci_vx_mem_bus_if[1].req_byteen),
.mem_req_data_out (cci_vx_mem_bus_if[1].req_data),
.mem_req_tag_out (cci_vx_mem_bus_if[1].req_tag),
.mem_req_ready_out (cci_vx_mem_bus_if[1].req_ready),
.mem_rsp_valid_out (cci_vx_mem_rsp_if[1].valid),
.mem_rsp_data_out (cci_vx_mem_rsp_if[1].data),
.mem_rsp_tag_out (cci_vx_mem_rsp_if[1].tag),
.mem_rsp_ready_out (cci_vx_mem_rsp_if[1].ready)
.mem_rsp_valid_out (cci_vx_mem_bus_if[1].rsp_valid),
.mem_rsp_data_out (cci_vx_mem_bus_if[1].rsp_data),
.mem_rsp_tag_out (cci_vx_mem_bus_if[1].rsp_tag),
.mem_rsp_ready_out (cci_vx_mem_bus_if[1].rsp_ready)
);
//--
@ -543,31 +538,26 @@ module vortex_afu #(
.mem_rsp_tag_in (vx_mem_rsp_tag),
.mem_rsp_ready_in (vx_mem_rsp_ready),
.mem_req_valid_out (cci_vx_mem_req_if[0].valid),
.mem_req_addr_out (cci_vx_mem_req_if[0].addr),
.mem_req_rw_out (cci_vx_mem_req_if[0].rw),
.mem_req_byteen_out (cci_vx_mem_req_if[0].byteen),
.mem_req_data_out (cci_vx_mem_req_if[0].data),
.mem_req_tag_out (cci_vx_mem_req_if[0].tag),
.mem_req_ready_out (cci_vx_mem_req_if[0].ready),
.mem_req_valid_out (cci_vx_mem_bus_if[0].req_valid),
.mem_req_addr_out (cci_vx_mem_bus_if[0].req_addr),
.mem_req_rw_out (cci_vx_mem_bus_if[0].req_rw),
.mem_req_byteen_out (cci_vx_mem_bus_if[0].req_byteen),
.mem_req_data_out (cci_vx_mem_bus_if[0].req_data),
.mem_req_tag_out (cci_vx_mem_bus_if[0].req_tag),
.mem_req_ready_out (cci_vx_mem_bus_if[0].req_ready),
.mem_rsp_valid_out (cci_vx_mem_rsp_if[0].valid),
.mem_rsp_data_out (cci_vx_mem_rsp_if[0].data),
.mem_rsp_tag_out (cci_vx_mem_rsp_if[0].tag),
.mem_rsp_ready_out (cci_vx_mem_rsp_if[0].ready)
.mem_rsp_valid_out (cci_vx_mem_bus_if[0].rsp_valid),
.mem_rsp_data_out (cci_vx_mem_bus_if[0].rsp_data),
.mem_rsp_tag_out (cci_vx_mem_bus_if[0].rsp_tag),
.mem_rsp_ready_out (cci_vx_mem_bus_if[0].rsp_ready)
);
//--
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH ($bits(t_local_mem_data)),
.ADDR_WIDTH ($bits(t_local_mem_addr)),
.TAG_WIDTH (AVS_REQ_TAGW+1)
) mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH ($bits(t_local_mem_data)),
.TAG_WIDTH (AVS_REQ_TAGW+1)
) mem_rsp_if();
) mem_bus_if();
`RESET_RELAY (mem_arb_reset, reset);
@ -582,10 +572,8 @@ module vortex_afu #(
) mem_arb (
.clk (clk),
.reset (mem_arb_reset),
.req_in_if (cci_vx_mem_req_if),
.rsp_in_if (cci_vx_mem_rsp_if),
.req_out_if (mem_req_if),
.rsp_out_if (mem_rsp_if)
.bus_in_if (cci_vx_mem_bus_if),
.bus_out_if (mem_bus_if)
);
//--
@ -606,19 +594,19 @@ module vortex_afu #(
.reset (avs_adapter_reset),
// Memory request
.mem_req_valid (mem_req_if.valid),
.mem_req_rw (mem_req_if.rw),
.mem_req_byteen (mem_req_if.byteen),
.mem_req_addr (mem_req_if.addr),
.mem_req_data (mem_req_if.data),
.mem_req_tag (mem_req_if.tag),
.mem_req_ready (mem_req_if.ready),
.mem_req_valid (mem_bus_if.req_valid),
.mem_req_rw (mem_bus_if.req_rw),
.mem_req_byteen (mem_bus_if.req_byteen),
.mem_req_addr (mem_bus_if.req_addr),
.mem_req_data (mem_bus_if.req_data),
.mem_req_tag (mem_bus_if.req_tag),
.mem_req_ready (mem_bus_if.req_ready),
// Memory response
.mem_rsp_valid (mem_rsp_if.valid),
.mem_rsp_data (mem_rsp_if.data),
.mem_rsp_tag (mem_rsp_if.tag),
.mem_rsp_ready (mem_rsp_if.ready),
.mem_rsp_valid (mem_bus_if.rsp_valid),
.mem_rsp_data (mem_bus_if.rsp_data),
.mem_rsp_tag (mem_bus_if.rsp_tag),
.mem_rsp_ready (mem_bus_if.rsp_ready),
// AVS bus
.avs_writedata (avs_writedata),
@ -1000,11 +988,11 @@ module vortex_afu #(
`ifdef DBG_SCOPE_AFU
`ifdef SCOPE
wire mem_req_fire = mem_req_if.valid && mem_req_if.ready;
wire mem_rsp_fire = mem_rsp_if.valid && mem_rsp_if.ready;
wire mem_req_fire = mem_bus_if.req_valid && mem_bus_if.req_ready;
wire mem_rsp_fire = mem_bus_if.rsp_valid && mem_bus_if.rsp_ready;
wire avs_write_fire = avs_write[0] && ~avs_waitrequest[0];
wire avs_read_fire = avs_read[0] && ~avs_waitrequest[0];
wire [$bits(t_local_mem_addr)-1:0] mem_req_if_addr = mem_req_if.addr;
wire [$bits(t_local_mem_addr)-1:0] mem_bus_if_addr = mem_bus_if.req_addr;
reg [STATE_WIDTH-1:0] state_prev;
always @(posedge clk) begin
@ -1064,7 +1052,7 @@ module vortex_afu #(
cci_rd_req_ctr,
cci_rd_rsp_ctr,
cci_wr_req_ctr,
mem_req_if_addr
mem_bus_if_addr
}),
.bus_in(scope_bus_in_w[0]),
.bus_out(scope_bus_out_w[0])

49
hw/rtl/cache/VX_cache.sv vendored
View file

@ -53,17 +53,8 @@ module VX_cache #(
input wire clk,
input wire reset,
// Core request
VX_mem_req_if.slave core_req_if [NUM_REQS],
// Core response
VX_mem_rsp_if.master core_rsp_if [NUM_REQS],
// Memory request
VX_mem_req_if.master mem_req_if,
// Memory response
VX_mem_rsp_if.slave mem_rsp_if
VX_mem_bus_if.slave core_bus_if [NUM_REQS],
VX_mem_bus_if.master mem_bus_if
);
`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter"))
@ -93,13 +84,13 @@ module VX_cache #(
wire [NUM_REQS-1:0] core_req_ready;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_valid[i] = core_req_if[i].valid;
assign core_req_rw[i] = core_req_if[i].rw;
assign core_req_addr[i] = core_req_if[i].addr;
assign core_req_byteen[i] = core_req_if[i].byteen;
assign core_req_data[i] = core_req_if[i].data;
assign core_req_tag[i] = core_req_if[i].tag;
assign core_req_if[i].ready = core_req_ready[i];
assign core_req_valid[i] = core_bus_if[i].req_valid;
assign core_req_rw[i] = core_bus_if[i].req_rw;
assign core_req_addr[i] = core_bus_if[i].req_addr;
assign core_req_byteen[i] = core_bus_if[i].req_byteen;
assign core_req_data[i] = core_bus_if[i].req_data;
assign core_req_tag[i] = core_bus_if[i].req_tag;
assign core_bus_if[i].req_ready = core_req_ready[i];
end
///////////////////////////////////////////////////////////////////////////
@ -123,9 +114,9 @@ module VX_cache #(
.valid_in (core_rsp_valid_s[i]),
.ready_in (core_rsp_ready_s[i]),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
.data_out ({core_rsp_if[i].data, core_rsp_if[i].tag}),
.valid_out (core_rsp_if[i].valid),
.ready_out (core_rsp_if[i].ready)
.data_out ({core_bus_if[i].rsp_data, core_bus_if[i].rsp_tag}),
.valid_out (core_bus_if[i].rsp_valid),
.ready_out (core_bus_if[i].rsp_ready)
);
end
@ -150,9 +141,9 @@ module VX_cache #(
.valid_in (mem_req_valid_s),
.ready_in (mem_req_ready_s),
.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
.data_out ({mem_req_if.rw, mem_req_if.byteen, mem_req_if.addr, mem_req_if.data, mem_req_if.tag}),
.valid_out (mem_req_if.valid),
.ready_out (mem_req_if.ready)
.data_out ({mem_bus_if.req_rw, mem_bus_if.req_byteen, mem_bus_if.req_addr, mem_bus_if.req_data, mem_bus_if.req_tag}),
.valid_out (mem_bus_if.req_valid),
.ready_out (mem_bus_if.req_ready)
);
///////////////////////////////////////////////////////////////////////////
@ -170,9 +161,9 @@ module VX_cache #(
) mem_rsp_queue (
.clk (clk),
.reset (reset),
.valid_in (mem_rsp_if.valid),
.ready_in (mem_rsp_if.ready),
.data_in ({mem_rsp_if.tag, mem_rsp_if.data}),
.valid_in (mem_bus_if.rsp_valid),
.ready_in (mem_bus_if.rsp_ready),
.data_in ({mem_bus_if.rsp_tag, mem_bus_if.rsp_data}),
.data_out ({mem_rsp_tag_s, mem_rsp_data_s}),
.valid_out (mem_rsp_valid_s),
.ready_out (mem_rsp_ready_s)
@ -565,12 +556,12 @@ module VX_cache #(
wire [NUM_REQS-1:0] perf_crsp_stall_per_req;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign perf_crsp_stall_per_req[i] = core_rsp_if[i].valid && ~core_rsp_if[i].ready;
assign perf_crsp_stall_per_req[i] = core_bus_if[i].rsp_valid && ~core_bus_if[i].rsp_ready;
end
`POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req);
wire perf_mem_stall_per_cycle = mem_req_if.valid && ~mem_req_if.ready;
wire perf_mem_stall_per_cycle = mem_bus_if.req_valid && ~mem_bus_if.req_ready;
reg [`PERF_CTR_BITS-1:0] perf_core_reads;
reg [`PERF_CTR_BITS-1:0] perf_core_writes;

51
hw/rtl/cache/VX_cache_arb.sv vendored
View file

@ -13,18 +13,9 @@ module VX_cache_arb #(
) (
input wire clk,
input wire reset,
// input requests
VX_cache_req_if.slave req_in_if [NUM_INPUTS],
// input responses
VX_cache_rsp_if.master rsp_in_if [NUM_INPUTS],
// output request
VX_cache_req_if.master req_out_if [NUM_OUTPUTS],
// output response
VX_cache_rsp_if.slave rsp_out_if [NUM_OUTPUTS]
VX_cache_bus_if.slave bus_in_if [NUM_INPUTS],
VX_cache_bus_if.master bus_out_if [NUM_OUTPUTS]
);
localparam ADDR_WIDTH = (`XLEN-`CLOG2(DATA_SIZE));
@ -48,8 +39,8 @@ module VX_cache_arb #(
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
assign req_valid_in[i][j] = req_in_if[i].valid[j];
assign req_in_if[i].ready[j] = req_ready_in[i][j];
assign req_valid_in[i][j] = bus_in_if[i].req_valid[j];
assign bus_in_if[i].req_ready[j] = req_ready_in[i][j];
if (NUM_INPUTS > NUM_OUTPUTS) begin
wire [TAG_OUT_WIDTH-1:0] req_tag_in;
@ -59,13 +50,13 @@ module VX_cache_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_insert (
.data_in (req_in_if[i].tag[j]),
.data_in (bus_in_if[i].req_tag[j]),
.sel_in (LOG_NUM_REQS'(r)),
.data_out (req_tag_in)
);
assign req_data_in[i][j] = {req_tag_in, req_in_if[i].addr[j], req_in_if[i].rw[j], req_in_if[i].byteen[j], req_in_if[i].data[j]};
assign req_data_in[i][j] = {req_tag_in, bus_in_if[i].req_addr[j], bus_in_if[i].req_rw[j], bus_in_if[i].req_byteen[j], bus_in_if[i].req_data[j]};
end else begin
assign req_data_in[i][j] = {req_in_if[i].tag[j], req_in_if[i].addr[j], req_in_if[i].rw[j], req_in_if[i].byteen[j], req_in_if[i].data[j]};
assign req_data_in[i][j] = {bus_in_if[i].req_tag[j], bus_in_if[i].req_addr[j], bus_in_if[i].req_rw[j], bus_in_if[i].req_byteen[j], bus_in_if[i].req_data[j]};
end
end
end
@ -91,9 +82,9 @@ module VX_cache_arb #(
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
assign req_out_if[i].valid[j] = req_valid_out[i][j];
assign {req_out_if[i].tag[j], req_out_if[i].addr[j], req_out_if[i].rw[j], req_out_if[i].byteen[j], req_out_if[i].data[j]} = req_data_out[i][j];
assign req_ready_out[i][j] = req_out_if[i].ready[j];
assign bus_out_if[i].req_valid[j] = req_valid_out[i][j];
assign {bus_out_if[i].req_tag[j], bus_out_if[i].req_addr[j], bus_out_if[i].req_rw[j], bus_out_if[i].req_byteen[j], bus_out_if[i].req_data[j]} = req_data_out[i][j];
assign req_ready_out[i][j] = bus_out_if[i].req_ready[j];
end
end
@ -121,16 +112,16 @@ module VX_cache_arb #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_remove (
.data_in (rsp_out_if[j].tag[i]),
.data_in (bus_out_if[j].rsp_tag[i]),
.data_out (rsp_tag_out)
);
assign rsp_valid_in[j] = rsp_out_if[j].valid[i];
assign rsp_data_in[j] = {rsp_tag_out, rsp_out_if[j].data[i]};
assign rsp_out_if[j].ready[i] = rsp_ready_in[j];
assign rsp_valid_in[j] = bus_out_if[j].rsp_valid[i];
assign rsp_data_in[j] = {rsp_tag_out, bus_out_if[j].rsp_data[i]};
assign bus_out_if[j].rsp_ready[i] = rsp_ready_in[j];
if (NUM_INPUTS > 1) begin
assign rsp_sel_in[j] = rsp_out_if[j].tag[i][TAG_SEL_IDX +: LOG_NUM_REQS];
assign rsp_sel_in[j] = bus_out_if[j].rsp_tag[i][TAG_SEL_IDX +: LOG_NUM_REQS];
end else begin
assign rsp_sel_in[j] = '0;
end
@ -157,9 +148,9 @@ module VX_cache_arb #(
end else begin
for (genvar j = 0; j < NUM_OUTPUTS; ++j) begin
assign rsp_valid_in[j] = rsp_out_if[j].valid[i];
assign rsp_data_in[j] = {rsp_out_if[j].tag[i], rsp_out_if[j].data[i]};
assign rsp_out_if[j].ready[i] = rsp_ready_in[j];
assign rsp_valid_in[j] = bus_out_if[j].rsp_valid[i];
assign rsp_data_in[j] = {bus_out_if[j].rsp_tag[i], bus_out_if[j].rsp_data[i]};
assign bus_out_if[j].rsp_ready[i] = rsp_ready_in[j];
end
VX_stream_arb #(
@ -183,9 +174,9 @@ module VX_cache_arb #(
end
for (genvar j = 0; j < NUM_INPUTS; ++j) begin
assign rsp_in_if[j].valid[i] = rsp_valid_out[j];
assign {rsp_in_if[j].tag[i], rsp_in_if[j].data[i]} = rsp_data_out[j];
assign rsp_ready_out[j] = rsp_in_if[j].ready[i];
assign bus_in_if[j].rsp_valid[i] = rsp_valid_out[j];
assign {bus_in_if[j].rsp_tag[i], bus_in_if[j].rsp_data[i]} = rsp_data_out[j];
assign rsp_ready_out[j] = bus_in_if[j].rsp_ready[i];
end
end

54
hw/rtl/cache/VX_cache_bus_if.sv vendored Normal file
View file

@ -0,0 +1,54 @@
`include "VX_cache_define.vh"
interface VX_cache_bus_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1,
parameter ADDR_WIDTH = `XLEN - `CLOG2(WORD_SIZE),
parameter DATA_WIDTH = WORD_SIZE * 8
) ();
wire [NUM_REQS-1:0] req_valid;
wire [NUM_REQS-1:0] req_rw;
wire [NUM_REQS-1:0][WORD_SIZE-1:0] req_byteen;
wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr;
wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] req_tag;
wire [NUM_REQS-1:0] req_ready;
wire [NUM_REQS-1:0] rsp_valid;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] rsp_data;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] rsp_tag;
wire [NUM_REQS-1:0] rsp_ready;
modport master (
output req_valid,
output req_rw,
output req_byteen,
output req_addr,
output req_data,
output req_tag,
input req_ready,
input rsp_valid,
input rsp_data,
input rsp_tag,
output rsp_ready
);
modport slave (
input req_valid,
input req_rw,
input req_byteen,
input req_addr,
input req_data,
input req_tag,
output req_ready,
output rsp_valid,
output rsp_data,
output rsp_tag,
input rsp_ready
);
endinterface

134
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -60,17 +60,8 @@ module VX_cache_cluster #(
VX_perf_cache_if.master perf_cache_if,
`endif
// Core request
VX_cache_req_if.slave core_req_if [NUM_INPUTS],
// Core response
VX_cache_rsp_if.master core_rsp_if [NUM_INPUTS],
// Memory request
VX_mem_req_if.master mem_req_if,
// Memory response
VX_mem_rsp_if.slave mem_rsp_if
VX_cache_bus_if.slave core_bus_if [NUM_INPUTS],
VX_mem_bus_if.master mem_bus_if
);
localparam NUM_CACHES = `UP(NUM_UNITS);
localparam PASSTHRU = (NUM_UNITS == 0);
@ -87,27 +78,16 @@ module VX_cache_cluster #(
`PERF_CACHE_ADD (perf_cache_if, perf_cache_unit_if, NUM_CACHES);
`endif
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (`LINE_WIDTH),
.TAG_WIDTH (MEM_TAG_WIDTH)
) cache_mem_req_if[NUM_CACHES]();
VX_mem_rsp_if #(
.DATA_WIDTH (`LINE_WIDTH),
.TAG_WIDTH (MEM_TAG_WIDTH)
) cache_mem_rsp_if[NUM_CACHES]();
) cache_mem_bus_if[NUM_CACHES]();
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (NUM_REQS),
.WORD_SIZE (WORD_SIZE),
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_req_if[NUM_CACHES]();
VX_cache_rsp_if #(
.NUM_REQS (NUM_REQS),
.WORD_SIZE (WORD_SIZE),
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_rsp_if[NUM_CACHES]();
) arb_core_bus_if[NUM_CACHES]();
`RESET_RELAY (cache_arb_reset, reset);
@ -124,30 +104,19 @@ module VX_cache_cluster #(
) cache_arb (
.clk (clk),
.reset (cache_arb_reset),
.req_in_if (core_req_if),
.rsp_in_if (core_rsp_if),
.req_out_if (arb_core_req_if),
.rsp_out_if (arb_core_rsp_if)
.bus_in_if (core_bus_if),
.bus_out_if (arb_core_bus_if)
);
for (genvar i = 0; i < NUM_CACHES; ++i) begin
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (`WORD_WIDTH),
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_req_m_if[NUM_REQS]();
VX_mem_rsp_if #(
.DATA_WIDTH (`WORD_WIDTH),
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_rsp_m_if[NUM_REQS]();
) arb_core_bus_m_if[NUM_REQS]();
for (genvar j = 0; j < NUM_REQS; ++j) begin
`CACHE_REQ_TO_MEM(arb_core_req_m_if, arb_core_req_if[i], j);
end
for (genvar j = 0; j < NUM_REQS; ++j) begin
`CACHE_RSP_FROM_MEM(arb_core_rsp_if[i], arb_core_rsp_m_if, j);
`CACHE_BUS_TO_MEM(arb_core_bus_m_if, arb_core_bus_if[i], j);
end
`RESET_RELAY (cache_reset, reset);
@ -181,10 +150,8 @@ module VX_cache_cluster #(
.clk (clk),
.reset (cache_reset),
.core_req_if (arb_core_req_m_if),
.core_rsp_if (arb_core_rsp_m_if),
.mem_req_if (cache_mem_req_if[i]),
.mem_rsp_if (cache_mem_rsp_if[i])
.core_bus_if (arb_core_bus_m_if),
.mem_bus_if (cache_mem_bus_if[i])
);
end
@ -201,10 +168,8 @@ module VX_cache_cluster #(
) mem_arb (
.clk (clk),
.reset (mem_arb_reset),
.req_in_if (cache_mem_req_if),
.rsp_in_if (cache_mem_rsp_if),
.req_out_if (mem_req_if),
.rsp_out_if (mem_rsp_if)
.bus_in_if (cache_mem_bus_if),
.bus_out_if (mem_bus_if)
);
endmodule
@ -304,61 +269,50 @@ module VX_cache_cluster_top #(
input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready
);
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (NUM_REQS),
.WORD_SIZE (WORD_SIZE),
.TAG_WIDTH (TAG_WIDTH)
) core_req_if[NUM_INPUTS]();
) core_bus_if[NUM_INPUTS]();
VX_cache_rsp_if #(
.NUM_REQS (NUM_REQS),
.WORD_SIZE (WORD_SIZE),
.TAG_WIDTH (TAG_WIDTH)
) core_rsp_if[NUM_INPUTS]();
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (`LINE_WIDTH),
.TAG_WIDTH (MEM_TAG_WIDTH)
) mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (`LINE_WIDTH),
.TAG_WIDTH (MEM_TAG_WIDTH)
) mem_rsp_if();
) mem_bus_if();
// Core request
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign core_req_if[i].valid = core_req_valid[i];
assign core_req_if[i].rw = core_req_rw[i];
assign core_req_if[i].byteen = core_req_byteen[i];
assign core_req_if[i].addr = core_req_addr[i];
assign core_req_if[i].data = core_req_data[i];
assign core_req_if[i].tag = core_req_tag[i];
assign core_req_ready[i] = core_req_if[i].ready;
assign core_bus_if[i].req_valid = core_req_valid[i];
assign core_bus_if[i].req_rw = core_req_rw[i];
assign core_bus_if[i].req_byteen = core_req_byteen[i];
assign core_bus_if[i].req_addr = core_req_addr[i];
assign core_bus_if[i].req_data = core_req_data[i];
assign core_bus_if[i].req_tag = core_req_tag[i];
assign core_req_ready[i] = core_bus_if[i].req_ready;
end
// Core response
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign core_rsp_valid[i] = core_rsp_if[i].valid;
assign core_rsp_data[i] = core_rsp_if[i].data;
assign core_rsp_tag[i] = core_rsp_if[i].tag;
assign core_rsp_if[i].ready = core_rsp_ready[i];
assign core_rsp_valid[i] = core_bus_if[i].rsp_valid;
assign core_rsp_data[i] = core_bus_if[i].rsp_data;
assign core_rsp_tag[i] = core_bus_if[i].rsp_tag;
assign core_bus_if[i].rsp_ready = core_rsp_ready[i];
end
// Memory request
assign mem_req_valid = mem_req_if.valid;
assign mem_req_rw = mem_req_if.rw;
assign mem_req_byteen = mem_req_if.byteen;
assign mem_req_addr = mem_req_if.addr;
assign mem_req_data = mem_req_if.data;
assign mem_req_tag = mem_req_if.tag;
assign mem_req_if.ready = mem_req_ready;
assign mem_req_valid = mem_bus_if.req_valid;
assign mem_req_rw = mem_bus_if.req_rw;
assign mem_req_byteen = mem_bus_if.req_byteen;
assign mem_req_addr = mem_bus_if.req_addr;
assign mem_req_data = mem_bus_if.req_data;
assign mem_req_tag = mem_bus_if.req_tag;
assign mem_bus_if.req_ready = mem_req_ready;
// Memory response
assign mem_rsp_if.valid = mem_rsp_valid;
assign mem_rsp_if.data = mem_rsp_data;
assign mem_rsp_if.tag = mem_rsp_tag;
assign mem_rsp_ready = mem_rsp_if.ready;
assign mem_bus_if.rsp_valid = mem_rsp_valid;
assign mem_bus_if.rsp_data = mem_rsp_data;
assign mem_bus_if.rsp_tag = mem_rsp_tag;
assign mem_rsp_ready = mem_bus_if.rsp_ready;
VX_cache_cluster #(
.INSTANCE_ID (INSTANCE_ID),
@ -387,10 +341,8 @@ module VX_cache_cluster_top #(
`endif
.clk (clk),
.reset (reset),
.core_req_if (core_req_if),
.core_rsp_if (core_rsp_if),
.mem_req_if (mem_req_if),
.mem_rsp_if (mem_rsp_if)
.core_bus_if (core_bus_if),
.mem_bus_if (mem_bus_if)
);
endmodule

39
hw/rtl/cache/VX_cache_req_if.sv vendored
View file

@ -1,39 +0,0 @@
`include "VX_cache_define.vh"
interface VX_cache_req_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1,
parameter ADDR_WIDTH = `XLEN - `CLOG2(WORD_SIZE),
parameter DATA_WIDTH = WORD_SIZE * 8
) ();
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0] rw;
wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen;
wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] addr;
wire [NUM_REQS-1:0][DATA_WIDTH-1:0] data;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
modport master (
output valid,
output rw,
output byteen,
output addr,
output data,
output tag,
input ready
);
modport slave (
input valid,
input rw,
input byteen,
input addr,
input data,
input tag,
output ready
);
endinterface

28
hw/rtl/cache/VX_cache_rsp_if.sv vendored
View file

@ -1,28 +0,0 @@
`include "VX_cache_define.vh"
interface VX_cache_rsp_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface

155
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -61,17 +61,8 @@ module VX_cache_wrap #(
VX_perf_cache_if.master perf_cache_if,
`endif
// Core request
VX_mem_req_if.slave core_req_if [NUM_REQS],
// Core response
VX_mem_rsp_if.master core_rsp_if [NUM_REQS],
// Memory request
VX_mem_req_if.master mem_req_if,
// Memory response
VX_mem_rsp_if.slave mem_rsp_if
VX_mem_bus_if.slave core_bus_if [NUM_REQS],
VX_mem_bus_if.master mem_bus_if
);
`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid parameter"))
@ -99,13 +90,13 @@ module VX_cache_wrap #(
wire [NUM_REQS-1:0] core_req_ready;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_valid[i] = core_req_if[i].valid;
assign core_req_rw[i] = core_req_if[i].rw;
assign core_req_addr[i] = core_req_if[i].addr;
assign core_req_byteen[i] = core_req_if[i].byteen;
assign core_req_data[i] = core_req_if[i].data;
assign core_req_tag[i] = core_req_if[i].tag;
assign core_req_if[i].ready = core_req_ready[i];
assign core_req_valid[i] = core_bus_if[i].req_valid;
assign core_req_rw[i] = core_bus_if[i].req_rw;
assign core_req_addr[i] = core_bus_if[i].req_addr;
assign core_req_byteen[i] = core_bus_if[i].req_byteen;
assign core_req_data[i] = core_bus_if[i].req_data;
assign core_req_tag[i] = core_bus_if[i].req_tag;
assign core_bus_if[i].req_ready = core_req_ready[i];
end
///////////////////////////////////////////////////////////////////////////
@ -129,9 +120,9 @@ module VX_cache_wrap #(
.valid_in (core_rsp_valid_s[i]),
.ready_in (core_rsp_ready_s[i]),
.data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}),
.data_out ({core_rsp_if[i].data, core_rsp_if[i].tag}),
.valid_out (core_rsp_if[i].valid),
.ready_out (core_rsp_if[i].ready)
.data_out ({core_bus_if[i].rsp_data, core_bus_if[i].rsp_tag}),
.valid_out (core_bus_if[i].rsp_valid),
.ready_out (core_bus_if[i].rsp_ready)
);
end
@ -156,9 +147,9 @@ module VX_cache_wrap #(
.valid_in (mem_req_valid_s),
.ready_in (mem_req_ready_s),
.data_in ({mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_data_s, mem_req_tag_s}),
.data_out ({mem_req_if.rw, mem_req_if.byteen, mem_req_if.addr, mem_req_if.data, mem_req_if.tag}),
.valid_out (mem_req_if.valid),
.ready_out (mem_req_if.ready)
.data_out ({mem_bus_if.req_rw, mem_bus_if.req_byteen, mem_bus_if.req_addr, mem_bus_if.req_data, mem_bus_if.req_tag}),
.valid_out (mem_bus_if.req_valid),
.ready_out (mem_bus_if.req_ready)
);
///////////////////////////////////////////////////////////////////////////
@ -267,10 +258,10 @@ module VX_cache_wrap #(
.mem_req_ready_out (mem_req_ready_s),
// Memory response in
.mem_rsp_valid_in (mem_rsp_if.valid),
.mem_rsp_data_in (mem_rsp_if.data),
.mem_rsp_tag_in (mem_rsp_if.tag),
.mem_rsp_ready_in (mem_rsp_if.ready),
.mem_rsp_valid_in (mem_bus_if.rsp_valid),
.mem_rsp_data_in (mem_bus_if.rsp_data),
.mem_rsp_tag_in (mem_bus_if.rsp_tag),
.mem_rsp_ready_in (mem_bus_if.rsp_ready),
// Memory response out
.mem_rsp_valid_out (mem_rsp_valid_b),
@ -310,9 +301,9 @@ module VX_cache_wrap #(
.data_out (mem_req_tag_s)
);
assign mem_rsp_valid_b = mem_rsp_if.valid;
assign mem_rsp_data_b = mem_rsp_if.data;
assign mem_rsp_if.ready = mem_rsp_ready_b;
assign mem_rsp_valid_b = mem_bus_if.rsp_valid;
assign mem_rsp_data_b = mem_bus_if.rsp_data;
assign mem_bus_if.rsp_ready = mem_rsp_ready_b;
// Remove NC flag from the memory response tag
@ -320,7 +311,7 @@ module VX_cache_wrap #(
.N (MEM_TAG_WIDTH),
.POS (NC_TAG_BIT)
) mem_rsp_tag_remove (
.data_in (mem_rsp_if.tag),
.data_in (mem_bus_if.rsp_tag),
.data_out (mem_rsp_tag_b)
);
end
@ -366,55 +357,45 @@ module VX_cache_wrap #(
end else begin
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (`WORD_WIDTH),
.TAG_WIDTH (CORE_TAG_X_WIDTH)
) core_req_wrap_if[NUM_REQS]();
VX_mem_rsp_if #(
.DATA_WIDTH (`WORD_WIDTH),
.TAG_WIDTH (CORE_TAG_X_WIDTH)
) core_rsp_wrap_if[NUM_REQS]();
) core_bus_wrap_if[NUM_REQS]();
VX_mem_req_if #(
VX_mem_bus_if #(
.DATA_WIDTH (`LINE_WIDTH),
.TAG_WIDTH (MEM_TAG_X_WIDTH)
) mem_req_wrap_if();
VX_mem_rsp_if #(
.DATA_WIDTH (`LINE_WIDTH),
.TAG_WIDTH (MEM_TAG_X_WIDTH)
) mem_rsp_wrap_if();
) mem_bus_wrap_if();
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_wrap_if[i].valid = core_req_valid_b[i];
assign core_req_wrap_if[i].rw = core_req_rw_b[i];
assign core_req_wrap_if[i].addr = core_req_addr_b[i];
assign core_req_wrap_if[i].byteen = core_req_byteen_b[i];
assign core_req_wrap_if[i].data = core_req_data_b[i];
assign core_req_wrap_if[i].tag = core_req_tag_b[i];
assign core_req_ready_b[i] = core_req_wrap_if[i].ready;
assign core_bus_wrap_if[i].req_valid = core_req_valid_b[i];
assign core_bus_wrap_if[i].req_rw = core_req_rw_b[i];
assign core_bus_wrap_if[i].req_addr = core_req_addr_b[i];
assign core_bus_wrap_if[i].req_byteen = core_req_byteen_b[i];
assign core_bus_wrap_if[i].req_data = core_req_data_b[i];
assign core_bus_wrap_if[i].req_tag = core_req_tag_b[i];
assign core_req_ready_b[i] = core_bus_wrap_if[i].req_ready;
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_rsp_valid_b[i] = core_rsp_wrap_if[i].valid;
assign core_rsp_data_b[i] = core_rsp_wrap_if[i].data;
assign core_rsp_tag_b[i] = core_rsp_wrap_if[i].tag;
assign core_rsp_wrap_if[i].ready = core_rsp_ready_b[i];
assign core_rsp_valid_b[i] = core_bus_wrap_if[i].rsp_valid;
assign core_rsp_data_b[i] = core_bus_wrap_if[i].rsp_data;
assign core_rsp_tag_b[i] = core_bus_wrap_if[i].rsp_tag;
assign core_bus_wrap_if[i].rsp_ready = core_rsp_ready_b[i];
end
assign mem_req_valid_b = mem_req_wrap_if.valid;
assign mem_req_addr_b = mem_req_wrap_if.addr;
assign mem_req_rw_b = mem_req_wrap_if.rw;
assign mem_req_byteen_b = mem_req_wrap_if.byteen;
assign mem_req_data_b = mem_req_wrap_if.data;
assign mem_req_tag_b = mem_req_wrap_if.tag;
assign mem_req_wrap_if.ready = mem_req_ready_b;
assign mem_req_valid_b = mem_bus_wrap_if.req_valid;
assign mem_req_addr_b = mem_bus_wrap_if.req_addr;
assign mem_req_rw_b = mem_bus_wrap_if.req_rw;
assign mem_req_byteen_b = mem_bus_wrap_if.req_byteen;
assign mem_req_data_b = mem_bus_wrap_if.req_data;
assign mem_req_tag_b = mem_bus_wrap_if.req_tag;
assign mem_bus_wrap_if.req_ready = mem_req_ready_b;
assign mem_rsp_wrap_if.valid = mem_rsp_valid_b;
assign mem_rsp_wrap_if.data = mem_rsp_data_b;
assign mem_rsp_wrap_if.tag = mem_rsp_tag_b;
assign mem_rsp_ready_b = mem_rsp_wrap_if.ready;
assign mem_bus_wrap_if.rsp_valid = mem_rsp_valid_b;
assign mem_bus_wrap_if.rsp_data = mem_rsp_data_b;
assign mem_bus_wrap_if.rsp_tag = mem_rsp_tag_b;
assign mem_rsp_ready_b = mem_bus_wrap_if.rsp_ready;
`RESET_RELAY (cache_reset, reset);
@ -445,10 +426,8 @@ module VX_cache_wrap #(
.perf_cache_if (perf_cache_if),
`endif
.core_req_if (core_req_wrap_if),
.core_rsp_if (core_rsp_wrap_if),
.mem_req_if (mem_req_wrap_if),
.mem_rsp_if (mem_rsp_wrap_if)
.core_bus_if (core_bus_wrap_if),
.mem_bus_if (mem_bus_wrap_if)
);
end
@ -460,25 +439,25 @@ module VX_cache_wrap #(
wire [`UP(UUID_WIDTH)-1:0] core_rsp_uuid;
if (UUID_WIDTH != 0) begin
assign core_req_uuid = core_req_if[i].tag[TAG_WIDTH-1 -: UUID_WIDTH];
assign core_rsp_uuid = core_rsp_if[i].tag[TAG_WIDTH-1 -: UUID_WIDTH];
assign core_req_uuid = core_bus_if[i].req_tag[TAG_WIDTH-1 -: UUID_WIDTH];
assign core_rsp_uuid = core_bus_if[i].rsp_tag[TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
assign core_req_uuid = 0;
assign core_rsp_uuid = 0;
end
wire core_req_fire = core_req_if[i].valid && core_req_if[i].ready;
wire core_rsp_fire = core_rsp_if[i].valid && core_rsp_if[i].ready;
wire core_req_fire = core_bus_if[i].req_valid && core_bus_if[i].req_ready;
wire core_rsp_fire = core_bus_if[i].rsp_valid && core_bus_if[i].rsp_ready;
always @(posedge clk) begin
if (core_req_fire) begin
if (core_req_if[i].rw)
`TRACE(1, ("%d: %s core-wr-req: tid=%0d, addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, `TO_FULL_ADDR(core_req_if[i].addr), core_req_if[i].tag, core_req_if[i].byteen, core_req_if[i].data, core_req_uuid));
if (core_bus_if[i].req_rw)
`TRACE(1, ("%d: %s core-wr-req: tid=%0d, addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, `TO_FULL_ADDR(core_bus_if[i].req_addr), core_bus_if[i].req_tag, core_bus_if[i].req_byteen, core_bus_if[i].req_data, core_req_uuid));
else
`TRACE(1, ("%d: %s core-rd-req: tid=%0d, addr=0x%0h, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, `TO_FULL_ADDR(core_req_if[i].addr), core_req_if[i].tag, core_req_uuid));
`TRACE(1, ("%d: %s core-rd-req: tid=%0d, addr=0x%0h, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, `TO_FULL_ADDR(core_bus_if[i].req_addr), core_bus_if[i].req_tag, core_req_uuid));
end
if (core_rsp_fire) begin
`TRACE(1, ("%d: %s core-rd-rsp: tid=%0d, tag=0x%0h, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, core_rsp_if[i].tag, core_rsp_if[i].data, core_rsp_uuid));
`TRACE(1, ("%d: %s core-rd-rsp: tid=%0d, tag=0x%0h, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, core_bus_if[i].rsp_tag, core_bus_if[i].rsp_data, core_rsp_uuid));
end
end
end
@ -487,25 +466,25 @@ module VX_cache_wrap #(
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_uuid;
if ((UUID_WIDTH != 0) && (NC_BYPASS != 0)) begin
assign mem_req_uuid = mem_req_if.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
assign mem_rsp_uuid = mem_rsp_if.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
assign mem_req_uuid = mem_bus_if.req_tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
assign mem_rsp_uuid = mem_bus_if.rsp_tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
end else begin
assign mem_req_uuid = '0;
assign mem_rsp_uuid = '0;
end
wire mem_req_fire = mem_req_if.valid && mem_req_if.ready;
wire mem_rsp_fire = mem_rsp_if.valid && mem_rsp_if.ready;
wire mem_req_fire = mem_bus_if.req_valid && mem_bus_if.req_ready;
wire mem_rsp_fire = mem_bus_if.rsp_valid && mem_bus_if.rsp_ready;
always @(posedge clk) begin
if (mem_req_fire) begin
if (mem_req_if.rw)
`TRACE(1, ("%d: %s mem-wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(mem_req_if.addr), mem_req_if.tag, mem_req_if.byteen, mem_req_if.data, mem_req_uuid));
if (mem_bus_if.req_rw)
`TRACE(1, ("%d: %s mem-wr-req: addr=0x%0h, tag=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_addr), mem_bus_if.req_tag, mem_bus_if.req_byteen, mem_bus_if.req_data, mem_req_uuid));
else
`TRACE(1, ("%d: %s mem-rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(mem_req_if.addr), mem_req_if.tag, mem_req_uuid));
`TRACE(1, ("%d: %s mem-rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_addr), mem_bus_if.req_tag, mem_req_uuid));
end
if (mem_rsp_fire) begin
`TRACE(1, ("%d: %s mem-rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, mem_rsp_if.tag, mem_rsp_if.data, mem_rsp_uuid));
`TRACE(1, ("%d: %s mem-rd-rsp: tag=0x%0h, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, mem_bus_if.rsp_tag, mem_bus_if.rsp_data, mem_rsp_uuid));
end
end
`endif

43
hw/rtl/cache/VX_smem_switch.sv vendored
View file

@ -12,18 +12,9 @@ module VX_smem_switch #(
) (
input wire clk,
input wire reset,
// input requests
VX_cache_req_if.slave req_in_if,
// input responses
VX_cache_rsp_if.master rsp_in_if,
// output request
VX_cache_req_if.master req_out_if [NUM_REQS],
// output response
VX_cache_rsp_if.slave rsp_out_if [NUM_REQS]
VX_cache_bus_if.slave bus_in_if,
VX_cache_bus_if.master bus_out_if [NUM_REQS]
);
localparam ADDR_WIDTH = (`XLEN-`CLOG2(DATA_SIZE));
localparam DATA_WIDTH = (8 * DATA_SIZE);
@ -47,17 +38,17 @@ module VX_smem_switch #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_remove (
.data_in (req_in_if.tag[i]),
.data_in (bus_in_if.req_tag[i]),
.data_out (req_tag_in)
);
if (NUM_REQS > 1) begin
assign req_sel_in = req_in_if.tag[i][TAG_SEL_IDX +: LOG_NUM_REQS];
assign req_sel_in = bus_in_if.req_tag[i][TAG_SEL_IDX +: LOG_NUM_REQS];
end else begin
assign req_sel_in = '0;
end
assign req_data_in = {req_tag_in, req_in_if.addr[i], req_in_if.rw[i], req_in_if.byteen[i], req_in_if.data[i]};
assign req_data_in = {req_tag_in, bus_in_if.req_addr[i], bus_in_if.req_rw[i], bus_in_if.req_byteen[i], bus_in_if.req_data[i]};
VX_stream_switch #(
.NUM_OUTPUTS (NUM_REQS),
@ -68,8 +59,8 @@ module VX_smem_switch #(
.clk (clk),
.reset (reset),
.sel_in (req_sel_in),
.valid_in (req_in_if.valid[i]),
.ready_in (req_in_if.ready[i]),
.valid_in (bus_in_if.req_valid[i]),
.ready_in (bus_in_if.req_ready[i]),
.data_in (req_data_in),
.data_out (req_data_out),
.valid_out (req_valid_out),
@ -77,9 +68,9 @@ module VX_smem_switch #(
);
for (genvar j = 0; j < NUM_REQS; ++j) begin
assign req_out_if[j].valid[i] = req_valid_out[j];
assign {req_out_if[j].tag[i], req_out_if[j].addr[i], req_out_if[j].rw[i], req_out_if[j].byteen[i], req_out_if[j].data[i]} = req_data_out[j];
assign req_ready_out[j] = req_out_if[j].ready[i];
assign bus_out_if[j].req_valid[i] = req_valid_out[j];
assign {bus_out_if[j].req_tag[i], bus_out_if[j].req_addr[i], bus_out_if[j].req_rw[i], bus_out_if[j].req_byteen[i], bus_out_if[j].req_data[i]} = req_data_out[j];
assign req_ready_out[j] = bus_out_if[j].req_ready[i];
end
end
@ -99,14 +90,14 @@ module VX_smem_switch #(
.S (LOG_NUM_REQS),
.POS (TAG_SEL_IDX)
) bits_insert (
.data_in (rsp_out_if[i].tag[j]),
.data_in (bus_out_if[i].rsp_tag[j]),
.sel_in (`UP(LOG_NUM_REQS)'(i)),
.data_out (rsp_tag_out)
);
assign rsp_valid_out[i][j] = rsp_out_if[i].valid[j];
assign rsp_data_out[i][j] = {rsp_tag_out, rsp_out_if[i].data[j]};
assign rsp_out_if[i].ready[j] = rsp_ready_out[i][j];
assign rsp_valid_out[i][j] = bus_out_if[i].rsp_valid[j];
assign rsp_data_out[i][j] = {rsp_tag_out, bus_out_if[i].rsp_data[j]};
assign bus_out_if[i].rsp_ready[j] = rsp_ready_out[i][j];
end
end
@ -123,12 +114,12 @@ module VX_smem_switch #(
.ready_in (rsp_ready_out),
.data_in (rsp_data_out),
.data_out (rsp_data_in),
.valid_out (rsp_in_if.valid),
.ready_out (rsp_in_if.ready)
.valid_out (bus_in_if.rsp_valid),
.ready_out (bus_in_if.rsp_ready)
);
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign {rsp_in_if.tag[i], rsp_in_if.data[i]} = rsp_data_in[i];
assign {bus_in_if.rsp_tag[i], bus_in_if.rsp_data[i]} = rsp_data_in[i];
end
endmodule

92
hw/rtl/core/VX_core.sv
View file

@ -39,11 +39,9 @@ module VX_core #(
VX_dcr_write_if.slave dcr_write_if,
VX_cache_req_if.master dcache_req_if,
VX_cache_rsp_if.slave dcache_rsp_if,
VX_cache_bus_if.master dcache_bus_if,
VX_cache_req_if.master icache_req_if,
VX_cache_rsp_if.slave icache_rsp_if,
VX_cache_bus_if.master icache_bus_if,
`ifdef EXT_F_ENABLE
VX_fpu_req_if.master fpu_req_if,
@ -139,8 +137,7 @@ module VX_core #(
.clk (clk),
.reset (fetch_reset),
.base_dcrs (base_dcrs),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
.icache_bus_if (icache_bus_if),
.wrelease_if (wrelease_if),
.join_if (join_if),
.warp_ctl_if (warp_ctl_if),
@ -202,8 +199,7 @@ module VX_core #(
.perf_pipeline_if(perf_pipeline_if),
`endif
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
.dcache_bus_if (dcache_bus_if),
`ifdef EXT_F_ENABLE
.fpu_agent_if (fpu_agent_if),
@ -298,12 +294,12 @@ module VX_core #(
reg [`PERF_CTR_BITS-1:0] perf_loads;
reg [`PERF_CTR_BITS-1:0] perf_stores;
wire [ICACHE_NUM_REQS-1:0] perf_icache_req_fire = icache_req_if.valid & icache_req_if.ready;
wire [ICACHE_NUM_REQS-1:0] perf_icache_rsp_fire = icache_rsp_if.valid & icache_rsp_if.ready;
wire [ICACHE_NUM_REQS-1:0] perf_icache_req_fire = icache_bus_if.req_valid & icache_bus_if.req_ready;
wire [ICACHE_NUM_REQS-1:0] perf_icache_rsp_fire = icache_bus_if.rsp_valid & icache_bus_if.rsp_ready;
wire [DCACHE_NUM_REQS-1:0] perf_dcache_rd_req_fire = dcache_req_if.valid & ~dcache_req_if.rw & dcache_req_if.ready;
wire [DCACHE_NUM_REQS-1:0] perf_dcache_wr_req_fire = dcache_req_if.valid & dcache_req_if.rw & dcache_req_if.ready;
wire [DCACHE_NUM_REQS-1:0] perf_dcache_rsp_fire = dcache_rsp_if.valid & dcache_rsp_if.ready;
wire [DCACHE_NUM_REQS-1:0] perf_dcache_rd_req_fire = dcache_bus_if.req_valid & ~dcache_bus_if.req_rw & dcache_bus_if.req_ready;
wire [DCACHE_NUM_REQS-1:0] perf_dcache_wr_req_fire = dcache_bus_if.req_valid & dcache_bus_if.req_rw & dcache_bus_if.req_ready;
wire [DCACHE_NUM_REQS-1:0] perf_dcache_rsp_fire = dcache_bus_if.rsp_valid & dcache_bus_if.rsp_ready;
`POP_COUNT(perf_icache_req_per_cycle, perf_icache_req_fire);
`POP_COUNT(perf_dcache_rd_req_per_cycle, perf_dcache_rd_req_fire);
@ -479,55 +475,43 @@ module VX_core_top #(
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) dcache_req_if();
) dcache_bus_if();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_TAG_WIDTH)
) dcache_rsp_if();
assign dcache_req_valid = dcache_bus_if.req_valid;
assign dcache_req_rw = dcache_bus_if.req_rw;
assign dcache_req_byteen = dcache_bus_if.req_byteen;
assign dcache_req_addr = dcache_bus_if.req_addr;
assign dcache_req_data = dcache_bus_if.req_data;
assign dcache_req_tag = dcache_bus_if.req_tag;
assign dcache_bus_if.req_ready = dcache_req_ready;
assign dcache_req_valid = dcache_req_if.valid;
assign dcache_req_rw = dcache_req_if.rw;
assign dcache_req_byteen = dcache_req_if.byteen;
assign dcache_req_addr = dcache_req_if.addr;
assign dcache_req_data = dcache_req_if.data;
assign dcache_req_tag = dcache_req_if.tag;
assign dcache_req_if.ready = dcache_req_ready;
assign dcache_bus_if.rsp_valid = dcache_rsp_valid;
assign dcache_bus_if.rsp_tag = dcache_rsp_tag;
assign dcache_bus_if.rsp_data = dcache_rsp_data;
assign dcache_rsp_ready = dcache_bus_if.rsp_ready;
assign dcache_rsp_if.valid = dcache_rsp_valid;
assign dcache_rsp_if.tag = dcache_rsp_tag;
assign dcache_rsp_if.data = dcache_rsp_data;
assign dcache_rsp_ready = dcache_rsp_if.ready;
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_TAG_WIDTH)
) icache_req_if();
) icache_bus_if();
VX_cache_rsp_if #(
.NUM_REQS (ICACHE_NUM_REQS),
.WORD_SIZE (ICACHE_WORD_SIZE),
.TAG_WIDTH (ICACHE_TAG_WIDTH)
) icache_rsp_if();
assign icache_req_valid = icache_bus_if.req_valid;
assign icache_req_rw = icache_bus_if.req_rw;
assign icache_req_byteen = icache_bus_if.req_byteen;
assign icache_req_addr = icache_bus_if.req_addr;
assign icache_req_data = icache_bus_if.req_data;
assign icache_req_tag = icache_bus_if.req_tag;
assign icache_bus_if.req_ready = icache_req_ready;
assign icache_req_valid = icache_req_if.valid;
assign icache_req_rw = icache_req_if.rw;
assign icache_req_byteen = icache_req_if.byteen;
assign icache_req_addr = icache_req_if.addr;
assign icache_req_data = icache_req_if.data;
assign icache_req_tag = icache_req_if.tag;
assign icache_req_if.ready = icache_req_ready;
assign icache_rsp_if.valid = icache_rsp_valid;
assign icache_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_if.data = icache_rsp_data;
assign icache_rsp_ready = icache_rsp_if.ready;
assign icache_bus_if.rsp_valid = icache_rsp_valid;
assign icache_bus_if.rsp_tag = icache_rsp_tag;
assign icache_bus_if.rsp_data = icache_rsp_data;
assign icache_rsp_ready = icache_bus_if.rsp_ready;
`ifdef EXT_F_ENABLE
VX_fpu_req_if #(
@ -626,11 +610,9 @@ module VX_core_top #(
.dcr_write_if (dcr_write_if),
.dcache_req_if (dcache_req_if),
.dcache_rsp_if (dcache_rsp_if),
.dcache_bus_if (dcache_bus_if),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
.icache_bus_if (icache_bus_if),
`ifdef EXT_F_ENABLE
.fpu_req_if (fpu_req_if),

6
hw/rtl/core/VX_execute.sv
View file

@ -16,8 +16,7 @@ module VX_execute #(
input base_dcrs_t base_dcrs,
// Dcache interface
VX_cache_req_if.master dcache_req_if,
VX_cache_rsp_if.slave dcache_rsp_if,
VX_cache_bus_if.master dcache_bus_if,
// commit interface
VX_cmt_to_csr_if.slave cmt_to_csr_if,
@ -128,8 +127,7 @@ module VX_execute #(
`SCOPE_IO_BIND (0)
.clk (clk),
.reset (lsu_reset),
.cache_req_if (dcache_req_if),
.cache_rsp_if (dcache_rsp_if),
.cache_bus_if (dcache_bus_if),
.lsu_req_if (lsu_req_if),
.ld_commit_if (ld_commit_if),
.st_commit_if (st_commit_if)

18
hw/rtl/core/VX_fetch.sv
View file

@ -16,8 +16,7 @@ module VX_fetch #(
input base_dcrs_t base_dcrs,
// Icache interface
VX_cache_req_if.master icache_req_if,
VX_cache_rsp_if.slave icache_rsp_if,
VX_cache_bus_if.master icache_bus_if,
// inputs
VX_wrelease_if.slave wrelease_if,
@ -70,8 +69,7 @@ module VX_fetch #(
.clk (clk),
.reset (reset),
.icache_req_if (icache_req_if),
.icache_rsp_if (icache_rsp_if),
.icache_bus_if (icache_bus_if),
.ifetch_req_if (ifetch_req_if),
.ifetch_rsp_if (ifetch_rsp_if)
@ -82,8 +80,8 @@ module VX_fetch #(
`ifdef SCOPE
localparam UUID_WIDTH = `UP(`UUID_BITS);
wire ifetch_req_fire = ifetch_req_if.valid && ifetch_req_if.ready;
wire icache_req_fire = icache_req_if.valid && icache_req_if.ready;
wire icache_rsp_fire = icache_rsp_if.valid && icache_rsp_if.ready;
wire icache_req_fire = icache_bus_if.req_valid && icache_bus_if.req_ready;
wire icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready;
VX_scope_tap #(
.SCOPE_ID (1),
.TRIGGERW (7),
@ -104,8 +102,8 @@ module VX_fetch #(
}),
.probes({
ifetch_req_if.uuid, ifetch_req_if.wid, ifetch_req_if.tmask, ifetch_req_if.PC,
icache_req_if.tag, icache_req_if.byteen, icache_req_if.addr,
icache_rsp_if.data, icache_rsp_if.tag,
icache_bus_if.req_tag, icache_bus_if.req_byteen, icache_bus_if.req_addr,
icache_bus_if.rsp_data, icache_bus_if.rsp_tag,
join_if.wid, warp_ctl_if.barrier, warp_ctl_if.split, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.wid,
branch_ctl_if.dest, branch_ctl_if.taken, branch_ctl_if.wid
}),
@ -117,8 +115,8 @@ module VX_fetch #(
ila_fetch ila_fetch_inst (
.clk (clk),
.probe0 ({reset, ifetch_req_if.uuid, ifetch_req_if.wid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.ready, ifetch_req_if.valid}),
.probe1 ({icache_req_if.tag, icache_req_if.byteen, icache_req_if.addr, icache_req_if.ready, icache_req_if.valid}),
.probe2 ({icache_rsp_if.data, icache_rsp_if.tag, icache_rsp_if.ready, icache_rsp_if.valid}),
.probe1 ({icache_bus_if.req_tag, icache_bus_if.req_byteen, icache_bus_if.req_addr, icache_bus_if.req_ready, icache_bus_if.req_valid}),
.probe2 ({icache_bus_if.rsp_data, icache_bus_if.rsp_tag, icache_bus_if.rsp_ready, icache_bus_if.rsp_valid}),
.probe3 ({join_if.wid, join_if.valid, warp_ctl_if.barrier, warp_ctl_if.split, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.wid, warp_ctl_if.valid}),
.probe4 ({branch_ctl_if.dest, branch_ctl_if.taken, branch_ctl_if.wid, branch_ctl_if.valid})
);

25
hw/rtl/core/VX_icache_stage.sv
View file

@ -12,8 +12,7 @@ module VX_icache_stage #(
input wire reset,
// Icache interface
VX_cache_req_if.master icache_req_if,
VX_cache_rsp_if.slave icache_rsp_if,
VX_cache_bus_if.master icache_bus_if,
// request
VX_ifetch_req_if.slave ifetch_req_if,
@ -39,7 +38,7 @@ module VX_icache_stage #(
assign req_tag = ifetch_req_if.wid;
assign {rsp_uuid, rsp_tag} = icache_rsp_if.tag;
assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_tag;
wire [`XLEN-1:0] rsp_PC;
wire [`NUM_THREADS-1:0] rsp_tmask;
@ -94,29 +93,29 @@ module VX_icache_stage #(
.reset (reset),
.valid_in (icache_req_valid),
.ready_in (icache_req_ready),
.data_in ({icache_req_addr, icache_req_tag}),
.data_out ({icache_req_if.addr, icache_req_if.tag}),
.valid_out (icache_req_if.valid),
.ready_out (icache_req_if.ready)
.data_in ({icache_req_addr, icache_req_tag}),
.data_out ({icache_bus_if.req_addr, icache_bus_if.req_tag}),
.valid_out (icache_bus_if.req_valid),
.ready_out (icache_bus_if.req_ready)
);
assign icache_req_if.rw = 0;
assign icache_req_if.byteen = 4'b1111;
assign icache_req_if.data = '0;
assign icache_bus_if.req_rw = 0;
assign icache_bus_if.req_byteen = 4'b1111;
assign icache_bus_if.req_data = '0;
// Icache Response
wire [NW_WIDTH-1:0] rsp_wid = rsp_tag;
assign ifetch_rsp_if.valid = icache_rsp_if.valid;
assign ifetch_rsp_if.valid = icache_bus_if.rsp_valid;
assign ifetch_rsp_if.tmask = rsp_tmask;
assign ifetch_rsp_if.wid = rsp_wid;
assign ifetch_rsp_if.PC = rsp_PC;
assign ifetch_rsp_if.data = icache_rsp_if.data;
assign ifetch_rsp_if.data = icache_bus_if.rsp_data;
assign ifetch_rsp_if.uuid = rsp_uuid;
// Can accept new response?
assign icache_rsp_if.ready = ifetch_rsp_if.ready;
assign icache_bus_if.rsp_ready = ifetch_rsp_if.ready;
`ifdef DBG_TRACE_CORE_ICACHE
wire ifetch_req_fire = ifetch_req_if.valid && ifetch_req_if.ready;

58
hw/rtl/core/VX_lsu_unit.sv
View file

@ -14,8 +14,7 @@ module VX_lsu_unit #(
input wire reset,
// Dcache interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// inputs
VX_lsu_req_if.slave lsu_req_if,
@ -192,17 +191,11 @@ module VX_lsu_unit #(
assign mem_req_tag = {lsu_req_if.uuid, lsu_addr_type, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rd, lsu_req_if.op_type, req_align, lsu_is_dup};
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (UUID_WIDTH + (`NUM_THREADS * `CACHE_ADDR_TYPE_BITS) + LSUQ_TAG_BITS)
) cache_req_tmp_if();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (UUID_WIDTH + (`NUM_THREADS * `CACHE_ADDR_TYPE_BITS) + LSUQ_TAG_BITS)
) cache_rsp_tmp_if();
) cache_bus_tmp_if();
`RESET_RELAY (mem_scheduler_reset, reset);
@ -243,19 +236,19 @@ module VX_lsu_unit #(
.rsp_ready (mem_rsp_ready),
// Memory request
.mem_req_valid (cache_req_tmp_if.valid),
.mem_req_rw (cache_req_tmp_if.rw),
.mem_req_byteen (cache_req_tmp_if.byteen),
.mem_req_addr (cache_req_tmp_if.addr),
.mem_req_data (cache_req_tmp_if.data),
.mem_req_tag (cache_req_tmp_if.tag),
.mem_req_ready (cache_req_tmp_if.ready),
.mem_req_valid (cache_bus_tmp_if.req_valid),
.mem_req_rw (cache_bus_tmp_if.req_rw),
.mem_req_byteen (cache_bus_tmp_if.req_byteen),
.mem_req_addr (cache_bus_tmp_if.req_addr),
.mem_req_data (cache_bus_tmp_if.req_data),
.mem_req_tag (cache_bus_tmp_if.req_tag),
.mem_req_ready (cache_bus_tmp_if.req_ready),
// Memory response
.mem_rsp_valid (cache_rsp_tmp_if.valid),
.mem_rsp_data (cache_rsp_tmp_if.data),
.mem_rsp_tag (cache_rsp_tmp_if.tag),
.mem_rsp_ready (cache_rsp_tmp_if.ready)
.mem_rsp_valid (cache_bus_tmp_if.rsp_valid),
.mem_rsp_data (cache_bus_tmp_if.rsp_data),
.mem_rsp_tag (cache_bus_tmp_if.rsp_tag),
.mem_rsp_ready (cache_bus_tmp_if.rsp_ready)
);
wire mem_req_fire = mem_req_valid && mem_req_ready;
@ -265,8 +258,7 @@ module VX_lsu_unit #(
// cache tag formatting: <uuid, tag, type>
`ASSIGN_VX_CACHE_REQ_IF_XTAG (cache_req_if, cache_req_tmp_if);
`ASSIGN_VX_CACHE_RSP_IF_XTAG (cache_rsp_tmp_if, cache_rsp_if);
`ASSIGN_VX_CACHE_BUS_IF_XTAG (cache_bus_if, cache_bus_tmp_if);
for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
wire [UUID_WIDTH-1:0] cache_req_uuid, cache_rsp_uuid;
@ -279,13 +271,13 @@ module VX_lsu_unit #(
wire [`CACHE_ADDR_TYPE_BITS-1:0] cache_req_type_bi, cache_rsp_type_bi;
wire [DCACHE_BATCH_SEL_BITS-1:0] cache_req_bid, cache_rsp_bid;
assign {cache_req_uuid, cache_req_type, cache_req_bid, cache_req_tag} = cache_req_tmp_if.tag[i];
assign {cache_req_uuid, cache_req_type, cache_req_bid, cache_req_tag} = cache_bus_tmp_if.req_tag[i];
assign cache_req_type_bi = cache_req_type_b[cache_req_bid];
assign cache_req_if.tag[i] = {cache_req_uuid, cache_req_bid, cache_req_tag, cache_req_type_bi};
assign cache_bus_if.req_tag[i] = {cache_req_uuid, cache_req_bid, cache_req_tag, cache_req_type_bi};
assign {cache_rsp_uuid, cache_rsp_bid, cache_rsp_tag, cache_rsp_type_bi} = cache_rsp_if.tag[i];
assign {cache_rsp_uuid, cache_rsp_bid, cache_rsp_tag, cache_rsp_type_bi} = cache_bus_if.rsp_tag[i];
assign cache_rsp_type_b = {DCACHE_NUM_BATCHES{cache_rsp_type_bi}};
assign cache_rsp_tmp_if.tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_bid, cache_rsp_tag};
assign cache_bus_tmp_if.rsp_tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_bid, cache_rsp_tag};
for (genvar j = 0; j < DCACHE_NUM_BATCHES; ++j) begin
localparam k = j * DCACHE_NUM_REQS + i;
@ -300,11 +292,11 @@ module VX_lsu_unit #(
end else begin
assign {cache_req_uuid, cache_req_type, cache_req_tag} = cache_req_tmp_if.tag[i];
assign cache_req_if.tag[i] = {cache_req_uuid, cache_req_tag, cache_req_type[i]};
assign {cache_req_uuid, cache_req_type, cache_req_tag} = cache_bus_tmp_if.req_tag[i];
assign cache_bus_if.req_tag[i] = {cache_req_uuid, cache_req_tag, cache_req_type[i]};
assign {cache_rsp_uuid, cache_rsp_tag, cache_rsp_type[i]} = cache_rsp_if.tag[i];
assign cache_rsp_tmp_if.tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_tag};
assign {cache_rsp_uuid, cache_rsp_tag, cache_rsp_type[i]} = cache_bus_if.rsp_tag[i];
assign cache_bus_tmp_if.rsp_tag[i] = {cache_rsp_uuid, cache_rsp_type, cache_rsp_tag};
for (genvar j = 0; j < DCACHE_NUM_REQS; ++j) begin
if (i != j) begin
@ -426,8 +418,8 @@ module VX_lsu_unit #(
.clk (clk),
.probe0 ({mem_req_data_0, lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.PC, mem_req_mask, full_addr_0, mem_req_byteen, mem_req_rw, mem_req_ready, mem_req_valid}),
.probe1 ({rsp_data_0, rsp_uuid, mem_rsp_eop, rsp_pc, rsp_rd, rsp_tmask, rsp_wid, mem_rsp_ready, mem_rsp_valid}),
.probe2 ({cache_req_if.data, cache_req_if.tag, cache_req_if.byteen, cache_req_if.addr, cache_req_if.rw, cache_req_if.ready, cache_req_if.valid}),
.probe3 ({cache_rsp_if.data, cache_rsp_if.tag, cache_rsp_if.ready, cache_rsp_if.valid})
.probe2 ({cache_bus_if.req_data, cache_bus_if.req_tag, cache_bus_if.req_byteen, cache_bus_if.req_addr, cache_bus_if.req_rw, cache_bus_if.req_ready, cache_bus_if.req_valid}),
.probe3 ({cache_bus_if.rsp_data, cache_bus_if.rsp_tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid})
);
`endif
end

53
hw/rtl/interfaces/VX_mem_bus_if.sv Normal file
View file

@ -0,0 +1,53 @@
`include "VX_define.vh"
interface VX_mem_bus_if #(
parameter DATA_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8,
parameter ADDR_WIDTH = `XLEN - `CLOG2(DATA_SIZE),
parameter TAG_WIDTH = 1
) ();
wire req_valid;
wire req_rw;
wire [DATA_SIZE-1:0] req_byteen;
wire [ADDR_WIDTH-1:0] req_addr;
wire [DATA_WIDTH-1:0] req_data;
wire [TAG_WIDTH-1:0] req_tag;
wire req_ready;
wire rsp_valid;
wire [DATA_WIDTH-1:0] rsp_data;
wire [TAG_WIDTH-1:0] rsp_tag;
wire rsp_ready;
modport master (
output req_valid,
output req_rw,
output req_byteen,
output req_addr,
output req_data,
output req_tag,
input req_ready,
input rsp_valid,
input rsp_data,
input rsp_tag,
output rsp_ready
);
modport slave (
input req_valid,
input req_rw,
input req_byteen,
input req_addr,
input req_data,
input req_tag,
output req_ready,
output rsp_valid,
output rsp_data,
output rsp_tag,
input rsp_ready
);
endinterface

38
hw/rtl/interfaces/VX_mem_req_if.sv
View file

@ -1,38 +0,0 @@
`include "VX_define.vh"
interface VX_mem_req_if #(
parameter DATA_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8,
parameter ADDR_WIDTH = `XLEN - `CLOG2(DATA_SIZE),
parameter TAG_WIDTH = 1
) ();
wire valid;
wire rw;
wire [DATA_SIZE-1:0] byteen;
wire [ADDR_WIDTH-1:0] addr;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output rw,
output byteen,
output addr,
output data,
output tag,
input ready
);
modport slave (
input valid,
input rw,
input byteen,
input addr,
input data,
input tag,
output ready
);
endinterface

27
hw/rtl/interfaces/VX_mem_rsp_if.sv
View file

@ -1,27 +0,0 @@
`include "VX_define.vh"
interface VX_mem_rsp_if #(
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface

25
hw/rtl/raster/VX_raster_mem.sv
View file

@ -20,8 +20,7 @@ module VX_raster_mem #(
raster_dcrs_t dcrs,
// Memory interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// Inputs
input wire start,
@ -296,19 +295,19 @@ module VX_raster_mem #(
.rsp_ready (mem_rsp_ready),
// Memory request
.mem_req_valid (cache_req_if.valid),
.mem_req_rw (cache_req_if.rw),
.mem_req_byteen (cache_req_if.byteen),
.mem_req_addr (cache_req_if.addr),
.mem_req_data (cache_req_if.data),
.mem_req_tag (cache_req_if.tag),
.mem_req_ready (cache_req_if.ready),
.mem_req_valid (cache_bus_if.req_valid),
.mem_req_rw (cache_bus_if.req_rw),
.mem_req_byteen (cache_bus_if.req_byteen),
.mem_req_addr (cache_bus_if.req_addr),
.mem_req_data (cache_bus_if.req_data),
.mem_req_tag (cache_bus_if.req_tag),
.mem_req_ready (cache_bus_if.req_ready),
// Memory response
.mem_rsp_valid (cache_rsp_if.valid),
.mem_rsp_data (cache_rsp_if.data),
.mem_rsp_tag (cache_rsp_if.tag),
.mem_rsp_ready (cache_rsp_if.ready)
.mem_rsp_valid (cache_bus_if.rsp_valid),
.mem_rsp_data (cache_bus_if.rsp_data),
.mem_rsp_tag (cache_bus_if.rsp_tag),
.mem_rsp_ready (cache_bus_if.rsp_ready)
);
wire [`RASTER_DATA_BITS-1:0] prim_mem_offset;

61
hw/rtl/raster/VX_raster_unit.sv
View file

@ -23,8 +23,7 @@ module VX_raster_unit #(
`endif
// Memory interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
@ -91,8 +90,7 @@ module VX_raster_unit #(
.dcrs (raster_dcrs),
.cache_req_if (cache_req_if),
.cache_rsp_if (cache_rsp_if),
.cache_bus_if (cache_bus_if),
.valid_out (mem_unit_valid),
.xloc_out (mem_xloc),
@ -287,8 +285,8 @@ module VX_raster_unit #(
`ifdef DBG_SCOPE_RASTER
if (INSTANCE_ID == "cluster0-raster0") begin
`ifdef SCOPE
wire cache_req_fire = cache_req_if.valid && cache_req_if.ready;
wire cache_rsp_fire = cache_rsp_if.valid && cache_rsp_if.ready;
wire cache_req_fire = cache_bus_if.req_valid && cache_bus_if.req_ready;
wire cache_rsp_fire = cache_bus_if.rsp_valid && cache_bus_if.rsp_ready;
wire raster_req_fire = raster_req_if.valid && raster_req_if.ready;
VX_scope_tap #(
.SCOPE_ID (4),
@ -311,11 +309,11 @@ module VX_raster_unit #(
raster_req_if.done
}),
.probes({
cache_rsp_if.data,
cache_rsp_if.tag,
cache_req_if.tag,
cache_req_if.addr,
cache_req_if.rw,
cache_bus_if.rsp_data,
cache_bus_if.rsp_tag,
cache_bus_if.req_tag,
cache_bus_if.req_addr,
cache_bus_if.req_rw,
no_pending_tiledata
}),
.bus_in(scope_bus_in),
@ -325,7 +323,7 @@ module VX_raster_unit #(
`ifdef CHIPSCOPE
ila_raster ila_raster_inst (
.clk (clk),
.probe0 ({cache_rsp_if.data, cache_rsp_if.tag, cache_rsp_if.ready, cache_rsp_if.valid, cache_req_if.tag, cache_req_if.addr, cache_req_if.rw, cache_req_if.valid, cache_req_if.ready}),
.probe0 ({cache_bus_if.rsp_data, cache_bus_if.rsp_tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid, cache_bus_if.req_tag, cache_bus_if.req_addr, cache_bus_if.req_rw, cache_bus_if.req_valid, cache_bus_if.req_ready}),
.probe1 ({no_pending_tiledata, mem_unit_busy, mem_unit_ready, mem_unit_start, mem_unit_valid, raster_req_if.done, raster_req_if.valid, raster_req_if.ready})
);
`endif
@ -337,8 +335,8 @@ module VX_raster_unit #(
wire [$clog2(RCACHE_NUM_REQS+1)-1:0] perf_mem_rsp_per_cycle;
wire [$clog2(RCACHE_NUM_REQS+1)+1-1:0] perf_pending_reads_cycle;
wire [RCACHE_NUM_REQS-1:0] perf_mem_req_fire = cache_req_if.valid & cache_req_if.ready;
wire [RCACHE_NUM_REQS-1:0] perf_mem_rsp_fire = cache_rsp_if.valid & cache_rsp_if.ready;
wire [RCACHE_NUM_REQS-1:0] perf_mem_req_fire = cache_bus_if.req_valid & cache_bus_if.req_ready;
wire [RCACHE_NUM_REQS-1:0] perf_mem_rsp_fire = cache_bus_if.rsp_valid & cache_bus_if.rsp_ready;
`POP_COUNT(perf_mem_req_per_cycle, perf_mem_req_fire);
`POP_COUNT(perf_mem_rsp_per_cycle, perf_mem_rsp_fire);
@ -451,30 +449,24 @@ module VX_raster_unit_top #(
assign raster_req_if.done = raster_req_done;
assign raster_req_if.ready = raster_req_ready;
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (RCACHE_NUM_REQS),
.WORD_SIZE (RCACHE_WORD_SIZE),
.TAG_WIDTH (RCACHE_TAG_WIDTH)
) cache_req_if();
) cache_bus_if();
VX_cache_rsp_if #(
.NUM_REQS (RCACHE_NUM_REQS),
.WORD_SIZE (RCACHE_WORD_SIZE),
.TAG_WIDTH (RCACHE_TAG_WIDTH)
) cache_rsp_if();
assign cache_req_valid = cache_bus_if.req_valid;
assign cache_req_rw = cache_bus_if.req_rw;
assign cache_req_byteen = cache_bus_if.req_byteen;
assign cache_req_addr = cache_bus_if.req_addr;
assign cache_req_data = cache_bus_if.req_data;
assign cache_req_tag = cache_bus_if.req_tag;
assign cache_bus_if.req_ready = cache_req_ready;
assign cache_req_valid = cache_req_if.valid;
assign cache_req_rw = cache_req_if.rw;
assign cache_req_byteen = cache_req_if.byteen;
assign cache_req_addr = cache_req_if.addr;
assign cache_req_data = cache_req_if.data;
assign cache_req_tag = cache_req_if.tag;
assign cache_req_if.ready = cache_req_ready;
assign cache_rsp_if.valid = cache_rsp_valid;
assign cache_rsp_if.tag = cache_rsp_tag;
assign cache_rsp_if.data = cache_rsp_data;
assign cache_rsp_ready = cache_rsp_if.ready;
assign cache_bus_if.rsp_valid = cache_rsp_valid;
assign cache_bus_if.rsp_tag = cache_rsp_tag;
assign cache_bus_if.rsp_data = cache_rsp_data;
assign cache_rsp_ready = cache_bus_if.rsp_ready;
`ifdef SCOPE
wire [0:0] scope_reset_w = 1'b0;
@ -502,8 +494,7 @@ module VX_raster_unit_top #(
`endif
.dcr_write_if (dcr_write_if),
.raster_req_if (raster_req_if),
.cache_req_if (cache_req_if),
.cache_rsp_if (cache_rsp_if)
.cache_bus_if (cache_bus_if)
);
endmodule

25
hw/rtl/rop/VX_rop_mem.sv
View file

@ -13,8 +13,7 @@ module VX_rop_mem #(
input rop_dcrs_t dcrs,
// Memory interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// Request interface
input wire req_valid,
@ -213,18 +212,18 @@ module VX_rop_mem #(
`UNUSED_PIN (rsp_eop),
.rsp_ready (mrsp_ready),
.mem_req_valid (cache_req_if.valid),
.mem_req_rw (cache_req_if.rw),
.mem_req_byteen (cache_req_if.byteen),
.mem_req_addr (cache_req_if.addr),
.mem_req_data (cache_req_if.data),
.mem_req_tag (cache_req_if.tag),
.mem_req_ready (cache_req_if.ready),
.mem_req_valid (cache_bus_if.req_valid),
.mem_req_rw (cache_bus_if.req_rw),
.mem_req_byteen (cache_bus_if.req_byteen),
.mem_req_addr (cache_bus_if.req_addr),
.mem_req_data (cache_bus_if.req_data),
.mem_req_tag (cache_bus_if.req_tag),
.mem_req_ready (cache_bus_if.req_ready),
.mem_rsp_valid (cache_rsp_if.valid),
.mem_rsp_data (cache_rsp_if.data),
.mem_rsp_tag (cache_rsp_if.tag),
.mem_rsp_ready (cache_rsp_if.ready)
.mem_rsp_valid (cache_bus_if.rsp_valid),
.mem_rsp_data (cache_bus_if.rsp_data),
.mem_rsp_tag (cache_bus_if.rsp_tag),
.mem_rsp_ready (cache_bus_if.rsp_ready)
);
assign rsp_valid = mrsp_valid;

47
hw/rtl/rop/VX_rop_unit.sv
View file

@ -13,8 +13,7 @@ module VX_rop_unit #(
`endif
// Memory interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
@ -74,8 +73,7 @@ module VX_rop_unit #(
.dcrs (rop_dcrs),
.cache_req_if (cache_req_if),
.cache_rsp_if (cache_rsp_if),
.cache_bus_if (cache_bus_if),
.req_valid (mem_req_valid_r),
.req_ds_mask (mem_req_ds_mask_r),
@ -329,9 +327,9 @@ module VX_rop_unit #(
wire [$clog2(OCACHE_NUM_REQS+1)-1:0] perf_mem_rd_rsp_per_cycle;
wire [$clog2(OCACHE_NUM_REQS+1)+1-1:0] perf_pending_reads_cycle;
wire [OCACHE_NUM_REQS-1:0] perf_mem_rd_req_fire = cache_req_if.valid & ~cache_req_if.rw & cache_req_if.ready;
wire [OCACHE_NUM_REQS-1:0] perf_mem_wr_req_fire = cache_req_if.valid & cache_req_if.rw & cache_req_if.ready;
wire [OCACHE_NUM_REQS-1:0] perf_mem_rd_rsp_fire = cache_rsp_if.valid & cache_rsp_if.ready;
wire [OCACHE_NUM_REQS-1:0] perf_mem_rd_req_fire = cache_bus_if.req_valid & ~cache_bus_if.req_rw & cache_bus_if.req_ready;
wire [OCACHE_NUM_REQS-1:0] perf_mem_wr_req_fire = cache_bus_if.req_valid & cache_bus_if.req_rw & cache_bus_if.req_ready;
wire [OCACHE_NUM_REQS-1:0] perf_mem_rd_rsp_fire = cache_bus_if.rsp_valid & cache_bus_if.rsp_ready;
`POP_COUNT(perf_mem_rd_req_per_cycle, perf_mem_rd_req_fire);
`POP_COUNT(perf_mem_wr_req_per_cycle, perf_mem_wr_req_fire);
@ -437,30 +435,24 @@ module VX_rop_unit_top #(
assign rop_req_if.face = rop_req_face;
assign rop_req_ready = rop_req_if.ready;
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (OCACHE_NUM_REQS),
.WORD_SIZE (OCACHE_WORD_SIZE),
.TAG_WIDTH (OCACHE_TAG_WIDTH)
) cache_req_if();
) cache_bus_if();
VX_cache_rsp_if #(
.NUM_REQS (OCACHE_NUM_REQS),
.WORD_SIZE (OCACHE_WORD_SIZE),
.TAG_WIDTH (OCACHE_TAG_WIDTH)
) cache_rsp_if();
assign cache_req_valid = cache_bus_if.req_valid;
assign cache_req_rw = cache_bus_if.req_rw;
assign cache_req_byteen = cache_bus_if.req_byteen;
assign cache_req_addr = cache_bus_if.req_addr;
assign cache_req_data = cache_bus_if.req_data;
assign cache_req_tag = cache_bus_if.req_tag;
assign cache_bus_if.req_ready = cache_req_ready;
assign cache_req_valid = cache_req_if.valid;
assign cache_req_rw = cache_req_if.rw;
assign cache_req_byteen = cache_req_if.byteen;
assign cache_req_addr = cache_req_if.addr;
assign cache_req_data = cache_req_if.data;
assign cache_req_tag = cache_req_if.tag;
assign cache_req_if.ready = cache_req_ready;
assign cache_rsp_if.valid = cache_rsp_valid;
assign cache_rsp_if.tag = cache_rsp_tag;
assign cache_rsp_if.data = cache_rsp_data;
assign cache_rsp_ready = cache_rsp_if.ready;
assign cache_bus_if.rsp_valid = cache_rsp_valid;
assign cache_bus_if.rsp_tag = cache_rsp_tag;
assign cache_bus_if.rsp_data = cache_rsp_data;
assign cache_rsp_ready = cache_bus_if.rsp_ready;
VX_rop_unit #(
.INSTANCE_ID (INSTANCE_ID),
@ -473,8 +465,7 @@ module VX_rop_unit_top #(
`endif
.dcr_write_if (dcr_write_if),
.rop_req_if (rop_req_if),
.cache_req_if (cache_req_if),
.cache_rsp_if (cache_rsp_if)
.cache_bus_if (cache_bus_if)
);
endmodule

25
hw/rtl/tex/VX_tex_mem.sv
View file

@ -9,8 +9,7 @@ module VX_tex_mem #(
input wire reset,
// memory interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// inputs
input wire req_valid,
@ -130,19 +129,19 @@ module VX_tex_mem #(
.rsp_ready (mem_rsp_ready),
// Memory request
.mem_req_valid (cache_req_if.valid),
.mem_req_rw (cache_req_if.rw),
.mem_req_byteen (cache_req_if.byteen),
.mem_req_addr (cache_req_if.addr),
.mem_req_data (cache_req_if.data),
.mem_req_tag (cache_req_if.tag),
.mem_req_ready (cache_req_if.ready),
.mem_req_valid (cache_bus_if.req_valid),
.mem_req_rw (cache_bus_if.req_rw),
.mem_req_byteen (cache_bus_if.req_byteen),
.mem_req_addr (cache_bus_if.req_addr),
.mem_req_data (cache_bus_if.req_data),
.mem_req_tag (cache_bus_if.req_tag),
.mem_req_ready (cache_bus_if.req_ready),
// Memory response
.mem_rsp_valid (cache_rsp_if.valid),
.mem_rsp_data (cache_rsp_if.data),
.mem_rsp_tag (cache_rsp_if.tag),
.mem_rsp_ready (cache_rsp_if.ready)
.mem_rsp_valid (cache_bus_if.rsp_valid),
.mem_rsp_data (cache_bus_if.rsp_data),
.mem_rsp_tag (cache_bus_if.rsp_tag),
.mem_rsp_ready (cache_bus_if.rsp_ready)
);
// handle memory response

45
hw/rtl/tex/VX_tex_unit.sv
View file

@ -14,8 +14,7 @@ module VX_tex_unit #(
`endif
// Memory interface
VX_cache_req_if.master cache_req_if,
VX_cache_rsp_if.slave cache_rsp_if,
VX_cache_bus_if.master cache_bus_if,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
@ -143,8 +142,7 @@ module VX_tex_unit #(
.reset (mem_reset),
// memory interface
.cache_req_if (cache_req_if),
.cache_rsp_if (cache_rsp_if),
.cache_bus_if (cache_bus_if),
// inputs
.req_valid (mem_req_valid),
@ -214,8 +212,8 @@ module VX_tex_unit #(
wire [$clog2(TCACHE_NUM_REQS+1)-1:0] perf_mem_rsp_per_cycle;
wire [$clog2(TCACHE_NUM_REQS+1)+1-1:0] perf_pending_reads_cycle;
wire [TCACHE_NUM_REQS-1:0] perf_mem_req_fire = cache_req_if.valid & cache_req_if.ready;
wire [TCACHE_NUM_REQS-1:0] perf_mem_rsp_fire = cache_rsp_if.valid & cache_rsp_if.ready;
wire [TCACHE_NUM_REQS-1:0] perf_mem_req_fire = cache_bus_if.req_valid & cache_bus_if.req_ready;
wire [TCACHE_NUM_REQS-1:0] perf_mem_rsp_fire = cache_bus_if.rsp_valid & cache_bus_if.rsp_ready;
`POP_COUNT(perf_mem_req_per_cycle, perf_mem_req_fire);
`POP_COUNT(perf_mem_rsp_per_cycle, perf_mem_rsp_fire);
@ -346,30 +344,24 @@ module VX_tex_unit_top #(
assign tex_rsp_tag = tex_rsp_if.tag;
assign tex_rsp_if.ready = tex_rsp_ready;
VX_cache_req_if #(
VX_cache_bus_if #(
.NUM_REQS (TCACHE_NUM_REQS),
.WORD_SIZE (TCACHE_WORD_SIZE),
.TAG_WIDTH (TCACHE_TAG_WIDTH)
) cache_req_if();
) cache_bus_if();
VX_cache_rsp_if #(
.NUM_REQS (TCACHE_NUM_REQS),
.WORD_SIZE (TCACHE_WORD_SIZE),
.TAG_WIDTH (TCACHE_TAG_WIDTH)
) cache_rsp_if();
assign cache_req_valid = cache_bus_if.req_valid;
assign cache_req_rw = cache_bus_if.req_rw;
assign cache_req_byteen = cache_bus_if.req_byteen;
assign cache_req_addr = cache_bus_if.req_addr;
assign cache_req_data = cache_bus_if.req_data;
assign cache_req_tag = cache_bus_if.req_tag;
assign cache_bus_if.req_ready = cache_req_ready;
assign cache_req_valid = cache_req_if.valid;
assign cache_req_rw = cache_req_if.rw;
assign cache_req_byteen = cache_req_if.byteen;
assign cache_req_addr = cache_req_if.addr;
assign cache_req_data = cache_req_if.data;
assign cache_req_tag = cache_req_if.tag;
assign cache_req_if.ready = cache_req_ready;
assign cache_rsp_if.valid = cache_rsp_valid;
assign cache_rsp_if.tag = cache_rsp_tag;
assign cache_rsp_if.data = cache_rsp_data;
assign cache_rsp_ready = cache_rsp_if.ready;
assign cache_bus_if.rsp_valid = cache_rsp_valid;
assign cache_bus_if.rsp_tag = cache_rsp_tag;
assign cache_bus_if.rsp_data = cache_rsp_data;
assign cache_rsp_ready = cache_bus_if.rsp_ready;
VX_tex_unit #(
.INSTANCE_ID (INSTANCE_ID),
@ -384,8 +376,7 @@ module VX_tex_unit_top #(
.dcr_write_if (dcr_write_if),
.tex_req_if (tex_req_if),
.tex_rsp_if (tex_rsp_if),
.cache_req_if (cache_req_if),
.cache_rsp_if (cache_rsp_if)
.cache_bus_if (cache_bus_if)
);
endmodule