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removed fill_invalidator (not needed anymore)

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This commit is contained in:
Blaise Tine 2020-05-23 19:24:52 -04:00
parent f3b21aab8f
commit 6882d88a62
11 changed files with 150382 additions and 7096 deletions
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2
driver/rtlsim/Makefile
View file

@ -12,7 +12,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-DDBG_PRINT_DRAM \
-DDBG_PRINT_OPAE
#DBG_PRINT=$(DBG_PRINT_FLAGS)
DBG_PRINT=$(DBG_PRINT_FLAGS)
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4

6
driver/tests/basic/Makefile
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@ -42,9 +42,6 @@ kernel.elf: $(SRCS)
$(PROJECT): $(SRCS)
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@
# $(PROJECT): $(SRCS)
# $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -L../../rtlsim -lvortex -o $@
run-fpga: $(PROJECT)
LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
@ -54,9 +51,6 @@ run-ase: $(PROJECT)
run-rtlsim: $(PROJECT)
LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT)
# run-rtlsim: $(PROJECT)
# DYLD_LIBRARY_PATH=../../rtlsim:$(DYLD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 4
run-simx: $(PROJECT)
LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

2
driver/tests/demo/Makefile
View file

@ -46,7 +46,7 @@ run-ase: $(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
run-rtlsim: $(PROJECT)
LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 4
LD_LIBRARY_PATH=../../rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
run-simx: $(PROJECT)
LD_LIBRARY_PATH=../../simx:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16

157335
driver/tests/demo/run.log
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File diff suppressed because it is too large Load diff

25
hw/rtl/VX_config.vh
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@ -144,11 +144,6 @@
`define DPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef DFILL_INVALIDAOR_SIZE
`define DFILL_INVALIDAOR_SIZE 32
`endif
// ========================== Icache Configurable Knobs =======================
// Size of cache in bytes
@ -215,11 +210,6 @@
`define IPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef IFILL_INVALIDAOR_SIZE
`define IFILL_INVALIDAOR_SIZE 32
`endif
// =========================== SM Configurable Knobs ==========================
// Size of cache in bytes
@ -286,11 +276,6 @@
`define SPRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef SFILL_INVALIDAOR_SIZE
`define SFILL_INVALIDAOR_SIZE 32
`endif
// ======================== L2cache Configurable Knobs ========================
// Size of cache in bytes
@ -362,11 +347,6 @@
`define L2PRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef L2FILL_INVALIDAOR_SIZE
`define L2FILL_INVALIDAOR_SIZE 32
`endif
// ======================== L3cache Configurable Knobs ========================
// Size of cache in bytes
@ -436,11 +416,6 @@
`ifndef L3PRFQ_STRIDE
`define L3PRFQ_STRIDE 0
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef L3FILL_INVALIDAOR_SIZE
`define L3FILL_INVALIDAOR_SIZE 32
`endif
// VX_CONFIG

3
hw/rtl/VX_dmem_ctrl.v
View file

@ -68,7 +68,6 @@ module VX_dmem_ctrl # (
.DFQQ_SIZE (`SDFQQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (0),
.WRITE_ENABLE (1),
@ -148,7 +147,6 @@ module VX_dmem_ctrl # (
.DFQQ_SIZE (`DDFQQ_SIZE),
.PRFQ_SIZE (`DPRFQ_SIZE),
.PRFQ_STRIDE (`DPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (1),
.WRITE_ENABLE (1),
@ -229,7 +227,6 @@ module VX_dmem_ctrl # (
.DFQQ_SIZE (`IDFQQ_SIZE),
.PRFQ_SIZE (`IPRFQ_SIZE),
.PRFQ_STRIDE (`IPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (1),
.WRITE_ENABLE (0),

3
hw/rtl/Vortex_Cluster.v
View file

@ -251,8 +251,7 @@ module Vortex_Cluster #(
.DWBQ_SIZE (`L2DWBQ_SIZE),
.DFQQ_SIZE (`L2DFQQ_SIZE),
.PRFQ_SIZE (`L2PRFQ_SIZE),
.PRFQ_STRIDE (`L2PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
.PRFQ_STRIDE (`L2PRFQ_STRIDE),
.DRAM_ENABLE (1),
.WRITE_ENABLE (1),
.SNOOP_FORWARDING (1),

1
hw/rtl/Vortex_Socket.v
View file

@ -260,7 +260,6 @@ module Vortex_Socket (
.DFQQ_SIZE (`L3DFQQ_SIZE),
.PRFQ_SIZE (`L3PRFQ_SIZE),
.PRFQ_STRIDE (`L3PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
.DRAM_ENABLE (1),
.WRITE_ENABLE (1),
.SNOOP_FORWARDING (1),

22
hw/rtl/cache/VX_bank.v vendored
View file

@ -34,9 +34,6 @@ module VX_bank #(
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 0,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 0,
// Enable cache writeable
parameter WRITE_ENABLE = 0,
@ -589,26 +586,9 @@ module VX_bank #(
// Enqueue DRAM fill request
wire invalidate_fill;
wire possible_fill = valid_st2 && miss_st2 && dram_fill_req_ready && ~is_snp_st2;
wire [`LINE_ADDR_WIDTH-1:0] fill_invalidator_addr = addr_st2;
VX_fill_invalidator #(
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
) fill_invalidator (
.clk (clk),
.reset (reset),
.possible_fill (possible_fill),
.success_fill (is_fill_st2),
.fill_addr (fill_invalidator_addr),
.invalidate_fill (invalidate_fill)
);
assign dram_fill_req_valid = miss_add && !mrvq_init_ready_state_st2;
assign dram_fill_req_addr = addr_st2;
assign dram_fill_req_stall = (valid_st2 && miss_st2 && !invalidate_fill && ~dram_fill_req_ready);
assign dram_fill_req_stall = (valid_st2 && miss_st2 && ~dram_fill_req_ready);
// Enqueue DRAM writeback request

4
hw/rtl/cache/VX_cache.v vendored
View file

@ -34,9 +34,6 @@ module VX_cache #(
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 0,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
@ -333,7 +330,6 @@ module VX_cache #(
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE),
.SNOOP_FORWARDING (SNOOP_FORWARDING),

75
hw/rtl/cache/VX_fill_invalidator.v vendored
View file

@ -1,75 +0,0 @@
`include "VX_cache_config.vh"
module VX_fill_invalidator #(
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 0,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 0,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 0
) (
input wire clk,
input wire reset,
input wire possible_fill,
input wire success_fill,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr,
output reg invalidate_fill
);
if (FILL_INVALIDAOR_SIZE == 0) begin
assign invalidate_fill = 0;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (possible_fill)
`UNUSED_VAR (success_fill)
`UNUSED_VAR (fill_addr)
end else begin
reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;
reg [FILL_INVALIDAOR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] fills_address;
reg [FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer i;
always @(*) begin
for (i = 0; i < FILL_INVALIDAOR_SIZE; i+=1) begin
matched_fill[i] = fills_active[i]
&& ((fills_address[i] == fill_addr) === 1); // use "case equality" to handle uninitialized entry
end
end
assign matched = (|(matched_fill));
wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
wire enqueue_found;
VX_generic_priority_encoder #(
.N(FILL_INVALIDAOR_SIZE)
) sel_bank (
.valids(~fills_active),
.index (enqueue_index),
.found (enqueue_found)
);
assign invalidate_fill = possible_fill && matched;
always @(posedge clk) begin
if (reset) begin
fills_active <= 0;
end else begin
if (possible_fill && !matched && enqueue_found) begin
fills_active [enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
end else if (success_fill && matched) begin
fills_active <= fills_active & (~matched_fill);
end
end
end
end
endmodule