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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
SimX writeback configuration
This commit is contained in:
Blaise Tine
parent
904a6dc136
commit
69126dfd35
5 changed files with 34 additions and 34 deletions
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@ -436,7 +436,7 @@ public:
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auto port_id = req_id % config_.ports_per_bank;
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// check MSHR capacity
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if ((!core_req.write || !config_.write_through)
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if ((!core_req.write || config_.write_back)
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&& bank.mshr.full()) {
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++perf_stats_.mshr_stalls;
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continue;
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@ -572,7 +572,7 @@ private:
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if (pipeline_req.write) {
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// handle write has_hit
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auto& hit_line = set.lines.at(hit_line_id);
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if (config_.write_through) {
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if (!config_.write_back) {
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// forward write request to memory
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, pipeline_req.set_id, pipeline_req.tag);
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@ -603,7 +603,7 @@ private:
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else
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++perf_stats_.read_misses;
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if (free_line_id == -1 && !config_.write_through) {
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if (free_line_id == -1 && config_.write_back) {
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// write back dirty line
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auto& repl_line = set.lines.at(repl_line_id);
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if (repl_line.dirty) {
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@ -617,7 +617,7 @@ private:
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}
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}
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if (pipeline_req.write && config_.write_through) {
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if (pipeline_req.write && !config_.write_back) {
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// forward write request to memory
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{
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MemReq mem_req;
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -30,12 +30,12 @@ public:
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uint8_t addr_width; // word address bits
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uint8_t ports_per_bank; // number of ports per bank
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uint8_t num_inputs; // number of inputs
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bool write_through; // is write-through
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bool write_back; // is write-back
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bool write_reponse; // enable write response
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uint16_t mshr_size; // MSHR buffer size
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uint8_t latency; // pipeline latency
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};
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struct PerfStats {
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uint64_t reads;
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uint64_t writes;
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@ -47,7 +47,7 @@ public:
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uint64_t mshr_stalls;
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uint64_t mem_latency;
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PerfStats()
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PerfStats()
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: reads(0)
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, writes(0)
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, read_misses(0)
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@ -82,11 +82,11 @@ public:
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~CacheSim();
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void reset();
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void tick();
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const PerfStats& perf_stats() const;
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private:
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class Impl;
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Impl* impl_;
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -15,11 +15,11 @@
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using namespace vortex;
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Cluster::Cluster(const SimContext& ctx,
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Cluster::Cluster(const SimContext& ctx,
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uint32_t cluster_id,
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ProcessorImpl* processor,
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const Arch &arch,
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const DCRS &dcrs)
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ProcessorImpl* processor,
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const Arch &arch,
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const DCRS &dcrs)
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: SimObject(ctx, "cluster")
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, mem_req_port(this)
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, mem_rsp_port(this)
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@ -43,9 +43,9 @@ Cluster::Cluster(const SimContext& ctx,
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for (uint32_t i = 0; i < sockets_per_cluster; ++i) {
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uint32_t socket_id = cluster_id * sockets_per_cluster + i;
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auto socket = Socket::Create(socket_id,
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this,
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arch,
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auto socket = Socket::Create(socket_id,
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this,
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arch,
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dcrs);
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socket->icache_mem_req_port.bind(&icache_switch->ReqIn.at(i));
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@ -58,7 +58,7 @@ Cluster::Cluster(const SimContext& ctx,
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}
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// Create l2cache
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snprintf(sname, 100, "cluster%d-l2cache", cluster_id);
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l2cache_ = CacheSim::Create(sname, CacheSim::Config{
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!L2_ENABLED,
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@ -67,10 +67,10 @@ Cluster::Cluster(const SimContext& ctx,
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log2ceil(L1_LINE_SIZE), // W
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log2ceil(L2_NUM_WAYS), // A
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log2ceil(L2_NUM_BANKS), // B
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XLEN, // address bits
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XLEN, // address bits
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1, // number of ports
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2, // request size
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true, // write-through
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2, // request size
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L2_WRITEBACK, // write-back
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false, // write response
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L2_MSHR_SIZE, // mshr size
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2, // pipeline latency
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@ -90,7 +90,7 @@ Cluster::~Cluster() {
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//--
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}
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void Cluster::reset() {
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void Cluster::reset() {
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for (auto& barrier : barriers_) {
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barrier.reset();
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}
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@ -39,7 +39,7 @@ ProcessorImpl::ProcessorImpl(const Arch& arch)
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XLEN, // address bits
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1, // number of ports
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uint8_t(arch.num_clusters()), // request size
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true, // write-through
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L3_WRITEBACK, // write-back
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false, // write response
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L3_MSHR_SIZE, // mshr size
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2, // pipeline latency
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -16,11 +16,11 @@
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using namespace vortex;
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Socket::Socket(const SimContext& ctx,
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Socket::Socket(const SimContext& ctx,
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uint32_t socket_id,
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Cluster* cluster,
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const Arch &arch,
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const DCRS &dcrs)
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Cluster* cluster,
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const Arch &arch,
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const DCRS &dcrs)
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: SimObject(ctx, "socket")
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, icache_mem_req_port(this)
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, icache_mem_rsp_port(this)
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@ -44,7 +44,7 @@ Socket::Socket(const SimContext& ctx,
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XLEN, // address bits
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1, // number of ports
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1, // number of inputs
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false, // write-through
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false, // write-back
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false, // write response
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(uint8_t)arch.num_warps(), // mshr size
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2, // pipeline latency
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@ -64,7 +64,7 @@ Socket::Socket(const SimContext& ctx,
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XLEN, // address bits
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1, // number of ports
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DCACHE_NUM_REQS, // number of inputs
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true, // write-through
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DCACHE_WRITEBACK, // write-back
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false, // write response
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DCACHE_MSHR_SIZE, // mshr size
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2, // pipeline latency
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