mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
build fixes and cleanup
This commit is contained in:
Blaise Tine
parent
72e06ef4fe
commit
6a9a279a32
27 changed files with 5 additions and 1562 deletions
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@ -1,12 +0,0 @@
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main.o: main.cc gaussianElim.h clutils.h \
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/opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h \
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/opt/pocl/runtime/include/CL/opencl.h \
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/opt/pocl/runtime/include/CL/cl_gl.h \
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/opt/pocl/runtime/include/CL/cl_gl_ext.h \
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/opt/pocl/runtime/include/CL/cl_ext.h
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clutils.o: clutils.cpp /opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h clutils.h utils.h
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utils.o: utils.cpp utils.h
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main.o: main.cc nearestNeighbor.h /opt/pocl/runtime/include/CL/opencl.h \
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/opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h \
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/opt/pocl/runtime/include/CL/cl_gl.h \
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/opt/pocl/runtime/include/CL/cl_gl_ext.h \
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/opt/pocl/runtime/include/CL/cl_ext.h clutils.h
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clutils.o: clutils.cpp /opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h clutils.h utils.h
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utils.o: utils.cpp utils.h
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@ -1,3 +0,0 @@
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main.o: main.cc /opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h
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main.o: main.cc /opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h
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main.o: main.cc /opt/pocl/runtime/include/CL/opencl.h \
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/opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h \
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/opt/pocl/runtime/include/CL/cl_gl.h \
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/opt/pocl/runtime/include/CL/cl_gl_ext.h \
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/opt/pocl/runtime/include/CL/cl_ext.h
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main.o: main.cc /opt/pocl/runtime/include/CL/opencl.h \
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/opt/pocl/runtime/include/CL/cl.h \
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/opt/pocl/runtime/include/CL/cl_version.h \
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/opt/pocl/runtime/include/CL/cl_platform.h \
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/opt/pocl/runtime/include/CL/cl_gl.h \
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/opt/pocl/runtime/include/CL/cl_gl_ext.h \
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/opt/pocl/runtime/include/CL/cl_ext.h
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@ -1,4 +0,0 @@
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vortex.o: vortex.cpp ../include/vortex.h ../../hw/VX_config.h \
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vortex_afu.h
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vx_utils.o: ../common/vx_utils.cpp ../include/vortex.h \
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../../hw/VX_config.h
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@ -44,7 +44,8 @@ SRCS = fpga.cpp opae_sim.cpp
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SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
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FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE)
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RTL_INCLUDE += -I$(RTL_DIR)/afu -I$(RTL_DIR)/afu/ccip
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VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
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@ -41,7 +41,8 @@ SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
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SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
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FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(DPI_DIR) -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
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RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE)
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VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS)
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VL_FLAGS += -Wno-DECLFILENAME
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demo.o: demo.cpp ../../include/vortex.h common.h
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437
hw/VX_config.h
437
hw/VX_config.h
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@ -1,437 +0,0 @@
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2021-03-13 13:57:30.622905
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#ifndef VX_USER_CONFIG
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#define VX_USER_CONFIG
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#endif
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2021-03-13 13:57:30.624676
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// Translated from VX_config.vh:
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#ifndef VX_CONFIG
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#define VX_CONFIG
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#ifndef NUM_CLUSTERS
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#define NUM_CLUSTERS 1
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#endif
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#ifndef NUM_CORES
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#define NUM_CORES 1
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#endif
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#ifndef NUM_WARPS
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#define NUM_WARPS 4
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#endif
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#ifndef NUM_THREADS
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#define NUM_THREADS 4
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#endif
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#ifndef NUM_BARRIERS
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#define NUM_BARRIERS 4
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#endif
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#ifndef L2_ENABLE
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#define L2_ENABLE 0
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#endif
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#ifndef L3_ENABLE
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#define L3_ENABLE 0
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#endif
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#ifndef SM_ENABLE
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#define SM_ENABLE 1
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#endif
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#ifndef GLOBAL_BLOCK_SIZE
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#define GLOBAL_BLOCK_SIZE 64
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#endif
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#ifndef L1_BLOCK_SIZE
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#define L1_BLOCK_SIZE (NUM_THREADS * 4)
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#endif
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#ifndef STARTUP_ADDR
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#define STARTUP_ADDR 0x80000000
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#endif
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#ifndef IO_BUS_BASE_ADDR
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#define IO_BUS_BASE_ADDR 0xFF000000
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#endif
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#ifndef SHARED_MEM_BASE_ADDR
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#define SHARED_MEM_BASE_ADDR IO_BUS_BASE_ADDR
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#endif
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#ifndef SHARED_MEM_BASE_ADDR_ALIGN
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#define SHARED_MEM_BASE_ADDR_ALIGN 64
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#endif
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#ifndef IO_BUS_ADDR_COUT
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#define IO_BUS_ADDR_COUT 0xFFFFFFFC
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#endif
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#ifndef FRAME_BUFFER_BASE_ADDR
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#define FRAME_BUFFER_BASE_ADDR 0xFF000000
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#endif
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#ifndef FRAME_BUFFER_WIDTH
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#define FRAME_BUFFER_WIDTH 1920
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#endif
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#ifndef FRAME_BUFFER_HEIGHT
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#define FRAME_BUFFER_HEIGHT 1080
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#endif
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#define FRAME_BUFFER_SIZE (FRAME_BUFFER_WIDTH * FRAME_BUFFER_HEIGHT)
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#ifndef EXT_M_DISABLE
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#define EXT_M_ENABLE
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#endif
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#ifndef EXT_F_DISABLE
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#define EXT_F_ENABLE
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#endif
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// Device identification
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#define VENDOR_ID 0
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#define ARCHITECTURE_ID 0
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#define IMPLEMENTATION_ID 0
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///////////////////////////////////////////////////////////////////////////////
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#ifndef LATENCY_IMUL
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#define LATENCY_IMUL 3
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#endif
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#ifndef LATENCY_FNCP
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#define LATENCY_FNCP 2
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#endif
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#ifndef LATENCY_FMA
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#define LATENCY_FMA 4
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#endif
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#ifndef LATENCY_FDIV
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#ifdef ALTERA_S10
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#define LATENCY_FDIV 34
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#else
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#define LATENCY_FDIV 15
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#endif
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#endif
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#ifndef LATENCY_FSQRT
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#ifdef ALTERA_S10
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#define LATENCY_FSQRT 25
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#else
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#define LATENCY_FSQRT 10
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#endif
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#endif
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#ifndef LATENCY_FDIVSQRT
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#define LATENCY_FDIVSQRT 32
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#endif
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#ifndef LATENCY_FCVT
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#define LATENCY_FCVT 4
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#endif
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// CSR Addresses //////////////////////////////////////////////////////////////
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// User Floating-Point CSRs
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#define CSR_FFLAGS 0x001
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#define CSR_FRM 0x002
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#define CSR_FCSR 0x003
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#define CSR_SATP 0x180
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#define CSR_PMPCFG0 0x3A0
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#define CSR_PMPADDR0 0x3B0
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MEPC 0x341
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// Machine Counter/Timers
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#define CSR_CYCLE 0xC00
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#define CSR_CYCLE_H 0xC80
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#define CSR_INSTRET 0xC02
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#define CSR_INSTRET_H 0xC82
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// Machine Performance-monitoring counters
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// PERF: pipeline
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#define CSR_MPM_IBUF_ST 0xB03
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#define CSR_MPM_IBUF_ST_H 0xB83
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#define CSR_MPM_SCRB_ST 0xB04
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#define CSR_MPM_SCRB_ST_H 0xB84
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#define CSR_MPM_ALU_ST 0xB05
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#define CSR_MPM_ALU_ST_H 0xB85
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#define CSR_MPM_LSU_ST 0xB06
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#define CSR_MPM_LSU_ST_H 0xB86
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#define CSR_MPM_CSR_ST 0xB07
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#define CSR_MPM_CSR_ST_H 0xB87
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#define CSR_MPM_FPU_ST 0xB08
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#define CSR_MPM_FPU_ST_H 0xB88
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#define CSR_MPM_GPU_ST 0xB09
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#define CSR_MPM_GPU_ST_H 0xB89
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// PERF: icache
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#define CSR_MPM_ICACHE_READS 0xB0A // total reads
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#define CSR_MPM_ICACHE_READS_H 0xB8A
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#define CSR_MPM_ICACHE_MISS_R 0xB0B // total misses
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#define CSR_MPM_ICACHE_MISS_R_H 0xB8B
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#define CSR_MPM_ICACHE_PIPE_ST 0xB0C // pipeline stalls
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#define CSR_MPM_ICACHE_PIPE_ST_H 0xB8C
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#define CSR_MPM_ICACHE_CRSP_ST 0xB0D // core response stalls
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#define CSR_MPM_ICACHE_CRSP_ST_H 0xB8D
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// PERF: dcache
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#define CSR_MPM_DCACHE_READS 0xB0E // total reads
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#define CSR_MPM_DCACHE_READS_H 0xB8E
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#define CSR_MPM_DCACHE_WRITES 0xB0F // total writes
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#define CSR_MPM_DCACHE_WRITES_H 0xB8F
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#define CSR_MPM_DCACHE_MISS_R 0xB10 // read misses
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#define CSR_MPM_DCACHE_MISS_R_H 0xB90
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#define CSR_MPM_DCACHE_MISS_W 0xB11 // write misses
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#define CSR_MPM_DCACHE_MISS_W_H 0xB91
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#define CSR_MPM_DCACHE_BANK_ST 0xB12 // bank conflicts stalls
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#define CSR_MPM_DCACHE_BANK_ST_H 0xB92
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#define CSR_MPM_DCACHE_MSHR_ST 0xB13 // MSHR stalls
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#define CSR_MPM_DCACHE_MSHR_ST_H 0xB93
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#define CSR_MPM_DCACHE_PIPE_ST 0xB14 // pipeline stalls
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#define CSR_MPM_DCACHE_PIPE_ST_H 0xB94
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#define CSR_MPM_DCACHE_CRSP_ST 0xB15 // core response stalls
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#define CSR_MPM_DCACHE_CRSP_ST_H 0xB95
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// PERF: smem
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#define CSR_MPM_SMEM_READS 0xB16 // total reads
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#define CSR_MPM_SMEM_READS_H 0xB96
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#define CSR_MPM_SMEM_WRITES 0xB17 // total writes
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#define CSR_MPM_SMEM_WRITES_H 0xB97
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#define CSR_MPM_SMEM_BANK_ST 0xB18 // bank conflicts stalls
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#define CSR_MPM_SMEM_BANK_ST_H 0xB98
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// PERF: memory
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#define CSR_MPM_DRAM_READS 0xB19 // dram reads
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#define CSR_MPM_DRAM_READS_H 0xB99
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#define CSR_MPM_DRAM_WRITES 0xB1A // dram writes
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#define CSR_MPM_DRAM_WRITES_H 0xB9A
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#define CSR_MPM_DRAM_ST 0xB1B // dram request stalls
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#define CSR_MPM_DRAM_ST_H 0xB9B
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#define CSR_MPM_DRAM_LAT 0xB1C // dram latency (total)
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#define CSR_MPM_DRAM_LAT_H 0xB9C
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// Machine Information Registers
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#define CSR_MVENDORID 0xF11
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#define CSR_MARCHID 0xF12
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#define CSR_MIMPID 0xF13
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#define CSR_MHARTID 0xF14
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// User SIMT CSRs
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#define CSR_WTID 0xCC0
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#define CSR_LTID 0xCC1
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#define CSR_GTID 0xCC2
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#define CSR_LWID 0xCC3
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#define CSR_GWID CSR_MHARTID
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#define CSR_GCID 0xCC5
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// Machine SIMT CSRs
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#define CSR_NT 0xFC0
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#define CSR_NW 0xFC1
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#define CSR_NC 0xFC2
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////////// Texture Unit CSRs /////////////
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#define CSR_TEX_BEGIN 0xFD0
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// Unit 1
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#define CSR_TEX0_ADDR CSR_TEX_BEGIN
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#define CSR_TEX0_FORMAT CSR_TEX_BEGIN + 0x1
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#define CSR_TEX0_WIDTH CSR_TEX_BEGIN + 0x2
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#define CSR_TEX0_HEIGHT CSR_TEX_BEGIN + 0x3
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#define CSR_TEX0_STRIDE CSR_TEX_BEGIN + 0x4
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#define CSR_TEX0_WRAP_U CSR_TEX_BEGIN + 0x5
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#define CSR_TEX0_WRAP_V CSR_TEX_BEGIN + 0x6
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#define CSR_TEX0_MIN_FILTER CSR_TEX_BEGIN + 0x7
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#define CSR_TEX0_MAX_FILTER CSR_TEX_BEGIN + 0x8
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// Unit 2
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#define CSR_TEX1_ADDR CSR_TEX_BEGIN + 0x9
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#define CSR_TEX1_FORMAT CSR_TEX_BEGIN + 0xA
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#define CSR_TEX1_WIDTH CSR_TEX_BEGIN + 0xB
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#define CSR_TEX1_HEIGHT CSR_TEX_BEGIN + 0xC
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#define CSR_TEX1_STRIDE CSR_TEX_BEGIN + 0xD
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#define CSR_TEX1_WRAP_U CSR_TEX_BEGIN + 0xE
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#define CSR_TEX1_WRAP_V CSR_TEX_BEGIN + 0xF
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#define CSR_TEX1_MIN_FILTER CSR_TEX_BEGIN + 0x10
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#define CSR_TEX1_MAX_FILTER CSR_TEX_BEGIN + 0x11
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#define CSR_TEX_END CSR_TEX1_MAX_FILTER
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of LSU Request Queue
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#ifndef LSUQ_SIZE
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#define LSUQ_SIZE 8
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#endif
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// Size of FPU Request Queue
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#ifndef FPUQ_SIZE
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#define FPUQ_SIZE 8
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#endif
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// Icache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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#ifndef ICACHE_SIZE
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#define ICACHE_SIZE 16384
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#endif
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// Core Request Queue Size
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#ifndef ICREQ_SIZE
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#define ICREQ_SIZE 4
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#endif
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// Miss Handling Register Size
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#ifndef IMSHR_SIZE
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#define IMSHR_SIZE NUM_WARPS
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#endif
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// DRAM Request Queue Size
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#ifndef IDREQ_SIZE
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#define IDREQ_SIZE 4
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#endif
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// DRAM Response Queue Size
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#ifndef IDRSQ_SIZE
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#define IDRSQ_SIZE 4
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#endif
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// Dcache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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#ifndef DCACHE_SIZE
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#define DCACHE_SIZE 16384
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#endif
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// Number of banks
|
||||
#ifndef DNUM_BANKS
|
||||
#define DNUM_BANKS NUM_THREADS
|
||||
#endif
|
||||
|
||||
// Number of bank ports
|
||||
#ifndef DNUM_PORTS
|
||||
#define DNUM_PORTS 1
|
||||
#endif
|
||||
|
||||
// Core Request Queue Size
|
||||
#ifndef DCREQ_SIZE
|
||||
#define DCREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// Miss Handling Register Size
|
||||
#ifndef DMSHR_SIZE
|
||||
#define DMSHR_SIZE LSUQ_SIZE
|
||||
#endif
|
||||
|
||||
// DRAM Request Queue Size
|
||||
#ifndef DDREQ_SIZE
|
||||
#define DDREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// DRAM Response Queue Size
|
||||
#ifndef DDRSQ_SIZE
|
||||
#define DDRSQ_SIZE MAX(4, (DNUM_BANKS * 2))
|
||||
#endif
|
||||
|
||||
// SM Configurable Knobs //////////////////////////////////////////////////////
|
||||
|
||||
// per thread stack size
|
||||
#ifndef STACK_SIZE
|
||||
#define STACK_SIZE 1024
|
||||
#endif
|
||||
|
||||
// Size of cache in bytes
|
||||
#ifndef SMEM_SIZE
|
||||
#define SMEM_SIZE (STACK_SIZE * NUM_WARPS * NUM_THREADS)
|
||||
#endif
|
||||
|
||||
// Number of banks
|
||||
#ifndef SNUM_BANKS
|
||||
#define SNUM_BANKS NUM_THREADS
|
||||
#endif
|
||||
|
||||
// Core Request Queue Size
|
||||
#ifndef SCREQ_SIZE
|
||||
#define SCREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// L2cache Configurable Knobs /////////////////////////////////////////////////
|
||||
|
||||
// Size of cache in bytes
|
||||
#ifndef L2CACHE_SIZE
|
||||
#define L2CACHE_SIZE 65536
|
||||
#endif
|
||||
|
||||
// Number of banks
|
||||
#ifndef L2NUM_BANKS
|
||||
#define L2NUM_BANKS MIN(NUM_CORES, 4)
|
||||
#endif
|
||||
|
||||
// Core Request Queue Size
|
||||
#ifndef L2CREQ_SIZE
|
||||
#define L2CREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// Miss Handling Register Size
|
||||
#ifndef L2MSHR_SIZE
|
||||
#define L2MSHR_SIZE 16
|
||||
#endif
|
||||
|
||||
// DRAM Request Queue Size
|
||||
#ifndef L2DREQ_SIZE
|
||||
#define L2DREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// DRAM Response Queue Size
|
||||
#ifndef L2DRSQ_SIZE
|
||||
#define L2DRSQ_SIZE MAX(4, (L2NUM_BANKS * 2))
|
||||
#endif
|
||||
|
||||
// L3cache Configurable Knobs /////////////////////////////////////////////////
|
||||
|
||||
// Size of cache in bytes
|
||||
#ifndef L3CACHE_SIZE
|
||||
#define L3CACHE_SIZE 131072
|
||||
#endif
|
||||
|
||||
// Number of banks
|
||||
#ifndef L3NUM_BANKS
|
||||
#define L3NUM_BANKS MIN(NUM_CLUSTERS, 4)
|
||||
#endif
|
||||
|
||||
// Core Request Queue Size
|
||||
#ifndef L3CREQ_SIZE
|
||||
#define L3CREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// Miss Handling Register Size
|
||||
#ifndef L3MSHR_SIZE
|
||||
#define L3MSHR_SIZE 16
|
||||
#endif
|
||||
|
||||
// DRAM Request Queue Size
|
||||
#ifndef L3DREQ_SIZE
|
||||
#define L3DREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// DRAM Response Queue Size
|
||||
#ifndef L3DRSQ_SIZE
|
||||
#define L3DRSQ_SIZE MAX(4, (L3NUM_BANKS * 2))
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -44,8 +44,7 @@ module VX_tex_unit #(
|
|||
// output wire cache_rsp_ready
|
||||
);
|
||||
|
||||
// `UNUSED_VAR (clk)
|
||||
`UNUSED_VAR (reset)
|
||||
`UNUSED_PARAM (CORE_ID)
|
||||
`UNUSED_VAR (reset)
|
||||
|
||||
`UNUSED_VAR(tex_addr)
|
||||
|
|
|
|||
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simX/simX
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Add table
Add a link
Reference in a new issue