minor update

hw/rtl/cache/VX_cache_bank.sv

@@ -616,7 +616,9 @@ module VX_cache_bank #(
         .ready_out (core_rsp_ready)
     );
 
-    assign crsp_queue_stall = crsp_queue_valid && ~crsp_queue_ready;
+    // we use 'do_read_st1' instead 'crsp_queue_valid'
+    // to remove costly 'is_hit_st1' signal from critical paths.
+    assign crsp_queue_stall = do_read_st1 && ~crsp_queue_ready;
 
     // schedule memory request
 

hw/rtl/cache/VX_cache_mshr.sv

@@ -101,8 +101,8 @@ module VX_cache_mshr #(
 );
     `UNUSED_PARAM (BANK_ID)
 
-    reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
-    reg [MSHR_ADDR_WIDTH-1:0] next_index [MSHR_SIZE-1:0];
+    reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [0:MSHR_SIZE-1];
+    reg [MSHR_ADDR_WIDTH-1:0] next_index [0:MSHR_SIZE-1];
 
     reg [MSHR_SIZE-1:0] valid_table, valid_table_n;
     reg [MSHR_SIZE-1:0] next_table, next_table_x, next_table_n;