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arbiters unlock refactoring

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This commit is contained in:
Blaise Tine 2024-02-04 20:16:18 -08:00
parent fe15647f98
commit 6f7a389a1f
10 changed files with 74 additions and 97 deletions
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12
hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -130,20 +130,20 @@ module VX_cache_bypass #(
assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_idxs;
wire core_req_in_fire = | (core_req_valid_in & core_req_ready_in);
wire core_req_nc_ready = ~mem_req_valid_in && mem_req_ready_out;
VX_generic_arbiter #(
.NUM_REQS (NUM_REQS),
.TYPE (PASSTHRU ? "R" : "P"),
.LOCK_ENABLE (1)
) req_arb (
) core_req_nc_arb (
.clk (clk),
.reset (reset),
.unlock (core_req_in_fire),
.reset (reset),
.requests (core_req_valid_in_nc),
.grant_index (core_req_nc_idx),
.grant_onehot (core_req_nc_sel),
.grant_valid (core_req_nc_valid)
.grant_valid (core_req_nc_valid),
.grant_unlock (core_req_nc_ready)
);
assign core_req_valid_out = core_req_valid_in & ~core_req_nc_idxs;
@ -164,7 +164,7 @@ module VX_cache_bypass #(
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_ready_in[i] = core_req_valid_in_nc[i] ? (~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i])
assign core_req_ready_in[i] = core_req_valid_in_nc[i] ? (core_req_nc_ready && core_req_nc_sel[i])
: core_req_ready_out[i];
end

11
hw/rtl/libs/VX_cyclic_arbiter.sv
View file

@ -21,15 +21,12 @@ module VX_cyclic_arbiter #(
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire unlock,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
output wire grant_valid,
input wire grant_unlock
);
`UNUSED_PARAM (LOCK_ENABLE)
`UNUSED_VAR (unlock)
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
@ -51,7 +48,7 @@ module VX_cyclic_arbiter #(
end else begin
if (!IS_POW2 && grant_index_r == LOG_NUM_REQS'(NUM_REQS-1)) begin
grant_index_r <= '0;
end else begin
end else if (!LOCK_ENABLE || ~grant_valid || grant_unlock) begin
grant_index_r <= grant_index_r + LOG_NUM_REQS'(1);
end
end

12
hw/rtl/libs/VX_fair_arbiter.sv
View file

@ -21,17 +21,17 @@ module VX_fair_arbiter #(
) (
input wire clk,
input wire reset,
input wire unlock,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
output wire grant_valid,
input wire grant_unlock
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (unlock)
`UNUSED_VAR (grant_unlock)
assign grant_index = '0;
assign grant_onehot = requests;
@ -48,18 +48,14 @@ module VX_fair_arbiter #(
always @(posedge clk) begin
if (reset) begin
buffer <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
buffer <= buffer_n;
end
end
VX_priority_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
) priority_arbiter (
.clk (clk),
.reset (reset),
.unlock (unlock),
.requests (requests_qual),
.grant_index (grant_index),
.grant_onehot (grant_onehot),

35
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -21,22 +21,23 @@ module VX_generic_arbiter #(
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire unlock,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
output wire grant_valid,
input wire grant_unlock
);
if (TYPE == "P") begin
`UNUSED_PARAM (LOCK_ENABLE)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_unlock)
VX_priority_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
.NUM_REQS (NUM_REQS),
) priority_arbiter (
.clk (clk),
.reset (reset),
.unlock (unlock),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
@ -50,12 +51,12 @@ module VX_generic_arbiter #(
.LOCK_ENABLE (LOCK_ENABLE)
) rr_arbiter (
.clk (clk),
.reset (reset),
.unlock (unlock),
.reset (reset),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot)
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
);
end else if (TYPE == "F") begin
@ -66,11 +67,11 @@ module VX_generic_arbiter #(
) fair_arbiter (
.clk (clk),
.reset (reset),
.unlock (unlock),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot)
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
);
end else if (TYPE == "M") begin
@ -81,11 +82,11 @@ module VX_generic_arbiter #(
) matrix_arbiter (
.clk (clk),
.reset (reset),
.unlock (unlock),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot)
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
);
end else if (TYPE == "C") begin
@ -96,11 +97,11 @@ module VX_generic_arbiter #(
) cyclic_arbiter (
.clk (clk),
.reset (reset),
.unlock (unlock),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot)
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
);
end else begin

14
hw/rtl/libs/VX_matrix_arbiter.sv
View file

@ -20,18 +20,18 @@ module VX_matrix_arbiter #(
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire unlock,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
output wire grant_valid,
input wire grant_unlock
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (unlock)
`UNUSED_VAR (grant_unlock)
assign grant_index = '0;
assign grant_onehot = requests;
@ -71,18 +71,18 @@ module VX_matrix_arbiter #(
end
if (LOCK_ENABLE == 0) begin
`UNUSED_VAR (unlock)
`UNUSED_VAR (grant_unlock)
assign grant_onehot = grant_unqual;
end else begin
reg [NUM_REQS-1:0] grant_unqual_prev;
always @(posedge clk) begin
if (reset) begin
grant_unqual_prev <= '0;
end else if (unlock) begin
end else if (grant_unlock) begin
grant_unqual_prev <= grant_unqual;
end
end
assign grant_onehot = unlock ? grant_unqual : grant_unqual_prev;
assign grant_onehot = grant_unlock ? grant_unqual : grant_unqual_prev;
end
VX_onehot_encoder #(

16
hw/rtl/libs/VX_mem_rsp_sel.sv
View file

@ -21,7 +21,7 @@ module VX_mem_rsp_sel #(
parameter TAG_SEL_BITS = 0,
parameter OUT_REG = 0
) (
input wire clk,
input wire clk,
input wire reset,
// input response
@ -46,18 +46,20 @@ input wire clk,
wire [LOG_NUM_REQS-1:0] grant_index;
wire grant_valid;
wire rsp_fire;
wire grant_ready;
VX_priority_arbiter #(
.NUM_REQS (NUM_REQS)
VX_generic_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (1),
.TYPE ("P")
) arbiter (
.clk (clk),
.reset (reset),
.unlock (rsp_fire),
.requests (rsp_valid_in),
.grant_valid (grant_valid),
.grant_index (grant_index),
`UNUSED_PIN (grant_onehot)
`UNUSED_PIN (grant_onehot),
.grant_unlock(grant_ready)
);
reg [NUM_REQS-1:0] rsp_valid_sel;
@ -78,7 +80,7 @@ input wire clk,
end
end
assign rsp_fire = grant_valid && rsp_ready_unqual;
assign grant_ready = rsp_ready_unqual;
VX_elastic_buffer #(
.DATAW (NUM_REQS + TAG_WIDTH + (NUM_REQS * DATA_WIDTH)),

13
hw/rtl/libs/VX_priority_arbiter.sv
View file

@ -16,22 +16,13 @@
`TRACING_OFF
module VX_priority_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire unlock,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
`UNUSED_PARAM (LOCK_ENABLE)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (unlock)
if (NUM_REQS == 1) begin
assign grant_index = '0;

26
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -21,18 +21,18 @@ module VX_rr_arbiter #(
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire unlock,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
output wire grant_valid,
input wire grant_unlock
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (unlock)
`UNUSED_VAR (grant_unlock)
assign grant_index = '0;
assign grant_onehot = requests;
@ -55,7 +55,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -85,7 +85,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -121,7 +121,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -165,7 +165,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -219,7 +219,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -285,7 +285,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -365,7 +365,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end
@ -399,7 +399,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
pointer_reg <= {NUM_REQS{1'b1}};
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
if (|req_masked) begin
pointer_reg <= mask_higher_pri_regs;
end else if (|requests) begin
@ -443,7 +443,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || unlock) begin
end else if (!LOCK_ENABLE || grant_unlock) begin
state <= grant_index_r;
end
end

27
hw/rtl/libs/VX_stream_arb.sv
View file

@ -19,7 +19,6 @@ module VX_stream_arb #(
parameter NUM_OUTPUTS = 1,
parameter DATAW = 1,
parameter `STRING ARBITER = "P",
parameter LOCK_ENABLE = 1,
parameter MAX_FANOUT = `MAX_FANOUT,
parameter OUT_REG = 0 ,
parameter NUM_REQS = (NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS,
@ -57,7 +56,6 @@ module VX_stream_arb #(
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) arb_slice (
@ -102,7 +100,6 @@ module VX_stream_arb #(
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) fanout_slice_arb (
@ -129,7 +126,6 @@ module VX_stream_arb #(
.NUM_OUTPUTS (1),
.DATAW (DATAW + LOG_NUM_REQS2),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) fanout_join_arb (
@ -158,25 +154,25 @@ module VX_stream_arb #(
wire arb_valid;
wire [NUM_REQS_W-1:0] arb_index;
wire [NUM_REQS-1:0] arb_onehot;
wire arb_unlock;
wire arb_ready;
VX_generic_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE),
.LOCK_ENABLE (1),
.TYPE (ARBITER)
) arbiter (
.clk (clk),
.reset (reset),
.requests (valid_in),
.unlock (arb_unlock),
.grant_valid (arb_valid),
.grant_index (arb_index),
.grant_onehot (arb_onehot)
.grant_onehot (arb_onehot),
.grant_unlock (arb_ready)
);
assign valid_in_r = arb_valid;
assign data_in_r = data_in[arb_index];
assign arb_unlock = | (valid_in_r & ready_in_r);
assign arb_ready = ready_in_r;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign ready_in[i] = ready_in_r & arb_onehot[i];
@ -217,7 +213,6 @@ module VX_stream_arb #(
.NUM_OUTPUTS (BATCH_SIZE),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) arb_slice (
@ -252,7 +247,6 @@ module VX_stream_arb #(
.NUM_OUTPUTS (NUM_BATCHES),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) fanout_fork_arb (
@ -280,7 +274,6 @@ module VX_stream_arb #(
.NUM_OUTPUTS (BATCH_SIZE),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) fanout_slice_arb (
@ -305,24 +298,24 @@ module VX_stream_arb #(
wire [NUM_OUTPUTS-1:0] arb_requests;
wire arb_valid;
wire [NUM_OUTPUTS-1:0] arb_onehot;
wire arb_unlock;
wire arb_ready;
VX_generic_arbiter #(
.NUM_REQS (NUM_OUTPUTS),
.LOCK_ENABLE (LOCK_ENABLE),
.LOCK_ENABLE (1),
.TYPE (ARBITER)
) arbiter (
.clk (clk),
.reset (reset),
.requests (arb_requests),
.unlock (arb_unlock),
.grant_valid (arb_valid),
`UNUSED_PIN (grant_index),
.grant_onehot (arb_onehot)
.grant_onehot (arb_onehot),
.grant_unlock (arb_ready)
);
assign arb_requests = ready_in_r;
assign arb_unlock = | (valid_in & ready_in);
assign arb_ready = valid_in[0];
assign ready_in = arb_valid;
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin

5
hw/rtl/libs/VX_stream_xbar.sv
View file

@ -21,8 +21,7 @@ module VX_stream_xbar #(
parameter IN_WIDTH = `LOG2UP(NUM_INPUTS),
parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS),
parameter ARBITER = "P",
parameter LOCK_ENABLE = 0,
parameter OUT_REG = 0,
parameter OUT_REG = 0,
parameter MAX_FANOUT = `MAX_FANOUT,
parameter PERF_CTR_BITS = `CLOG2(NUM_INPUTS+1)
) (
@ -66,7 +65,6 @@ module VX_stream_xbar #(
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) xbar_arb (
@ -95,7 +93,6 @@ module VX_stream_xbar #(
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.LOCK_ENABLE (LOCK_ENABLE),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
) xbar_arb (