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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
b0b7cd2b1e
commit
fe15647f98
2 changed files with 66 additions and 67 deletions
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@ -47,8 +47,6 @@ module VX_operands import VX_gpu_pkg::*; #(
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reg [`NUM_THREADS-1:0] cache_tmask_n [ISSUE_RATIO-1:0];
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reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n;
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reg valid_out_r;
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reg [DATAW-1:0] data_out_r;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n;
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@ -60,7 +58,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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reg rs3_ready, rs3_ready_n;
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reg data_ready, data_ready_n;
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wire ready_out = operands_if[i].ready;
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wire stg_valid_in, stg_ready_in;
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wire is_rs1_zero = (scoreboard_if[i].data.rs1 == 0);
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wire is_rs2_zero = (scoreboard_if[i].data.rs2 == 0);
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@ -85,7 +83,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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case (state)
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STATE_IDLE: begin
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if (valid_out_r && ready_out) begin
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if (operands_if[i].valid && operands_if[i].ready) begin
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data_ready_n = 0;
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end
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if (scoreboard_if[i].valid && data_ready_n == 0) begin
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@ -173,37 +171,15 @@ module VX_operands import VX_gpu_pkg::*; #(
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end
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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state <= STATE_IDLE;
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cache_eop <= {ISSUE_RATIO{1'b1}};
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data_ready <= 0;
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valid_out_r <= 0;
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end else begin
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state <= state_n;
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cache_eop <= cache_eop_n;
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data_ready <= data_ready_n;
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if (~valid_out_r) begin
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valid_out_r <= scoreboard_if[i].valid && data_ready;
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end else if (ready_out) begin
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valid_out_r <= 0;
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end
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data_ready <= data_ready_n;
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end
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if (~valid_out_r) begin
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data_out_r <= {scoreboard_if[i].data.uuid,
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scoreboard_if[i].data.wis,
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scoreboard_if[i].data.tmask,
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scoreboard_if[i].data.PC,
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scoreboard_if[i].data.wb,
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scoreboard_if[i].data.ex_type,
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scoreboard_if[i].data.op_type,
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scoreboard_if[i].data.op_mod,
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scoreboard_if[i].data.use_PC,
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scoreboard_if[i].data.use_imm,
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scoreboard_if[i].data.imm,
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scoreboard_if[i].data.rd};
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end
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gpr_rd_rid <= gpr_rd_rid_n;
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gpr_rd_wis <= gpr_rd_wis_n;
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rs2_ready <= rs2_ready_n;
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@ -216,10 +192,35 @@ module VX_operands import VX_gpu_pkg::*; #(
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cache_data <= cache_data_n;
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cache_reg <= cache_reg_n;
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cache_tmask <= cache_tmask_n;
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end
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end
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assign operands_if[i].valid = valid_out_r;
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assign {operands_if[i].data.uuid,
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assign stg_valid_in = scoreboard_if[i].valid && data_ready;
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assign scoreboard_if[i].ready = stg_ready_in && data_ready;
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VX_toggle_buffer #(
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.DATAW (DATAW)
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) staging_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (stg_valid_in),
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.data_in ({
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scoreboard_if[i].data.uuid,
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scoreboard_if[i].data.wis,
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scoreboard_if[i].data.tmask,
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scoreboard_if[i].data.PC,
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scoreboard_if[i].data.wb,
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scoreboard_if[i].data.ex_type,
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scoreboard_if[i].data.op_type,
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scoreboard_if[i].data.op_mod,
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scoreboard_if[i].data.use_PC,
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scoreboard_if[i].data.use_imm,
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scoreboard_if[i].data.imm,
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scoreboard_if[i].data.rd
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}),
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.ready_in (stg_ready_in),
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.valid_out (operands_if[i].valid),
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.data_out ({
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operands_if[i].data.uuid,
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operands_if[i].data.wis,
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operands_if[i].data.tmask,
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operands_if[i].data.PC,
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@ -230,13 +231,15 @@ module VX_operands import VX_gpu_pkg::*; #(
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operands_if[i].data.use_PC,
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operands_if[i].data.use_imm,
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operands_if[i].data.imm,
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operands_if[i].data.rd} = data_out_r;
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operands_if[i].data.rd
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}),
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.ready_out (operands_if[i].ready)
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);
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assign operands_if[i].data.rs1_data = rs1_data;
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assign operands_if[i].data.rs2_data = rs2_data;
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assign operands_if[i].data.rs3_data = rs3_data;
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assign scoreboard_if[i].ready = ~valid_out_r && data_ready;
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// GPR banks
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reg [RAM_ADDRW-1:0] gpr_rd_addr;
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@ -152,51 +152,47 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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assign perf_issue_stalls_per_cycle[i] = ibuffer_if[i].valid && ~ibuffer_if[i].ready;
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`endif
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reg [DATAW-1:0] data_out_r;
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reg valid_out_r;
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wire ready_out;
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wire [3:0] operands_busy = {inuse_rd, inuse_rs1, inuse_rs2, inuse_rs3};
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wire operands_ready = ~(| operands_busy);
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wire stg_valid_in, stg_ready_in;
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assign stg_valid_in = ibuffer_if[i].valid && operands_ready;
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assign ibuffer_if[i].ready = stg_ready_in && operands_ready;
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wire [3:0] ready_masks = ~{inuse_rd, inuse_rs1, inuse_rs2, inuse_rs3};
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wire deps_ready = (& ready_masks);
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wire valid_in = ibuffer_if[i].valid && deps_ready;
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wire ready_in = ~valid_out_r && deps_ready;
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wire [DATAW-1:0] data_in = ibuffer_if[i].data;
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assign ready_out = scoreboard_if[i].ready;
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VX_stream_buffer #(
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.DATAW (DATAW)
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) staging_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (stg_valid_in),
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.data_in (ibuffer_if[i].data),
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.ready_in (stg_ready_in),
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.valid_out (scoreboard_if[i].valid),
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.data_out (scoreboard_if[i].data),
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.ready_out (scoreboard_if[i].ready)
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);
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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inuse_regs <= '0;
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end else begin
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if (writeback_fire) begin
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inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] <= 0;
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end
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if (~valid_out_r) begin
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valid_out_r <= valid_in;
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end else if (ready_out) begin
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if (scoreboard_if[i].data.wb) begin
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inuse_regs[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= 1;
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`ifdef PERF_ENABLE
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inuse_units[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= scoreboard_if[i].data.ex_type;
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if (scoreboard_if[i].data.ex_type == `EX_SFU) begin
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inuse_sfu[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= sfu_type;
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end
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`endif
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end
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valid_out_r <= 0;
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if (stg_valid_in && stg_ready_in && ibuffer_if[i].data.wb) begin
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inuse_regs[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] <= 1;
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end
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end
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if (~valid_out_r) begin
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data_out_r <= data_in;
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`ifdef PERF_ENABLE
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if (stg_valid_in && stg_ready_in && ibuffer_if[i].data.wb) begin
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inuse_units[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] <= ibuffer_if[i].data.ex_type;
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if (ibuffer_if[i].data.ex_type == `EX_SFU) begin
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inuse_sfu[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd] <= sfu_type;
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end
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end
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`endif
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end
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assign ibuffer_if[i].ready = ready_in;
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assign scoreboard_if[i].valid = valid_out_r;
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assign scoreboard_if[i].data = data_out_r;
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`ifdef SIMULATION
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reg [31:0] timeout_ctr;
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@ -208,7 +204,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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`ifdef DBG_TRACE_CORE_PIPELINE
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`TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n",
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$time, CORE_ID, wis_to_wid(ibuffer_if[i].data.wis, i), ibuffer_if[i].data.PC, ibuffer_if[i].data.tmask, timeout_ctr,
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~ready_masks, ibuffer_if[i].data.uuid));
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operands_busy, ibuffer_if[i].data.uuid));
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`endif
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timeout_ctr <= timeout_ctr + 1;
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end else if (ibuffer_if[i].valid && ibuffer_if[i].ready) begin
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@ -220,7 +216,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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`RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT),
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("%t: *** core%0d-scoreboard-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)",
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$time, CORE_ID, wis_to_wid(ibuffer_if[i].data.wis, i), ibuffer_if[i].data.PC, ibuffer_if[i].data.tmask, timeout_ctr,
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~ready_masks, ibuffer_if[i].data.uuid));
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operands_busy, ibuffer_if[i].data.uuid));
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`RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] != 0,
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("%t: *** core%0d: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",
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