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added support for write-through cache, removed cache snooping support

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This commit is contained in:
Blaise Tine 2020-12-23 23:51:02 -08:00
parent d956e268b9
commit 703a861fe9
55 changed files with 1077 additions and 2178 deletions
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10
benchmarks/opencl/Makefile
View file

@ -20,4 +20,12 @@ clean:
$(MAKE) -C saxpy clean
$(MAKE) -C sfilter clean
$(MAKE) -C nearn clean
$(MAKE) -C guassian clean
$(MAKE) -C guassian clean
clean-all:
$(MAKE) -C vecadd clean-all
$(MAKE) -C sgemm clean-all
$(MAKE) -C saxpy clean-all
$(MAKE) -C sfilter clean-all
$(MAKE) -C nearn clean-all
$(MAKE) -C guassian clean-all

3
benchmarks/opencl/bfs/Makefile
View file

@ -51,6 +51,9 @@ run-rtlsim: $(PROJECT) kernel.pocl
clean:
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif

5
benchmarks/opencl/convolution/Makefile
View file

@ -49,7 +49,10 @@ run-rtlsim: $(PROJECT) kernel.pocl
$(CXX) $(CXXFLAGS) -MM $^ > .depend;
clean:
rm -rf $(PROJECT) *.o .depend
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend

5
benchmarks/opencl/guassian/Makefile
View file

@ -52,7 +52,10 @@ run-rtlsim: $(PROJECT) kernel.pocl
$(CXX) $(CXXFLAGS) -MM $^ > .depend;
clean:
rm -rf $(PROJECT) *.o .depend
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend

3
benchmarks/opencl/kmeans/Makefile
View file

@ -51,6 +51,9 @@ run-rtlsim: $(PROJECT) kernel.pocl
clean:
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif

3
benchmarks/opencl/nearn/Makefile
View file

@ -54,6 +54,9 @@ run-rtlsim: $(PROJECT) kernel.pocl
clean:
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif

5
benchmarks/opencl/saxpy/Makefile
View file

@ -51,7 +51,10 @@ run-rtlsim: $(PROJECT) kernel.pocl
$(CXX) $(CXXFLAGS) -MM $^ > .depend;
clean:
rm -rf $(PROJECT) *.o .depend
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend

3
benchmarks/opencl/sfilter/Makefile
View file

@ -53,6 +53,9 @@ run-rtlsim: $(PROJECT) kernel.pocl
clean:
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif

5
benchmarks/opencl/sgemm/Makefile
View file

@ -51,7 +51,10 @@ run-rtlsim: $(PROJECT) kernel.pocl
$(CXX) $(CXXFLAGS) -MM $^ > .depend;
clean:
rm -rf $(PROJECT) *.o .depend
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend

5
benchmarks/opencl/transpose/Makefile
View file

@ -49,7 +49,10 @@ run-rtlsim: $(PROJECT) kernel.pocl
$(CXX) $(CXXFLAGS) -MM $^ > .depend;
clean:
rm -rf $(PROJECT) *.o .depend
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend

3
benchmarks/opencl/vecadd/Makefile
View file

@ -53,6 +53,9 @@ run-rtlsim: $(PROJECT) kernel.pocl
clean:
rm -rf $(PROJECT) *.o .depend
clean-all: clean
rm *.pocl *.dump
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif

2
ci/blackbox.sh
View file

@ -9,7 +9,7 @@ show_usage()
echo "Usage: [[--clusters=#n] [--cores=#n] [--warps=#n] [--threads=#n] [--l2cache] [--l3cache] [[--driver=rtlsim|vlsim] [--debug] [--scope] [--perf] [--app=vecadd|sgemm|basic|demo|dogfood] [--args=<args>] [--help]]"
}
SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
SCRIPT_DIR=$(dirname "$0")
VORTEX_HOME=$SCRIPT_DIR/..
DRIVER=vlsim

3
driver/include/vortex.h
View file

@ -43,9 +43,6 @@ int vx_buf_release(vx_buffer_h hbuffer);
// allocate device memory and return address
int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr);
// Copy bytes from device local memory to buffer
int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size);
// Copy bytes from buffer to device local memory
int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, size_t src_offset);

31
driver/opae/vortex.cpp
View file

@ -41,7 +41,6 @@
#define CMD_MEM_READ AFU_IMAGE_CMD_MEM_READ
#define CMD_MEM_WRITE AFU_IMAGE_CMD_MEM_WRITE
#define CMD_RUN AFU_IMAGE_CMD_RUN
#define CMD_CLFLUSH AFU_IMAGE_CMD_CLFLUSH
#define CMD_CSR_READ AFU_IMAGE_CMD_CSR_READ
#define CMD_CSR_WRITE AFU_IMAGE_CMD_CSR_WRITE
@ -462,36 +461,6 @@ extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size,
return 0;
}
extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) {
if (nullptr == hdevice
|| 0 >= size)
return -1;
vx_device_t* device = ((vx_device_t*)hdevice);
size_t asize = align_size(size, CACHE_BLOCK_SIZE);
// check alignment
if (!is_aligned(dev_maddr, CACHE_BLOCK_SIZE))
return -1;
// Ensure ready for new command
if (vx_ready_wait(hdevice, -1) != 0)
return -1;
auto ls_shift = (int)std::log2(CACHE_BLOCK_SIZE);
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift));
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift));
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CLFLUSH));
// Wait for the write operation to finish
if (vx_ready_wait(hdevice, -1) != 0)
return -1;
return 0;
}
extern int vx_start(vx_device_h hdevice) {
if (nullptr == hdevice)
return -1;

5
driver/opae/vortex_afu.h
View file

@ -7,9 +7,8 @@
#define AFU_ACCEL_NAME "vortex_afu"
#define AFU_ACCEL_UUID "35F9452B-25C2-434C-93D5-6F8C60DB361C"
#define AFU_IMAGE_CMD_CLFLUSH 4
#define AFU_IMAGE_CMD_CSR_READ 5
#define AFU_IMAGE_CMD_CSR_WRITE 6
#define AFU_IMAGE_CMD_CSR_READ 4
#define AFU_IMAGE_CMD_CSR_WRITE 5
#define AFU_IMAGE_CMD_MEM_READ 1
#define AFU_IMAGE_CMD_MEM_WRITE 2
#define AFU_IMAGE_CMD_RUN 3

23
driver/rtlsim/vortex.cpp
View file

@ -140,19 +140,6 @@ public:
return 0;
}
int flush_caches(size_t dev_maddr, size_t size) {
if (future_.valid()) {
future_.wait(); // ensure prior run completed
}
simulator_.attach_ram(&ram_);
simulator_.flush_caches(dev_maddr, size);
while (simulator_.snp_req_active()) {
simulator_.step();
};
simulator_.attach_ram(NULL);
return 0;
}
int set_csr(int core_id, int addr, unsigned value) {
if (future_.valid()) {
future_.wait(); // ensure prior run completed
@ -257,16 +244,6 @@ extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr)
return device->alloc_local_mem(size, dev_maddr);
}
extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) {
if (nullptr == hdevice
|| 0 >= size)
return -1;
vx_device *device = ((vx_device*)hdevice);
return device->flush_caches(dev_maddr, size);
}
extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer) {
if (nullptr == hdevice

8
driver/simx/vortex.cpp
View file

@ -267,14 +267,6 @@ extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr)
return device->alloc_local_mem(size, dev_maddr);
}
extern int vx_flush_caches(vx_device_h hdevice, size_t /*dev_maddr*/, size_t size) {
if (nullptr == hdevice
|| 0 >= size)
return -1;
// this functionality is not need by simX
return 0;
}
extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer) {
if (nullptr == hdevice
|| 0 >= size

4
driver/stub/vortex.cpp
View file

@ -16,10 +16,6 @@ extern int vx_alloc_dev_mem(vx_device_h /*hdevice*/, size_t /*size*/, size_t* /*
return -1;
}
extern int vx_flush_caches(vx_device_h /*hdevice*/, size_t /*dev_maddr*/, size_t /*size*/) {
return -1;
}
extern int vx_alloc_shared_mem(vx_device_h /*hdevice*/, size_t /*size*/, vx_buffer_h* /*hbuffer*/) {
return -1;
}

5
driver/tests/Makefile
View file

@ -13,3 +13,8 @@ clean:
$(MAKE) -C demo clean
$(MAKE) -C dogfood clean
clean-all:
$(MAKE) -C basic clean-all
$(MAKE) -C demo clean-all
$(MAKE) -C dogfood clean-all

12
driver/tests/basic/basic.cpp
View file

@ -171,17 +171,11 @@ int run_kernel_test(const kernel_arg_t& kernel_arg,
RT_CHECK(vx_ready_wait(device, -1));
auto t3 = std::chrono::high_resolution_clock::now();
// flush the caches
std::cout << "flush the caches" << std::endl;
auto t4 = std::chrono::high_resolution_clock::now();
RT_CHECK(vx_flush_caches(device, kernel_arg.dst_ptr, buf_size));
auto t5 = std::chrono::high_resolution_clock::now();
// read buffer from local memory
std::cout << "read buffer from local memory" << std::endl;
auto t6 = std::chrono::high_resolution_clock::now();
auto t4 = std::chrono::high_resolution_clock::now();
RT_CHECK(vx_copy_from_dev(buffer, kernel_arg.dst_ptr, buf_size, 0));
auto t7 = std::chrono::high_resolution_clock::now();
auto t5 = std::chrono::high_resolution_clock::now();
// verify result
@ -210,8 +204,6 @@ int run_kernel_test(const kernel_arg_t& kernel_arg,
elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t3 - t2).count();
printf("execute time: %lg ms\n", elapsed);
elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t5 - t4).count();
printf("flush time: %lg ms\n", elapsed);
elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(t7 - t6).count();
printf("download time: %lg ms\n", elapsed);
elapsed = std::chrono::duration_cast<std::chrono::milliseconds>(time_end - time_start).count();
printf("Total elapsed time: %lg ms\n", elapsed);

BIN
driver/tests/basic/kernel.bin
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21
driver/tests/basic/kernel.dump
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@ -142,11 +142,11 @@ Disassembly of section .text:
80000180: 00008067 ret
80000184 <vx_num_cycles>:
80000184: c0002573 rdcycle a0
80000184: b0002573 csrr a0,mcycle
80000188: 00008067 ret
8000018c <vx_num_instrs>:
8000018c: c0202573 rdinstret a0
8000018c: b0202573 csrr a0,minstret
80000190: 00008067 ret
80000194 <atexit>:
@ -390,7 +390,7 @@ Disassembly of section .text:
80000518: 00492703 lw a4,4(s2)
8000051c: 148a2783 lw a5,328(s4)
80000520: 01871463 bne a4,s8,80000528 <__call_exitprocs+0xe4>
80000524: f8f904e3 beq s2,a5,800004ac <__call_exitprocs+0x68>
80000524: f92784e3 beq a5,s2,800004ac <__call_exitprocs+0x68>
80000528: f80788e3 beqz a5,800004b8 <__call_exitprocs+0x74>
8000052c: 00078913 mv s2,a5
80000530: f5dff06f j 8000048c <__call_exitprocs+0x48>
@ -450,21 +450,20 @@ Disassembly of section .comment:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm
a: 3920 fld fs0,112(a0)
c: 322e fld ft4,232(sp)
e: 302e fld ft0,232(sp)
...
a: 3120 fld fs0,96(a0)
c: 2e30 fld fa2,88(a2)
e: 2e32 fld ft8,264(sp)
10: 0030 addi a2,sp,8
Disassembly of section .riscv.attributes:
00000000 <.riscv.attributes>:
0: 2541 jal 680 <_start-0x7ffff980>
0: 2941 jal 490 <_start-0x7ffffb70>
2: 0000 unimp
4: 7200 flw fs0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <_start-0x7fffffec>
c: 0000001b 0x1b
10: 1004 addi s1,sp,32
c: 001f 0000 1004 0x10040000001f
12: 7205 lui tp,0xfffe1
14: 3376 fld ft6,376(sp)
16: 6932 flw fs2,12(sp)
@ -473,3 +472,5 @@ Disassembly of section .riscv.attributes:
1c: 326d jal fffff9c6 <__global_pointer$+0x7fffdc5e>
1e: 3070 fld fa2,224(s0)
20: 665f 7032 0030 0x307032665f
26: 0108 addi a0,sp,128
28: 0b0a slli s6,s6,0x2

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driver/tests/basic/kernel.elf
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4
driver/tests/demo/demo.cpp
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@ -69,10 +69,6 @@ int run_test(const kernel_arg_t& kernel_arg,
std::cout << "wait for completion" << std::endl;
RT_CHECK(vx_ready_wait(device, -1));
// flush the destination buffer caches
std::cout << "flush the destination buffer caches" << std::endl;
RT_CHECK(vx_flush_caches(device, kernel_arg.dst_ptr, buf_size));
// download destination buffer
std::cout << "download destination buffer" << std::endl;
RT_CHECK(vx_copy_from_dev(buffer, kernel_arg.dst_ptr, buf_size, 0));

BIN
driver/tests/demo/kernel.bin
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24
driver/tests/demo/kernel.dump
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@ -165,11 +165,11 @@ Disassembly of section .text:
800001d4: 00008067 ret
800001d8 <vx_num_cycles>:
800001d8: c0002573 rdcycle a0
800001d8: b0002573 csrr a0,mcycle
800001dc: 00008067 ret
800001e0 <vx_num_instrs>:
800001e0: c0202573 rdinstret a0
800001e0: b0202573 csrr a0,minstret
800001e4: 00008067 ret
800001e8 <spawn_warp_runonce>:
@ -461,7 +461,7 @@ Disassembly of section .text:
8000061c: 00492703 lw a4,4(s2)
80000620: 148a2783 lw a5,328(s4)
80000624: 01871463 bne a4,s8,8000062c <__call_exitprocs+0xe4>
80000628: f8f904e3 beq s2,a5,800005b0 <__call_exitprocs+0x68>
80000628: f92784e3 beq a5,s2,800005b0 <__call_exitprocs+0x68>
8000062c: f80788e3 beqz a5,800005bc <__call_exitprocs+0x74>
80000630: 00078913 mv s2,a5
80000634: f5dff06f j 80000590 <__call_exitprocs+0x48>
@ -527,22 +527,20 @@ Disassembly of section .comment:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm
a: 3920 fld fs0,112(a0)
c: 322e fld ft4,232(sp)
e: 302e fld ft0,232(sp)
...
a: 3120 fld fs0,96(a0)
c: 2e30 fld fa2,88(a2)
e: 2e32 fld ft8,264(sp)
10: 0030 addi a2,sp,8
Disassembly of section .riscv.attributes:
00000000 <.riscv.attributes>:
0: 2041 jal 80 <_start-0x7fffff80>
0: 2941 jal 490 <_start-0x7ffffb70>
2: 0000 unimp
4: 7200 flw fs0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <_start-0x7fffffec>
c: 0016 c.slli zero,0x5
e: 0000 unimp
10: 1004 addi s1,sp,32
c: 001f 0000 1004 0x10040000001f
12: 7205 lui tp,0xfffe1
14: 3376 fld ft6,376(sp)
16: 6932 flw fs2,12(sp)
@ -550,4 +548,6 @@ Disassembly of section .riscv.attributes:
1a: 5f30 lw a2,120(a4)
1c: 326d jal fffff9c6 <__global_pointer$+0x7fffdb56>
1e: 3070 fld fa2,224(s0)
...
20: 665f 7032 0030 0x307032665f
26: 0108 addi a0,sp,128
28: 0b0a slli s6,s6,0x2

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driver/tests/demo/kernel.elf
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4
driver/tests/dogfood/dogfood.cpp
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@ -245,10 +245,6 @@ int main(int argc, char *argv[]) {
std::cout << "wait for completion" << std::endl;
RT_CHECK(vx_ready_wait(device, -1));
// flush the destination buffer caches
std::cout << "flush the destination buffer caches" << std::endl;
RT_CHECK(vx_flush_caches(device, kernel_arg.dst_ptr, buf_size));
// download destination buffer
std::cout << "download destination buffer" << std::endl;
RT_CHECK(vx_copy_from_dev(dst_buf, kernel_arg.dst_ptr, buf_size, 0));

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driver/tests/dogfood/kernel.bin
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1140
driver/tests/dogfood/kernel.dump
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File diff suppressed because it is too large Load diff

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driver/tests/dogfood/kernel.elf
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5
hw/opae/vortex_afu.json
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@ -8,9 +8,8 @@
"cmd-mem-read": 1,
"cmd-mem-write": 2,
"cmd-run": 3,
"cmd-clflush": 4,
"cmd-csr-read": 5,
"cmd-csr-write": 6,
"cmd-csr-read": 4,
"cmd-csr-write": 5,
"mmio-cmd-type": 10,
"mmio-io-addr": 12,

217
hw/rtl/VX_cluster.v
View file

@ -24,30 +24,18 @@ module VX_cluster #(
input wire [`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`L2DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [`L2SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [`L2SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// CSR Request
input wire csr_io_req_valid,
input wire [`NC_BITS-1:0] csr_io_req_coreid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
input wire csr_req_valid,
input wire [`NC_BITS-1:0] csr_req_coreid,
input wire [11:0] csr_req_addr,
input wire csr_req_rw,
input wire [31:0] csr_req_data,
output wire csr_req_ready,
// CSR Response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
output wire csr_rsp_valid,
output wire [31:0] csr_rsp_data,
input wire csr_rsp_ready,
// Status
output wire busy,
@ -66,25 +54,15 @@ module VX_cluster #(
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_snp_req_valid;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_snp_req_addr;
wire [`NUM_CORES-1:0] per_core_snp_req_inv;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] per_core_snp_req_tag;
wire [`NUM_CORES-1:0] per_core_snp_req_ready;
wire [`NUM_CORES-1:0] per_core_snp_rsp_valid;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] per_core_snp_rsp_tag;
wire [`NUM_CORES-1:0] per_core_snp_rsp_ready;
wire [`NUM_CORES-1:0] per_core_csr_req_valid;
wire [`NUM_CORES-1:0][11:0] per_core_csr_req_addr;
wire [`NUM_CORES-1:0] per_core_csr_req_rw;
wire [`NUM_CORES-1:0][31:0] per_core_csr_req_data;
wire [`NUM_CORES-1:0] per_core_csr_req_ready;
wire [`NUM_CORES-1:0] per_core_csr_io_req_valid;
wire [`NUM_CORES-1:0][11:0] per_core_csr_io_req_addr;
wire [`NUM_CORES-1:0] per_core_csr_io_req_rw;
wire [`NUM_CORES-1:0][31:0] per_core_csr_io_req_data;
wire [`NUM_CORES-1:0] per_core_csr_io_req_ready;
wire [`NUM_CORES-1:0] per_core_csr_io_rsp_valid;
wire [`NUM_CORES-1:0][31:0] per_core_csr_io_rsp_data;
wire [`NUM_CORES-1:0] per_core_csr_io_rsp_ready;
wire [`NUM_CORES-1:0] per_core_csr_rsp_valid;
wire [`NUM_CORES-1:0][31:0] per_core_csr_rsp_data;
wire [`NUM_CORES-1:0] per_core_csr_rsp_ready;
wire [`NUM_CORES-1:0] per_core_busy;
wire [`NUM_CORES-1:0] per_core_ebreak;
@ -95,129 +73,77 @@ module VX_cluster #(
) core (
`SCOPE_BIND_VX_cluster_core(i)
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
.dram_req_valid (per_core_dram_req_valid [i]),
.dram_req_rw (per_core_dram_req_rw [i]),
.dram_req_byteen (per_core_dram_req_byteen [i]),
.dram_req_addr (per_core_dram_req_addr [i]),
.dram_req_data (per_core_dram_req_data [i]),
.dram_req_tag (per_core_dram_req_tag [i]),
.dram_req_ready (per_core_dram_req_ready [i]),
.dram_req_valid (per_core_dram_req_valid[i]),
.dram_req_rw (per_core_dram_req_rw [i]),
.dram_req_byteen(per_core_dram_req_byteen[i]),
.dram_req_addr (per_core_dram_req_addr [i]),
.dram_req_data (per_core_dram_req_data [i]),
.dram_req_tag (per_core_dram_req_tag [i]),
.dram_req_ready (per_core_dram_req_ready[i]),
.dram_rsp_valid (per_core_dram_rsp_valid [i]),
.dram_rsp_data (per_core_dram_rsp_data [i]),
.dram_rsp_tag (per_core_dram_rsp_tag [i]),
.dram_rsp_ready (per_core_dram_rsp_ready [i]),
.dram_rsp_valid (per_core_dram_rsp_valid[i]),
.dram_rsp_data (per_core_dram_rsp_data [i]),
.dram_rsp_tag (per_core_dram_rsp_tag [i]),
.dram_rsp_ready (per_core_dram_rsp_ready[i]),
.snp_req_valid (per_core_snp_req_valid [i]),
.snp_req_addr (per_core_snp_req_addr [i]),
.snp_req_inv (per_core_snp_req_inv [i]),
.snp_req_tag (per_core_snp_req_tag [i]),
.snp_req_ready (per_core_snp_req_ready [i]),
.csr_req_valid (per_core_csr_req_valid [i]),
.csr_req_rw (per_core_csr_req_rw [i]),
.csr_req_addr (per_core_csr_req_addr [i]),
.csr_req_data (per_core_csr_req_data [i]),
.csr_req_ready (per_core_csr_req_ready [i]),
.snp_rsp_valid (per_core_snp_rsp_valid [i]),
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.csr_rsp_valid (per_core_csr_rsp_valid [i]),
.csr_rsp_data (per_core_csr_rsp_data [i]),
.csr_rsp_ready (per_core_csr_rsp_ready [i]),
.csr_io_req_valid (per_core_csr_io_req_valid[i]),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready[i]),
.csr_io_rsp_valid (per_core_csr_io_rsp_valid[i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready[i]),
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
);
end
VX_csr_io_arb #(
VX_csr_arb #(
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (32),
.ADDR_WIDTH (12),
.BUFFERED_REQ (1),
.BUFFERED_RSP (`NUM_CORES >= 4)
) csr_io_arb (
) csr_arb (
.clk (clk),
.reset (reset),
.request_id (csr_io_req_coreid),
.request_id (csr_req_coreid),
// input requests
.req_valid_in (csr_io_req_valid),
.req_addr_in (csr_io_req_addr),
.req_rw_in (csr_io_req_rw),
.req_data_in (csr_io_req_data),
.req_ready_in (csr_io_req_ready),
.req_valid_in (csr_req_valid),
.req_addr_in (csr_req_addr),
.req_rw_in (csr_req_rw),
.req_data_in (csr_req_data),
.req_ready_in (csr_req_ready),
// output request
.req_valid_out (per_core_csr_io_req_valid),
.req_addr_out (per_core_csr_io_req_addr),
.req_rw_out (per_core_csr_io_req_rw),
.req_data_out (per_core_csr_io_req_data),
.req_ready_out (per_core_csr_io_req_ready),
.req_valid_out (per_core_csr_req_valid),
.req_addr_out (per_core_csr_req_addr),
.req_rw_out (per_core_csr_req_rw),
.req_data_out (per_core_csr_req_data),
.req_ready_out (per_core_csr_req_ready),
// input responses
.rsp_valid_in (per_core_csr_io_rsp_valid),
.rsp_data_in (per_core_csr_io_rsp_data),
.rsp_ready_in (per_core_csr_io_rsp_ready),
.rsp_valid_in (per_core_csr_rsp_valid),
.rsp_data_in (per_core_csr_rsp_data),
.rsp_ready_in (per_core_csr_rsp_ready),
// output response
.rsp_valid_out (csr_io_rsp_valid),
.rsp_data_out (csr_io_rsp_data),
.rsp_ready_out (csr_io_rsp_ready)
.rsp_valid_out (csr_rsp_valid),
.rsp_data_out (csr_rsp_data),
.rsp_ready_out (csr_rsp_ready)
);
assign busy = (| per_core_busy);
assign ebreak = (| per_core_ebreak);
wire snp_fwd_rsp_valid;
wire [`L2DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L2SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
VX_snp_forwarder #(
.CACHE_ID (`L2CACHE_ID),
.NUM_REQS (`NUM_CORES),
.SRC_ADDR_WIDTH (`L2DRAM_ADDR_WIDTH),
.DST_ADDR_WIDTH (`DDRAM_ADDR_WIDTH),
.SREQ_SIZE (`L2SREQ_SIZE),
.TAG_IN_WIDTH (`L2SNP_TAG_WIDTH),
.TAG_OUT_WIDTH (`DSNP_TAG_WIDTH),
.BUFFERED (`NUM_CORES >= 4)
) snp_forwarder (
.clk (clk),
.reset (reset),
.snp_req_valid (snp_req_valid),
.snp_req_addr (snp_req_addr),
.snp_req_inv (snp_req_inv),
.snp_req_tag (snp_req_tag),
.snp_req_ready (snp_req_ready),
.snp_rsp_valid (snp_fwd_rsp_valid),
.snp_rsp_addr (snp_fwd_rsp_addr),
.snp_rsp_inv (snp_fwd_rsp_inv),
.snp_rsp_tag (snp_fwd_rsp_tag),
.snp_rsp_ready (snp_fwd_rsp_ready),
.snp_fwdout_valid (per_core_snp_req_valid),
.snp_fwdout_addr (per_core_snp_req_addr),
.snp_fwdout_inv (per_core_snp_req_inv),
.snp_fwdout_tag (per_core_snp_req_tag),
.snp_fwdout_ready (per_core_snp_req_ready),
.snp_fwdin_valid (per_core_snp_rsp_valid),
.snp_fwdin_tag (per_core_snp_rsp_tag),
.snp_fwdin_ready (per_core_snp_rsp_ready)
);
if (`L2_ENABLE) begin
`ifdef PERF_ENABLE
VX_perf_cache_if perf_l2cache_if();
@ -233,17 +159,13 @@ module VX_cluster #(
.CREQ_SIZE (`L2CREQ_SIZE),
.MSHR_SIZE (`L2MSHR_SIZE),
.DRSQ_SIZE (`L2DRSQ_SIZE),
.SREQ_SIZE (`L2SREQ_SIZE),
.CRSQ_SIZE (`L2CRSQ_SIZE),
.DREQ_SIZE (`L2DREQ_SIZE),
.SRSQ_SIZE (`L2SRSQ_SIZE),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`XDRAM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
.SNP_TAG_WIDTH (`L2SNP_TAG_WIDTH)
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
) l2cache (
`SCOPE_BIND_VX_cluster_l2cache
@ -284,18 +206,6 @@ module VX_cluster #(
.dram_rsp_data (dram_rsp_data),
.dram_rsp_ready (dram_rsp_ready),
// Snoop request
.snp_req_valid (snp_fwd_rsp_valid),
.snp_req_addr (snp_fwd_rsp_addr),
.snp_req_inv (snp_fwd_rsp_inv),
.snp_req_tag (snp_fwd_rsp_tag),
.snp_req_ready (snp_fwd_rsp_ready),
// Snoop response
.snp_rsp_valid (snp_rsp_valid),
.snp_rsp_tag (snp_rsp_tag),
.snp_rsp_ready (snp_rsp_ready),
// Miss status
`UNUSED_PIN (miss_vec)
);
@ -344,13 +254,6 @@ module VX_cluster #(
.rsp_ready_in (dram_rsp_ready)
);
`UNUSED_VAR (snp_fwd_rsp_addr)
`UNUSED_VAR (snp_fwd_rsp_inv)
assign snp_rsp_valid = snp_fwd_rsp_valid;
assign snp_rsp_tag = snp_fwd_rsp_tag;
assign snp_fwd_rsp_ready = snp_rsp_ready;
end
endmodule

30
hw/rtl/VX_config.vh
View file

@ -323,16 +323,6 @@
`define DDRSQ_SIZE 4
`endif
// Snoop Request Queue Size
`ifndef DSREQ_SIZE
`define DSREQ_SIZE 4
`endif
// Snoop Response Queue Size
`ifndef DSRSQ_SIZE
`define DSRSQ_SIZE 4
`endif
// SM Configurable Knobs //////////////////////////////////////////////////////
// Size of cache in bytes
@ -392,16 +382,6 @@
`define L2DRSQ_SIZE 4
`endif
// Snoop Request Queue Size
`ifndef L2SREQ_SIZE
`define L2SREQ_SIZE 4
`endif
// Snoop Response Queue Size
`ifndef L2SRSQ_SIZE
`define L2SRSQ_SIZE 4
`endif
// L3cache Configurable Knobs /////////////////////////////////////////////////
// Size of cache in bytes
@ -439,14 +419,4 @@
`define L3DRSQ_SIZE 4
`endif
// Snoop Request Queue Size
`ifndef L3SREQ_SIZE
`define L3SREQ_SIZE 4
`endif
// Snoop Response Queue Size
`ifndef L3SRSQ_SIZE
`define L3SRSQ_SIZE 4
`endif
`endif

80
hw/rtl/VX_core.v
View file

@ -24,28 +24,17 @@ module VX_core #(
input wire [`XDRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// CSR request
input wire csr_req_valid,
input wire [11:0] csr_req_addr,
input wire csr_req_rw,
input wire [31:0] csr_req_data,
output wire csr_req_ready,
output wire snp_rsp_valid,
output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// CSR I/O request
input wire csr_io_req_valid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
// CSR I/O response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
// CSR response
output wire csr_rsp_valid,
output wire [31:0] csr_rsp_data,
input wire csr_rsp_ready,
// Status
output wire busy,
@ -81,27 +70,6 @@ module VX_core #(
//--
VX_cache_snp_req_if #(
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_req_if();
VX_cache_snp_rsp_if #(
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_rsp_if();
assign dcache_snp_req_if.valid = snp_req_valid;
assign dcache_snp_req_if.addr = snp_req_addr;
assign dcache_snp_req_if.invalidate = snp_req_inv;
assign dcache_snp_req_if.tag = snp_req_tag;
assign snp_req_ready = dcache_snp_req_if.ready;
assign snp_rsp_valid = dcache_snp_rsp_if.valid;
assign snp_rsp_tag = dcache_snp_rsp_if.tag;
assign dcache_snp_rsp_if.ready = snp_rsp_ready;
//--
VX_cache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
@ -135,7 +103,7 @@ module VX_core #(
) pipeline (
`SCOPE_BIND_VX_core_pipeline
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_memsys_if (perf_memsys_if),
`endif
.clk(clk),
@ -171,17 +139,17 @@ module VX_core #(
.icache_rsp_tag (core_icache_rsp_if.tag),
.icache_rsp_ready (core_icache_rsp_if.ready),
// CSR I/O request
.csr_io_req_valid (csr_io_req_valid),
.csr_io_req_rw (csr_io_req_rw),
.csr_io_req_addr (csr_io_req_addr),
.csr_io_req_data (csr_io_req_data),
.csr_io_req_ready (csr_io_req_ready),
// CSR request
.csr_req_valid (csr_req_valid),
.csr_req_rw (csr_req_rw),
.csr_req_addr (csr_req_addr),
.csr_req_data (csr_req_data),
.csr_req_ready (csr_req_ready),
// CSR I/O response
.csr_io_rsp_valid (csr_io_rsp_valid),
.csr_io_rsp_data (csr_io_rsp_data),
.csr_io_rsp_ready (csr_io_rsp_ready),
// CSR response
.csr_rsp_valid (csr_rsp_valid),
.csr_rsp_data (csr_rsp_data),
.csr_rsp_ready (csr_rsp_ready),
// Status
.busy(busy),
@ -195,7 +163,7 @@ module VX_core #(
) mem_unit (
`SCOPE_BIND_VX_core_mem_unit
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_memsys_if (perf_memsys_if),
`endif
.clk (clk),
@ -209,10 +177,6 @@ module VX_core #(
.core_icache_req_if (core_icache_req_if),
.core_icache_rsp_if (core_icache_rsp_if),
// Dcache Snoop
.dcache_snp_req_if (dcache_snp_req_if),
.dcache_snp_rsp_if (dcache_snp_rsp_if),
// DRAM
.dram_req_if (dram_req_if),
.dram_rsp_if (dram_rsp_if)

117
hw/rtl/VX_csr_arb.v
View file

@ -1,70 +1,81 @@
`include "VX_define.vh"
module VX_csr_arb (
input wire clk,
input wire reset,
module VX_csr_arb #(
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter BUFFERED_REQ = 0,
parameter BUFFERED_RSP = 0,
parameter DATA_SIZE = (DATA_WIDTH / 8),
parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [LOG_NUM_REQS-1:0] request_id,
// bus select
input wire select_io_rsp,
// input requets
VX_csr_req_if csr_core_req_if,
VX_csr_io_req_if csr_io_req_if,
// input requests
input wire req_valid_in,
input wire [ADDR_WIDTH-1:0] req_addr_in,
input wire req_rw_in,
input wire [DATA_WIDTH-1:0] req_data_in,
output wire req_ready_in,
// output request
VX_csr_pipe_req_if csr_pipe_req_if,
output wire [NUM_REQS-1:0] req_valid_out,
output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_out,
output wire [NUM_REQS-1:0] req_rw_out,
output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_out,
input wire [NUM_REQS-1:0] req_ready_out,
// input response
VX_commit_if csr_pipe_rsp_if,
input wire [NUM_REQS-1:0] rsp_valid_in,
input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in,
output wire [NUM_REQS-1:0] rsp_ready_in,
// outputs responses
VX_commit_if csr_commit_if,
VX_csr_io_rsp_if csr_io_rsp_if
// output response
output wire rsp_valid_out,
output wire [DATA_WIDTH-1:0] rsp_data_out,
input wire rsp_ready_out
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
localparam REQ_DATAW = ADDR_WIDTH + 1 + DATA_WIDTH;
localparam RSP_DATAW = DATA_WIDTH;
wire [31:0] csr_core_req_mask = csr_core_req_if.rs2_is_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_out;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign {req_addr_out[i], req_rw_out[i], req_data_out[i]} = req_merged_data_out[i];
end
// requests
assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid;
assign csr_pipe_req_if.wid = csr_core_req_if.wid;
assign csr_pipe_req_if.tmask = csr_core_req_if.tmask;
assign csr_pipe_req_if.PC = csr_core_req_if.PC;
assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_pipe_req_if.csr_addr = csr_core_req_if.valid ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
assign csr_pipe_req_if.csr_mask = csr_core_req_if.valid ? csr_core_req_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_pipe_req_if.rd = csr_core_req_if.rd;
assign csr_pipe_req_if.wb = csr_core_req_if.wb;
assign csr_pipe_req_if.is_io = !csr_core_req_if.valid;
// core always takes priority over IO bus
assign csr_core_req_if.ready = csr_pipe_req_if.ready;
assign csr_io_req_if.ready = csr_pipe_req_if.ready && !csr_core_req_if.valid;
// responses
wire csr_io_rsp_ready;
VX_skid_buffer #(
.DATAW (32)
) csr_io_out_buffer (
VX_stream_demux #(
.NUM_REQS (NUM_REQS),
.DATAW (REQ_DATAW),
.BUFFERED (BUFFERED_REQ)
) req_demux (
.clk (clk),
.reset (reset),
.valid_in (csr_pipe_rsp_if.valid & select_io_rsp),
.data_in (csr_pipe_rsp_if.data[0]),
.ready_in (csr_io_rsp_ready),
.valid_out (csr_io_rsp_if.valid),
.data_out (csr_io_rsp_if.data),
.ready_out (csr_io_rsp_if.ready)
.sel (request_id),
.valid_in (req_valid_in),
.data_in ({req_addr_in, req_rw_in, req_data_in}),
.ready_in (req_ready_in),
.valid_out (req_valid_out),
.data_out (req_merged_data_out),
.ready_out (req_ready_out)
);
assign csr_commit_if.valid = csr_pipe_rsp_if.valid & ~select_io_rsp;
assign csr_commit_if.wid = csr_pipe_rsp_if.wid;
assign csr_commit_if.tmask = csr_pipe_rsp_if.tmask;
assign csr_commit_if.PC = csr_pipe_rsp_if.PC;
assign csr_commit_if.rd = csr_pipe_rsp_if.rd;
assign csr_commit_if.wb = csr_pipe_rsp_if.wb;
assign csr_commit_if.data = csr_pipe_rsp_if.data;
assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_ready : csr_commit_if.ready;
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in),
.data_in (rsp_data_in),
.ready_in (rsp_ready_in),
.valid_out (rsp_valid_out),
.data_out (rsp_data_out),
.ready_out (rsp_ready_out)
);
endmodule

117
hw/rtl/VX_csr_io_arb.v
View file

@ -1,81 +1,70 @@
`include "VX_define.vh"
module VX_csr_io_arb #(
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter BUFFERED_REQ = 0,
parameter BUFFERED_RSP = 0,
parameter DATA_SIZE = (DATA_WIDTH / 8),
parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [LOG_NUM_REQS-1:0] request_id,
module VX_csr_io_arb (
input wire clk,
input wire reset,
// input requests
input wire req_valid_in,
input wire [ADDR_WIDTH-1:0] req_addr_in,
input wire req_rw_in,
input wire [DATA_WIDTH-1:0] req_data_in,
output wire req_ready_in,
// bus select
input wire select_io_rsp,
// input requets
VX_csr_req_if csr_core_req_if,
VX_csr_io_req_if csr_io_req_if,
// output request
output wire [NUM_REQS-1:0] req_valid_out,
output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_out,
output wire [NUM_REQS-1:0] req_rw_out,
output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_out,
input wire [NUM_REQS-1:0] req_ready_out,
VX_csr_pipe_req_if csr_pipe_req_if,
// input response
input wire [NUM_REQS-1:0] rsp_valid_in,
input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in,
output wire [NUM_REQS-1:0] rsp_ready_in,
VX_commit_if csr_pipe_rsp_if,
// output response
output wire rsp_valid_out,
output wire [DATA_WIDTH-1:0] rsp_data_out,
input wire rsp_ready_out
// outputs responses
VX_commit_if csr_commit_if,
VX_csr_io_rsp_if csr_io_rsp_if
);
localparam REQ_DATAW = ADDR_WIDTH + 1 + DATA_WIDTH;
localparam RSP_DATAW = DATA_WIDTH;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_out;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign {req_addr_out[i], req_rw_out[i], req_data_out[i]} = req_merged_data_out[i];
end
wire [31:0] csr_core_req_mask = csr_core_req_if.rs2_is_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
VX_stream_demux #(
.NUM_REQS (NUM_REQS),
.DATAW (REQ_DATAW),
.BUFFERED (BUFFERED_REQ)
) req_demux (
// requests
assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid;
assign csr_pipe_req_if.wid = csr_core_req_if.wid;
assign csr_pipe_req_if.tmask = csr_core_req_if.tmask;
assign csr_pipe_req_if.PC = csr_core_req_if.PC;
assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_pipe_req_if.csr_addr = csr_core_req_if.valid ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
assign csr_pipe_req_if.csr_mask = csr_core_req_if.valid ? csr_core_req_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_pipe_req_if.rd = csr_core_req_if.rd;
assign csr_pipe_req_if.wb = csr_core_req_if.wb;
assign csr_pipe_req_if.is_io = !csr_core_req_if.valid;
// core always takes priority over IO bus
assign csr_core_req_if.ready = csr_pipe_req_if.ready;
assign csr_io_req_if.ready = csr_pipe_req_if.ready && !csr_core_req_if.valid;
// responses
wire csr_io_rsp_ready;
VX_skid_buffer #(
.DATAW (32)
) csr_io_out_buffer (
.clk (clk),
.reset (reset),
.sel (request_id),
.valid_in (req_valid_in),
.data_in ({req_addr_in, req_rw_in, req_data_in}),
.ready_in (req_ready_in),
.valid_out (req_valid_out),
.data_out (req_merged_data_out),
.ready_out (req_ready_out)
.valid_in (csr_pipe_rsp_if.valid & select_io_rsp),
.data_in (csr_pipe_rsp_if.data[0]),
.ready_in (csr_io_rsp_ready),
.valid_out (csr_io_rsp_if.valid),
.data_out (csr_io_rsp_if.data),
.ready_out (csr_io_rsp_if.ready)
);
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in),
.data_in (rsp_data_in),
.ready_in (rsp_ready_in),
.valid_out (rsp_valid_out),
.data_out (rsp_data_out),
.ready_out (rsp_ready_out)
);
assign csr_commit_if.valid = csr_pipe_rsp_if.valid & ~select_io_rsp;
assign csr_commit_if.wid = csr_pipe_rsp_if.wid;
assign csr_commit_if.tmask = csr_pipe_rsp_if.tmask;
assign csr_commit_if.PC = csr_pipe_rsp_if.PC;
assign csr_commit_if.rd = csr_pipe_rsp_if.rd;
assign csr_commit_if.wb = csr_pipe_rsp_if.wb;
assign csr_commit_if.data = csr_pipe_rsp_if.data;
assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_ready : csr_commit_if.ready;
endmodule

2
hw/rtl/VX_csr_unit.v
View file

@ -29,7 +29,7 @@ module VX_csr_unit #(
wire select_io_rsp;
VX_csr_arb csr_arb (
VX_csr_io_arb csr_io_arb (
.clk (clk),
.reset (reset),

10
hw/rtl/VX_define.vh
View file

@ -313,9 +313,6 @@
// Core request size
`define DNUM_REQUESTS `NUM_THREADS
// Snoop request tag bits
`define DSNP_TAG_WIDTH ((`NUM_CORES > 1) ? `LOG2UP(`L2SREQ_SIZE) : `L2SNP_TAG_WIDTH)
////////////////////////// SM Configurable Knobs //////////////////////////////
// Cache ID
@ -365,9 +362,6 @@
// DRAM request tag bits
`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`XDRAM_TAG_WIDTH+`CLOG2(`NUM_CORES)))
// Snoop request tag bits
`define L2SNP_TAG_WIDTH ((`NUM_CLUSTERS > 1) ? `LOG2UP(`L3SREQ_SIZE) : `L3SNP_TAG_WIDTH)
////////////////////////// L3cache Configurable Knobs /////////////////////////
// Cache ID
@ -394,16 +388,12 @@
// DRAM request tag bits
`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : (`L2DRAM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS)))
// Snoop request tag bits
`define L3SNP_TAG_WIDTH `VX_SNP_TAG_WIDTH
///////////////////////////////////////////////////////////////////////////////
`define VX_DRAM_BYTEEN_WIDTH `L3DRAM_BYTEEN_WIDTH
`define VX_DRAM_ADDR_WIDTH `L3DRAM_ADDR_WIDTH
`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH
`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
`define VX_SNP_TAG_WIDTH 16
`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)

54
hw/rtl/VX_mem_unit.v
View file

@ -20,10 +20,6 @@ module VX_mem_unit # (
VX_cache_core_req_if core_icache_req_if,
VX_cache_core_rsp_if core_icache_rsp_if,
// Dcache Snoop
VX_cache_snp_req_if dcache_snp_req_if,
VX_cache_snp_rsp_if dcache_snp_rsp_if,
// DRAM
VX_cache_dram_req_if dram_req_if,
VX_cache_dram_rsp_if dram_rsp_if
@ -95,12 +91,9 @@ module VX_mem_unit # (
.CREQ_SIZE (`ICREQ_SIZE),
.MSHR_SIZE (`IMSHR_SIZE),
.DRSQ_SIZE (`IDRSQ_SIZE),
.SREQ_SIZE (1),
.CRSQ_SIZE (`ICRSQ_SIZE),
.DREQ_SIZE (`IDREQ_SIZE),
.SRSQ_SIZE (1),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (0),
.CORE_TAG_WIDTH (`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
@ -145,18 +138,6 @@ module VX_mem_unit # (
.dram_rsp_tag (icache_dram_rsp_if.tag),
.dram_rsp_ready (icache_dram_rsp_if.ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_inv (1'b0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
// Miss status
`UNUSED_PIN (miss_vec)
);
@ -171,17 +152,13 @@ module VX_mem_unit # (
.CREQ_SIZE (`DCREQ_SIZE),
.MSHR_SIZE (`DMSHR_SIZE),
.DRSQ_SIZE (`DDRSQ_SIZE),
.SREQ_SIZE (`DSREQ_SIZE),
.CRSQ_SIZE (`DCRSQ_SIZE),
.DREQ_SIZE (`DDREQ_SIZE),
.SRSQ_SIZE (`DSRSQ_SIZE),
.DREQ_SIZE (`DDREQ_SIZE),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_TAG_WIDTH (`DSNP_TAG_WIDTH)
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH)
) dcache (
`SCOPE_BIND_VX_mem_unit_dcache
@ -222,18 +199,6 @@ module VX_mem_unit # (
.dram_rsp_tag (dcache_dram_rsp_if.tag),
.dram_rsp_ready (dcache_dram_rsp_if.ready),
// Snoop request
.snp_req_valid (dcache_snp_req_if.valid),
.snp_req_addr (dcache_snp_req_if.addr),
.snp_req_inv (dcache_snp_req_if.invalidate),
.snp_req_tag (dcache_snp_req_if.tag),
.snp_req_ready (dcache_snp_req_if.ready),
// Snoop response
.snp_rsp_valid (dcache_snp_rsp_if.valid),
.snp_rsp_tag (dcache_snp_rsp_if.tag),
.snp_rsp_ready (dcache_snp_rsp_if.ready),
// Miss status
`UNUSED_PIN (miss_vec)
);
@ -250,12 +215,9 @@ module VX_mem_unit # (
.CREQ_SIZE (`SCREQ_SIZE),
.MSHR_SIZE (8),
.DRSQ_SIZE (1),
.SREQ_SIZE (1),
.CRSQ_SIZE (`SCRSQ_SIZE),
.DREQ_SIZE (1),
.SRSQ_SIZE (1),
.DRAM_ENABLE (0),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
@ -300,18 +262,6 @@ module VX_mem_unit # (
.dram_rsp_tag (0),
`UNUSED_PIN (dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_inv (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
// Miss status
`UNUSED_PIN (miss_vec)
);

34
hw/rtl/VX_pipeline.v
View file

@ -40,16 +40,16 @@ module VX_pipeline #(
output wire icache_rsp_ready,
// CSR I/O Request
input wire csr_io_req_valid,
input wire[11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire[31:0] csr_io_req_data,
output wire csr_io_req_ready,
input wire csr_req_valid,
input wire[11:0] csr_req_addr,
input wire csr_req_rw,
input wire[31:0] csr_req_data,
output wire csr_req_ready,
// CSR I/O Response
output wire csr_io_rsp_valid,
output wire[31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
output wire csr_rsp_valid,
output wire[31:0] csr_rsp_data,
input wire csr_rsp_ready,
`ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if,
@ -134,22 +134,20 @@ module VX_pipeline #(
//
VX_csr_io_req_if csr_io_req_if();
assign csr_io_req_if.valid = csr_io_req_valid;
assign csr_io_req_if.rw = csr_io_req_rw;
assign csr_io_req_if.addr = csr_io_req_addr;
assign csr_io_req_if.data = csr_io_req_data;
assign csr_io_req_ready = csr_io_req_if.ready;
assign csr_io_req_if.valid = csr_req_valid;
assign csr_io_req_if.rw = csr_req_rw;
assign csr_io_req_if.addr = csr_req_addr;
assign csr_io_req_if.data = csr_req_data;
assign csr_req_ready = csr_io_req_if.ready;
//
// CSR IO response
//
VX_csr_io_rsp_if csr_io_rsp_if();
assign csr_io_rsp_valid = csr_io_rsp_if.valid;
assign csr_io_rsp_data = csr_io_rsp_if.data;
assign csr_io_rsp_if.ready = csr_io_rsp_ready;
assign csr_rsp_valid = csr_io_rsp_if.valid;
assign csr_rsp_data = csr_io_rsp_if.data;
assign csr_io_rsp_if.ready = csr_rsp_ready;
///////////////////////////////////////////////////////////////////////////

231
hw/rtl/Vortex.v
View file

@ -22,30 +22,18 @@ module Vortex (
input wire [`VX_DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [`VX_SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [`VX_SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// CSR Request
input wire csr_io_req_valid,
input wire [`VX_CSR_ID_WIDTH-1:0] csr_io_req_coreid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
input wire csr_req_valid,
input wire [`VX_CSR_ID_WIDTH-1:0] csr_req_coreid,
input wire [11:0] csr_req_addr,
input wire csr_req_rw,
input wire [31:0] csr_req_data,
output wire csr_req_ready,
// CSR Response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
output wire csr_rsp_valid,
output wire [31:0] csr_rsp_data,
input wire csr_rsp_ready,
// Status
output wire busy,
@ -64,31 +52,21 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr;
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_inv;
wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_req_valid;
wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_req_addr;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_req_rw;
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_req_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid;
wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid;
wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw;
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid;
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_rsp_valid;
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_rsp_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak;
wire [`LOG2UP(`NUM_CLUSTERS)-1:0] csr_io_cluster_id = `LOG2UP(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CORES));
wire [`NC_BITS-1:0] csr_io_core_id = `NC_BITS'(csr_io_req_coreid);
wire [`LOG2UP(`NUM_CLUSTERS)-1:0] csr_cluster_id = `LOG2UP(`NUM_CLUSTERS)'(csr_req_coreid >> `CLOG2(`NUM_CORES));
wire [`NC_BITS-1:0] csr_core_id = `NC_BITS'(csr_req_coreid);
for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
VX_cluster #(
@ -96,130 +74,78 @@ module Vortex (
) cluster (
`SCOPE_BIND_Vortex_cluster(i)
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
.dram_req_valid (per_cluster_dram_req_valid [i]),
.dram_req_rw (per_cluster_dram_req_rw [i]),
.dram_req_byteen (per_cluster_dram_req_byteen[i]),
.dram_req_addr (per_cluster_dram_req_addr [i]),
.dram_req_data (per_cluster_dram_req_data [i]),
.dram_req_tag (per_cluster_dram_req_tag [i]),
.dram_req_ready (per_cluster_dram_req_ready [i]),
.dram_req_valid (per_cluster_dram_req_valid [i]),
.dram_req_rw (per_cluster_dram_req_rw [i]),
.dram_req_byteen(per_cluster_dram_req_byteen[i]),
.dram_req_addr (per_cluster_dram_req_addr [i]),
.dram_req_data (per_cluster_dram_req_data [i]),
.dram_req_tag (per_cluster_dram_req_tag [i]),
.dram_req_ready (per_cluster_dram_req_ready [i]),
.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
.dram_rsp_data (per_cluster_dram_rsp_data [i]),
.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
.dram_rsp_data (per_cluster_dram_rsp_data [i]),
.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
.snp_req_valid (per_cluster_snp_req_valid [i]),
.snp_req_addr (per_cluster_snp_req_addr [i]),
.snp_req_inv (per_cluster_snp_req_inv [i]),
.snp_req_tag (per_cluster_snp_req_tag [i]),
.snp_req_ready (per_cluster_snp_req_ready [i]),
.csr_req_valid (per_cluster_csr_req_valid [i]),
.csr_req_coreid (csr_core_id),
.csr_req_rw (per_cluster_csr_req_rw [i]),
.csr_req_addr (per_cluster_csr_req_addr [i]),
.csr_req_data (per_cluster_csr_req_data [i]),
.csr_req_ready (per_cluster_csr_req_ready [i]),
.snp_rsp_valid (per_cluster_snp_rsp_valid [i]),
.snp_rsp_tag (per_cluster_snp_rsp_tag [i]),
.snp_rsp_ready (per_cluster_snp_rsp_ready [i]),
.csr_rsp_valid (per_cluster_csr_rsp_valid [i]),
.csr_rsp_data (per_cluster_csr_rsp_data [i]),
.csr_rsp_ready (per_cluster_csr_rsp_ready [i]),
.csr_io_req_valid (per_cluster_csr_io_req_valid[i]),
.csr_io_req_coreid (csr_io_core_id),
.csr_io_req_rw (per_cluster_csr_io_req_rw [i]),
.csr_io_req_addr (per_cluster_csr_io_req_addr[i]),
.csr_io_req_data (per_cluster_csr_io_req_data[i]),
.csr_io_req_ready (per_cluster_csr_io_req_ready[i]),
.csr_io_rsp_valid (per_cluster_csr_io_rsp_valid[i]),
.csr_io_rsp_data (per_cluster_csr_io_rsp_data[i]),
.csr_io_rsp_ready (per_cluster_csr_io_rsp_ready[i]),
.busy (per_cluster_busy [i]),
.ebreak (per_cluster_ebreak [i])
.busy (per_cluster_busy [i]),
.ebreak (per_cluster_ebreak [i])
);
end
VX_csr_io_arb #(
VX_csr_arb #(
.NUM_REQS (`NUM_CLUSTERS),
.DATA_WIDTH (32),
.ADDR_WIDTH (12),
.BUFFERED_REQ (`NUM_CLUSTERS >= 4),
.BUFFERED_RSP (1)
) csr_io_arb (
) csr_arb (
.clk (clk),
.reset (reset),
.request_id (csr_io_cluster_id),
.request_id (csr_cluster_id),
// input requests
.req_valid_in (csr_io_req_valid),
.req_addr_in (csr_io_req_addr),
.req_rw_in (csr_io_req_rw),
.req_data_in (csr_io_req_data),
.req_ready_in (csr_io_req_ready),
.req_valid_in (csr_req_valid),
.req_addr_in (csr_req_addr),
.req_rw_in (csr_req_rw),
.req_data_in (csr_req_data),
.req_ready_in (csr_req_ready),
// output request
.req_valid_out (per_cluster_csr_io_req_valid),
.req_addr_out (per_cluster_csr_io_req_addr),
.req_rw_out (per_cluster_csr_io_req_rw),
.req_data_out (per_cluster_csr_io_req_data),
.req_ready_out (per_cluster_csr_io_req_ready),
.req_valid_out (per_cluster_csr_req_valid),
.req_addr_out (per_cluster_csr_req_addr),
.req_rw_out (per_cluster_csr_req_rw),
.req_data_out (per_cluster_csr_req_data),
.req_ready_out (per_cluster_csr_req_ready),
// input responses
.rsp_valid_in (per_cluster_csr_io_rsp_valid),
.rsp_data_in (per_cluster_csr_io_rsp_data),
.rsp_ready_in (per_cluster_csr_io_rsp_ready),
.rsp_valid_in (per_cluster_csr_rsp_valid),
.rsp_data_in (per_cluster_csr_rsp_data),
.rsp_ready_in (per_cluster_csr_rsp_ready),
// output response
.rsp_valid_out (csr_io_rsp_valid),
.rsp_data_out (csr_io_rsp_data),
.rsp_ready_out (csr_io_rsp_ready)
.rsp_valid_out (csr_rsp_valid),
.rsp_data_out (csr_rsp_data),
.rsp_ready_out (csr_rsp_ready)
);
assign busy = (| per_cluster_busy);
assign ebreak = (| per_cluster_ebreak);
wire snp_fwd_rsp_valid;
wire [`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L3SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
VX_snp_forwarder #(
.CACHE_ID (`L3CACHE_ID),
.NUM_REQS (`NUM_CLUSTERS),
.SRC_ADDR_WIDTH (`L3DRAM_ADDR_WIDTH),
.DST_ADDR_WIDTH (`L2DRAM_ADDR_WIDTH),
.TAG_IN_WIDTH (`L3SNP_TAG_WIDTH),
.TAG_OUT_WIDTH (`L2SNP_TAG_WIDTH),
.SREQ_SIZE (`L3SREQ_SIZE),
.BUFFERED (`NUM_CLUSTERS >= 4)
) snp_forwarder (
.clk (clk),
.reset (reset),
.snp_req_valid (snp_req_valid),
.snp_req_addr (snp_req_addr),
.snp_req_inv (snp_req_inv),
.snp_req_tag (snp_req_tag),
.snp_req_ready (snp_req_ready),
.snp_rsp_valid (snp_fwd_rsp_valid),
.snp_rsp_addr (snp_fwd_rsp_addr),
.snp_rsp_inv (snp_fwd_rsp_inv),
.snp_rsp_tag (snp_fwd_rsp_tag),
.snp_rsp_ready (snp_fwd_rsp_ready),
.snp_fwdout_valid (per_cluster_snp_req_valid),
.snp_fwdout_addr (per_cluster_snp_req_addr),
.snp_fwdout_inv (per_cluster_snp_req_inv),
.snp_fwdout_tag (per_cluster_snp_req_tag),
.snp_fwdout_ready (per_cluster_snp_req_ready),
.snp_fwdin_valid (per_cluster_snp_rsp_valid),
.snp_fwdin_tag (per_cluster_snp_rsp_tag),
.snp_fwdin_ready (per_cluster_snp_rsp_ready)
);
if (`L3_ENABLE) begin
`ifdef PERF_ENABLE
VX_perf_cache_if perf_l3cache_if();
@ -235,17 +161,13 @@ module Vortex (
.CREQ_SIZE (`L3CREQ_SIZE),
.MSHR_SIZE (`L3MSHR_SIZE),
.DRSQ_SIZE (`L3DRSQ_SIZE),
.SREQ_SIZE (`L3SREQ_SIZE),
.CRSQ_SIZE (`L3CRSQ_SIZE),
.DREQ_SIZE (`L3DREQ_SIZE),
.SRSQ_SIZE (`L3SRSQ_SIZE),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH),
.SNP_TAG_WIDTH (`L3SNP_TAG_WIDTH)
.DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH)
) l3cache (
`SCOPE_BIND_Vortex_l3cache
@ -286,18 +208,6 @@ module Vortex (
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_ready (dram_rsp_ready),
// Snoop request
.snp_req_valid (snp_fwd_rsp_valid),
.snp_req_addr (snp_fwd_rsp_addr),
.snp_req_inv (snp_fwd_rsp_inv),
.snp_req_tag (snp_fwd_rsp_tag),
.snp_req_ready (snp_fwd_rsp_ready),
// Snoop response
.snp_rsp_valid (snp_rsp_valid),
.snp_rsp_tag (snp_rsp_tag),
.snp_rsp_ready (snp_rsp_ready),
// Miss status
`UNUSED_PIN (miss_vec)
);
@ -346,13 +256,6 @@ module Vortex (
.rsp_ready_in (dram_rsp_ready)
);
`UNUSED_VAR (snp_fwd_rsp_addr)
`UNUSED_VAR (snp_fwd_rsp_inv)
assign snp_rsp_valid = snp_fwd_rsp_valid;
assign snp_rsp_tag = snp_fwd_rsp_tag;
assign snp_fwd_rsp_ready = snp_rsp_ready;
end
`SCOPE_ASSIGN (reset, reset);
@ -366,14 +269,6 @@ module Vortex (
`SCOPE_ASSIGN (dram_rsp_fire, dram_rsp_valid && dram_rsp_ready);
`SCOPE_ASSIGN (dram_rsp_data, dram_rsp_data);
`SCOPE_ASSIGN (dram_rsp_tag, dram_rsp_tag);
`SCOPE_ASSIGN (snp_req_fire, snp_req_valid && snp_req_ready);
`SCOPE_ASSIGN (snp_req_addr, `TO_FULL_ADDR(snp_req_addr));
`SCOPE_ASSIGN (snp_req_inv, snp_req_inv);
`SCOPE_ASSIGN (snp_req_tag, snp_req_tag);
`SCOPE_ASSIGN (snp_rsp_fire, snp_rsp_valid && snp_rsp_ready);
`SCOPE_ASSIGN (snp_rsp_tag, snp_rsp_tag);
`SCOPE_ASSIGN (snp_rsp_fire, snp_rsp_valid && snp_rsp_ready);
`SCOPE_ASSIGN (snp_rsp_tag, snp_rsp_tag);
`SCOPE_ASSIGN (busy, busy);
`ifdef DBG_PRINT_DRAM

176
hw/rtl/afu/vortex_afu.sv
View file

@ -57,7 +57,6 @@ localparam AFU_ID_H = 16'h0004; // AFU ID Higher
localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ;
localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE;
localparam CMD_RUN = `AFU_IMAGE_CMD_RUN;
localparam CMD_CLFLUSH = `AFU_IMAGE_CMD_CLFLUSH;
localparam CMD_CSR_READ = `AFU_IMAGE_CMD_CSR_READ;
localparam CMD_CSR_WRITE = `AFU_IMAGE_CMD_CSR_WRITE;
@ -83,10 +82,9 @@ localparam STATE_READ = 1;
localparam STATE_WRITE = 2;
localparam STATE_START = 3;
localparam STATE_RUN = 4;
localparam STATE_CLFLUSH = 5;
localparam STATE_CSR_READ = 6;
localparam STATE_CSR_WRITE = 7;
localparam STATE_MAX_VALUE = 8;
localparam STATE_CSR_READ = 5;
localparam STATE_CSR_WRITE = 6;
localparam STATE_MAX_VALUE = 7;
localparam STATE_WIDTH = $clog2(STATE_MAX_VALUE);
`ifdef SCOPE
@ -112,18 +110,6 @@ wire [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data;
wire [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_rsp_tag;
wire vx_dram_rsp_ready;
reg vx_snp_req_valid;
reg [`VX_DRAM_ADDR_WIDTH-1:0] vx_snp_req_addr;
wire vx_snp_req_inv = 0;
wire [`VX_SNP_TAG_WIDTH-1:0] vx_snp_req_tag;
wire vx_snp_req_ready;
wire vx_snp_rsp_valid;
`DEBUG_BEGIN
wire [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag;
`DEBUG_END
reg vx_snp_rsp_ready;
wire vx_csr_io_req_valid;
wire [`VX_CSR_ID_WIDTH-1:0] vx_csr_io_req_coreid;
wire [11:0] vx_csr_io_req_addr;
@ -335,7 +321,6 @@ end
wire cmd_read_done;
wire cmd_write_done;
wire cmd_clflush_done;
wire cmd_csr_done;
wire cmd_run_done;
@ -371,12 +356,6 @@ always @(posedge clk) begin
vx_enabled <= 1;
state <= STATE_START;
end
CMD_CLFLUSH: begin
`ifdef DBG_PRINT_OPAE
$display("%t: STATE CFLUSH: addr=%0h size=%0d", $time, cmd_mem_addr, cmd_data_size);
`endif
state <= STATE_CLFLUSH;
end
CMD_CSR_READ: begin
`ifdef DBG_PRINT_OPAE
$display("%t: STATE CSR_READ: addr=%0h", $time, cmd_csr_addr);
@ -426,15 +405,6 @@ always @(posedge clk) begin
end
end
STATE_CLFLUSH: begin
if (cmd_clflush_done) begin
state <= STATE_IDLE;
`ifdef DBG_PRINT_OPAE
$display("%t: STATE IDLE", $time);
`endif
end
end
STATE_CSR_READ: begin
if (cmd_csr_done) begin
state <= STATE_IDLE;
@ -854,80 +824,6 @@ begin
end
end
// Vortex cache snooping //////////////////////////////////////////////////////
wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_size;
wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_baseaddr;
reg [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_ctr, snp_rsp_ctr;
wire [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_ctr_next, snp_rsp_ctr_next;
wire vx_snp_req_fire, vx_snp_rsp_fire;
if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
assign snp_req_baseaddr = {cmd_mem_addr, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)};
assign snp_req_size = {cmd_data_size, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)};
end else begin
assign snp_req_baseaddr = cmd_mem_addr;
assign snp_req_size = cmd_data_size;
end
assign vx_snp_req_tag = (`VX_SNP_TAG_WIDTH)'(snp_req_ctr);
assign vx_snp_req_fire = vx_snp_req_valid && vx_snp_req_ready;
assign vx_snp_rsp_fire = vx_snp_rsp_valid && vx_snp_rsp_ready;
assign snp_req_ctr_next = vx_snp_req_fire ? (snp_req_ctr + `VX_DRAM_ADDR_WIDTH'(1)) : snp_req_ctr;
assign snp_rsp_ctr_next = vx_snp_rsp_fire ? (snp_rsp_ctr - `VX_DRAM_ADDR_WIDTH'(1)) : snp_rsp_ctr;
assign cmd_clflush_done = (0 == snp_rsp_ctr);
always @(posedge clk) begin
if (reset) begin
vx_snp_req_valid <= 0;
vx_snp_req_addr <= 0;
vx_snp_rsp_ready <= 0;
snp_req_ctr <= 0;
snp_rsp_ctr <= 0;
end else begin
if ((STATE_IDLE == state)
&& (CMD_CLFLUSH == cmd_type)) begin
vx_snp_req_valid <= (snp_req_size != 0);
vx_snp_req_addr <= snp_req_baseaddr;
vx_snp_rsp_ready <= (snp_req_size != 0);
snp_req_ctr <= 0;
snp_rsp_ctr <= snp_req_size;
end
if ((STATE_CLFLUSH == state)
&& (snp_req_ctr_next == snp_req_size)) begin
vx_snp_req_valid <= 0;
end
if ((STATE_CLFLUSH == state)
&& (0 == snp_rsp_ctr_next)) begin
vx_snp_rsp_ready <= 0;
end
if (vx_snp_req_fire) begin
assert(snp_req_ctr < snp_req_size);
vx_snp_req_addr <= vx_snp_req_addr + `VX_DRAM_ADDR_WIDTH'(1);
snp_req_ctr <= snp_req_ctr_next;
`ifdef DBG_PRINT_OPAE
$display("%t: AFU Snp Req: addr=%0h, tag=%0h, rem=%0d", $time, `TO_FULL_ADDR(vx_snp_req_addr), (`VX_SNP_TAG_WIDTH)'(vx_snp_req_tag), (snp_req_size - snp_req_ctr_next));
`endif
end
if ((STATE_CLFLUSH == state)
&& vx_snp_rsp_fire) begin
assert(snp_rsp_ctr != 0);
snp_rsp_ctr <= snp_rsp_ctr_next;
`ifdef DBG_PRINT_OPAE
$display("%t: AFU Snp Rsp: tag=%0h, rem=%0d", $time, vx_snp_rsp_tag, snp_rsp_ctr_next);
`endif
end
end
end
// CSRs ///////////////////////////////////////////////////////////////////////
reg csr_io_req_sent;
@ -969,52 +865,40 @@ assign cmd_run_done = !vx_busy;
Vortex #() vortex (
`SCOPE_BIND_afu_vortex
.clk (clk),
.reset (reset | vx_reset),
.clk (clk),
.reset (reset | vx_reset),
// DRAM request
.dram_req_valid (vx_dram_req_valid),
.dram_req_rw (vx_dram_req_rw),
.dram_req_byteen (vx_dram_req_byteen),
.dram_req_addr (vx_dram_req_addr),
.dram_req_data (vx_dram_req_data),
.dram_req_tag (vx_dram_req_tag),
.dram_req_ready (vx_dram_req_ready),
.dram_req_valid (vx_dram_req_valid),
.dram_req_rw (vx_dram_req_rw),
.dram_req_byteen(vx_dram_req_byteen),
.dram_req_addr (vx_dram_req_addr),
.dram_req_data (vx_dram_req_data),
.dram_req_tag (vx_dram_req_tag),
.dram_req_ready (vx_dram_req_ready),
// DRAM response
.dram_rsp_valid (vx_dram_rsp_valid),
.dram_rsp_data (vx_dram_rsp_data),
.dram_rsp_tag (vx_dram_rsp_tag),
.dram_rsp_ready (vx_dram_rsp_ready),
.dram_rsp_valid (vx_dram_rsp_valid),
.dram_rsp_data (vx_dram_rsp_data),
.dram_rsp_tag (vx_dram_rsp_tag),
.dram_rsp_ready (vx_dram_rsp_ready),
// Snoop request
.snp_req_valid (vx_snp_req_valid),
.snp_req_addr (vx_snp_req_addr),
.snp_req_inv (vx_snp_req_inv),
.snp_req_tag (vx_snp_req_tag),
.snp_req_ready (vx_snp_req_ready),
// CSR Request
.csr_req_valid (vx_csr_io_req_valid),
.csr_req_coreid (vx_csr_io_req_coreid),
.csr_req_addr (vx_csr_io_req_addr),
.csr_req_rw (vx_csr_io_req_rw),
.csr_req_data (vx_csr_io_req_data),
.csr_req_ready (vx_csr_io_req_ready),
// Snoop response
.snp_rsp_valid (vx_snp_rsp_valid),
.snp_rsp_tag (vx_snp_rsp_tag),
.snp_rsp_ready (vx_snp_rsp_ready),
// CSR I/O Request
.csr_io_req_valid (vx_csr_io_req_valid),
.csr_io_req_coreid(vx_csr_io_req_coreid),
.csr_io_req_addr (vx_csr_io_req_addr),
.csr_io_req_rw (vx_csr_io_req_rw),
.csr_io_req_data (vx_csr_io_req_data),
.csr_io_req_ready (vx_csr_io_req_ready),
// CSR I/O Response
.csr_io_rsp_valid (vx_csr_io_rsp_valid),
.csr_io_rsp_data (vx_csr_io_rsp_data),
.csr_io_rsp_ready (vx_csr_io_rsp_ready),
// CSR Response
.csr_rsp_valid (vx_csr_io_rsp_valid),
.csr_rsp_data (vx_csr_io_rsp_data),
.csr_rsp_ready (vx_csr_io_rsp_ready),
// status
.busy (vx_busy),
`UNUSED_PIN (ebreak)
.busy (vx_busy),
`UNUSED_PIN (ebreak)
);
// SCOPE //////////////////////////////////////////////////////////////////////
@ -1049,8 +933,6 @@ Vortex #() vortex (
`SCOPE_ASSIGN (ccip_rd_req_ctr, cci_rd_req_ctr);
`SCOPE_ASSIGN (ccip_rd_rsp_ctr, cci_rd_rsp_ctr);
`SCOPE_ASSIGN (ccip_wr_req_ctr, cci_wr_req_ctr);
`SCOPE_ASSIGN (snp_req_ctr, snp_req_ctr);
`SCOPE_ASSIGN (snp_rsp_ctr, snp_rsp_ctr);
wire scope_changed = `SCOPE_TRIGGER;

5
hw/rtl/afu/vortex_afu.vh
View file

@ -13,9 +13,8 @@
`define AFU_ACCEL_NAME "vortex_afu"
`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c
`define AFU_IMAGE_CMD_CLFLUSH 4
`define AFU_IMAGE_CMD_CSR_READ 5
`define AFU_IMAGE_CMD_CSR_WRITE 6
`define AFU_IMAGE_CMD_CSR_READ 4
`define AFU_IMAGE_CMD_CSR_WRITE 5
`define AFU_IMAGE_CMD_MEM_READ 1
`define AFU_IMAGE_CMD_MEM_WRITE 2
`define AFU_IMAGE_CMD_RUN 3

249
hw/rtl/cache/VX_bank.v vendored
View file

@ -21,33 +21,26 @@ module VX_bank #(
parameter MSHR_SIZE = 1,
// DRAM Response Queue Size
parameter DRSQ_SIZE = 1,
// Snoop Request Queue Size
parameter SREQ_SIZE = 1,
// Core Response Queue Size
parameter CRSQ_SIZE = 1,
// DRAM Request Queue Size
parameter DREQ_SIZE = 1,
// Snoop Response Size
parameter SRSQ_SIZE = 1,
// Enable cache writeable
parameter WRITE_ENABLE = 0,
// Enable dram update
parameter DRAM_ENABLE = 0,
// Enable cache flush
parameter FLUSH_ENABLE = 0,
parameter DRAM_ENABLE = 1,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
// Enable write-through
parameter WRITE_THROUGH = 1,
// core request tag size
parameter CORE_TAG_WIDTH = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0,
// Snooping request tag width
parameter SNP_TAG_WIDTH = 1
parameter CORE_TAG_ID_BITS = 0
) (
`SCOPE_IO_VX_bank
@ -85,18 +78,6 @@ module VX_bank #(
input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
output wire dram_rsp_ready,
// Snoop Request
input wire snp_req_valid,
input wire [`LINE_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop Response
output wire snp_rsp_valid,
output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
`ifdef PERF_ENABLE
output wire perf_read_misses,
output wire perf_write_misses,
@ -107,8 +88,6 @@ module VX_bank #(
// Misses
output wire misses
);
`STATIC_ASSERT (!FLUSH_ENABLE || DRAM_ENABLE, ("invalid parameter"))
`ifdef DBG_CACHE_REQ_INFO
/* verilator lint_off UNUSED */
wire [31:0] debug_pc_st0;
@ -133,48 +112,6 @@ module VX_bank #(
/* verilator lint_on UNUSED */
`endif
wire sreq_pop;
wire sreq_empty;
wire [`LINE_ADDR_WIDTH-1:0] sreq_addr_st0;
wire sreq_inv_st0;
wire [SNP_TAG_WIDTH-1:0] sreq_tag_st0;
if (FLUSH_ENABLE) begin
wire sreq_full;
assign snp_req_ready = !sreq_full;
wire sreq_push = snp_req_valid && snp_req_ready;
VX_generic_queue #(
.DATAW (`LINE_ADDR_WIDTH + 1 + SNP_TAG_WIDTH),
.SIZE (SREQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) snp_req_queue (
.clk (clk),
.reset (reset),
.push (sreq_push),
.pop (sreq_pop),
.data_in ({snp_req_addr, snp_req_inv, snp_req_tag}),
.data_out({sreq_addr_st0, sreq_inv_st0, sreq_tag_st0}),
.empty (sreq_empty),
.full (sreq_full),
`UNUSED_PIN (size)
);
end else begin
`UNUSED_VAR (snp_req_valid)
`UNUSED_VAR (snp_req_addr)
`UNUSED_VAR (snp_req_inv)
`UNUSED_VAR (snp_req_tag)
assign sreq_empty = 1;
assign sreq_addr_st0 = 0;
assign sreq_inv_st0 = 0;
assign sreq_tag_st0 = 0;
assign snp_req_ready = 0;
end
wire drsq_pop;
wire drsq_empty;
@ -258,19 +195,15 @@ module VX_bank #(
wire [`REQ_TAG_WIDTH-1:0] mshr_tag_st0;
wire mshr_rw_st0;
wire [WORD_SIZE-1:0] mshr_byteen_st0;
wire mshr_is_snp_st0;
wire mshr_snp_inv_st0;
wire mshr_pending_hazard_unqual_st0;
wire is_fill_st0;
wire is_mshr_st0;
wire is_snp_st0;
wire valid_st0;
wire [`LINE_ADDR_WIDTH-1:0] addr_st0;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st0;
wire [`WORD_WIDTH-1:0] writeword_st0;
wire [`BANK_LINE_WIDTH-1:0] writedata_st0;
wire snp_inv_st0;
wire [`REQ_TAG_WIDTH-1:0] tag_st0;
wire mem_rw_st0;
wire [WORD_SIZE-1:0] byteen_st0;
@ -278,13 +211,11 @@ module VX_bank #(
wire is_fill_st1;
wire is_mshr_st1;
wire is_snp_st1;
wire valid_st1;
wire [`LINE_ADDR_WIDTH-1:0] addr_st1;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1;
wire [`WORD_WIDTH-1:0] writeword_st1;
wire [`BANK_LINE_WIDTH-1:0] writedata_st1;
wire snp_inv_st1;
wire [`TAG_SELECT_BITS-1:0] readtag_st1;
wire miss_st1;
wire force_miss_st1;
@ -305,8 +236,6 @@ module VX_bank #(
wire [BANK_LINE_SIZE-1:0] dirtyb_st2;
wire [`TAG_SELECT_BITS-1:0] readtag_st2;
wire is_fill_st2;
wire is_snp_st2;
wire snp_inv_st2;
wire is_mshr_st2;
wire miss_st2;
wire force_miss_st2;
@ -331,26 +260,25 @@ module VX_bank #(
wire mshr_push_stall;
wire crsq_push_stall;
wire dreq_push_stall;
wire srsq_push_stall;
wire dreq_push_stall;
wire pipeline_stall;
wire is_mshr_miss_st2 = valid_st2 && is_mshr_st2 && (miss_st2 || force_miss_st2);
wire is_mshr_miss_st3 = valid_st3 && is_mshr_st3 && (miss_st3 || force_miss_st3);
wire creq_commit = valid_st2 && core_req_hit_st2 && !pipeline_stall;
wire creq_commit = valid_st2
&& (core_req_hit_st2 || (WRITE_THROUGH && mem_rw_st2))
&& !pipeline_stall;
// determine which queue to pop next in piority order
wire mshr_pop_unqual = mshr_valid_st0;
wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_going_full;
wire sreq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_pop_unqual && !sreq_empty && !mshr_going_full;
assign mshr_pop = mshr_pop_unqual && !pipeline_stall
&& !(is_mshr_miss_st2 || is_mshr_miss_st3); // stop if previous request was a miss
assign drsq_pop = drsq_pop_unqual && !pipeline_stall;
assign creq_pop = creq_pop_unqual && !pipeline_stall;
assign sreq_pop = sreq_pop_unqual && !pipeline_stall;
// MSHR pending size
assign mshr_pending_size_n = mshr_pending_size +
@ -368,12 +296,11 @@ module VX_bank #(
assign is_mshr_st0 = mshr_pop_unqual;
assign is_fill_st0 = drsq_pop_unqual;
assign valid_st0 = drsq_pop || mshr_pop || creq_pop || sreq_pop;
assign valid_st0 = drsq_pop || mshr_pop || creq_pop;
assign addr_st0 = mshr_pop_unqual ? mshr_addr_st0 :
drsq_pop_unqual ? drsq_addr_st0 :
creq_pop_unqual ? creq_addr_st0[`LINE_SELECT_ADDR_RNG] :
sreq_pop_unqual ? sreq_addr_st0 :
0;
if (`WORD_SELECT_WIDTH != 0) begin
@ -389,32 +316,20 @@ module VX_bank #(
assign tag_st0 = mshr_pop_unqual ? `REQ_TAG_WIDTH'(mshr_tag_st0) :
creq_pop_unqual ? `REQ_TAG_WIDTH'(creq_tag_st0) :
sreq_pop_unqual ? `REQ_TAG_WIDTH'(sreq_tag_st0) :
0;
assign mem_rw_st0 = mshr_pop_unqual ? mshr_rw_st0 :
creq_pop_unqual ? creq_rw_st0 :
sreq_pop_unqual ? 1'b0 :
0;
assign byteen_st0 = mshr_pop_unqual ? mshr_byteen_st0 :
creq_pop_unqual ? creq_byteen_st0 :
sreq_pop_unqual ? WORD_SIZE'(0) :
0;
assign req_tid_st0 = mshr_pop_unqual ? mshr_tid_st0 :
creq_pop_unqual ? creq_tid_st0 :
sreq_pop_unqual ? `REQS_BITS'(0) :
0;
assign is_snp_st0 = mshr_pop_unqual ? mshr_is_snp_st0 :
sreq_pop_unqual ? 1 :
0;
assign snp_inv_st0 = mshr_pop_unqual ? mshr_snp_inv_st0 :
sreq_pop_unqual ? sreq_inv_st0 :
0;
assign writeword_st0 = mshr_pop_unqual ? mshr_writeword_st0 :
creq_pop_unqual ? creq_writeword_st0 :
0;
@ -436,15 +351,15 @@ if (DRAM_ENABLE) begin
|| (valid_st3 && (miss_st3 || force_miss_st3) && (addr_st3 == addr_st0));
VX_generic_register #(
.N(1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.R(1)
) pipe_reg0 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.data_in ({valid_st0, is_mshr_st0, is_snp_st0, snp_inv_st0, mshr_pending_hazard_st0, addr_st0, wsel_st0, writeword_st0, is_fill_st0, writedata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}),
.data_out ({valid_st1, is_mshr_st1, is_snp_st1, snp_inv_st1, mshr_pending_hazard_st1, addr_st1, wsel_st1, writeword_st1, is_fill_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1})
.data_in ({valid_st0, is_mshr_st0, mshr_pending_hazard_st0, addr_st0, wsel_st0, writeword_st0, is_fill_st0, writedata_st0, mem_rw_st0, byteen_st0, req_tid_st0, tag_st0}),
.data_out ({valid_st1, is_mshr_st1, mshr_pending_hazard_st1, addr_st1, wsel_st1, writeword_st1, is_fill_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1})
);
`ifdef DBG_CACHE_REQ_INFO
@ -471,8 +386,7 @@ if (DRAM_ENABLE) begin
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),
.FLUSH_ENABLE (FLUSH_ENABLE)
.WRITE_ENABLE (WRITE_ENABLE)
) tag_access (
.clk (clk),
.reset (reset),
@ -491,8 +405,6 @@ if (DRAM_ENABLE) begin
.addr_in (addr_st1),
.is_write_in (mem_rw_st1),
.is_fill_in (is_fill_st1),
.is_snp_in (is_snp_st1),
.snp_inv_in (snp_inv_st1),
.force_miss_in (force_miss_st1),
// Outputs
@ -504,20 +416,20 @@ if (DRAM_ENABLE) begin
assign misses = miss_st1;
wire core_req_hit_st1 = !is_fill_st1 && !is_snp_st1 && !miss_st1 && !force_miss_st1;
wire core_req_hit_st1 = !is_fill_st1 && !miss_st1 && !force_miss_st1;
wire incoming_fill_st1 = !drsq_empty && (addr_st1 == drsq_addr_st0);
VX_generic_register #(
.N(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.N(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + `BANK_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + `REQ_TAG_WIDTH),
.R(1)
) pipe_reg1 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.data_in ({valid_st1, incoming_fill_st1, core_req_hit_st1, is_mshr_st1, writeen_st1, force_miss_st1, dirty_st1, is_snp_st1, snp_inv_st1, is_fill_st1, addr_st1, wsel_st1, writeword_st1, readtag_st1, miss_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}),
.data_out ({valid_st2, incoming_fill_st2, core_req_hit_st2, is_mshr_st2, writeen_st2, force_miss_st2, dirty_st2, is_snp_st2, snp_inv_st2, is_fill_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, writedata_st2, mem_rw_st2, byteen_st2, req_tid_st2, tag_st2})
.data_in ({valid_st1, incoming_fill_st1, core_req_hit_st1, is_mshr_st1, writeen_st1, force_miss_st1, dirty_st1, is_fill_st1, addr_st1, wsel_st1, writeword_st1, readtag_st1, miss_st1, writedata_st1, mem_rw_st1, byteen_st1, req_tid_st1, tag_st1}),
.data_out ({valid_st2, incoming_fill_st2, core_req_hit_st2, is_mshr_st2, writeen_st2, force_miss_st2, dirty_st2, is_fill_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, writedata_st2, mem_rw_st2, byteen_st2, req_tid_st2, tag_st2})
);
end else begin
@ -528,12 +440,10 @@ end else begin
assign is_fill_st1 = is_fill_st0;
assign is_mshr_st1 = is_mshr_st0;
assign is_snp_st1 = is_snp_st0;
assign valid_st1 = valid_st0;
assign wsel_st1 = wsel_st0;
assign writeword_st1= writeword_st0;
assign writedata_st1= writedata_st0;
assign snp_inv_st1 = snp_inv_st0;
assign addr_st1 = creq_addr_st0[`LINE_SELECT_ADDR_RNG];
assign dirty_st1 = 0;
assign readtag_st1 = 0;
@ -547,12 +457,10 @@ end else begin
assign is_fill_st2 = is_fill_st1;
assign is_mshr_st2 = is_mshr_st1;
assign is_snp_st2 = is_snp_st1;
assign valid_st2 = valid_st1;
assign wsel_st2 = wsel_st1;
assign writeword_st2= writeword_st1;
assign writedata_st2= writedata_st1;
assign snp_inv_st2 = snp_inv_st1;
assign addr_st2 = addr_st1;
assign dirty_st2 = dirty_st1;
assign readtag_st2 = readtag_st1;
@ -586,7 +494,8 @@ end
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.WRITE_ENABLE (WRITE_ENABLE)
.WRITE_ENABLE (WRITE_ENABLE),
.WRITE_THROUGH (WRITE_THROUGH)
) data_access (
.clk (clk),
.reset (reset),
@ -597,7 +506,6 @@ end
.debug_wid (debug_wid_st2),
.debug_tagid (debug_tagid_st2),
`endif
.stall (pipeline_stall),
// Inputs
@ -621,45 +529,41 @@ end
wire [`WORD_WIDTH-1:0] readword_st3;
wire [`BANK_LINE_WIDTH-1:0] readdata_st3;
wire [BANK_LINE_SIZE-1:0] dirtyb_st3;
wire [`TAG_SELECT_BITS-1:0] readtag_st3;
wire is_snp_st3;
wire snp_inv_st3;
wire [`TAG_SELECT_BITS-1:0] readtag_st3;
wire do_writeback_st3;
wire incoming_fill_st3;
wire mshr_push_st3;
wire crsq_push_st3;
wire dreq_push_st3;
wire srsq_push_st3;
wire incoming_fill_qual_st2 = (!drsq_empty && (addr_st2 == drsq_addr_st0)) || incoming_fill_st2;
wire do_fill_req_st2 = miss_st2
&& !(WRITE_THROUGH && mem_rw_st2)
&& (!force_miss_st2
|| (is_mshr_st2 && addr_st2 != addr_st3))
&& !incoming_fill_qual_st2;
wire do_writeback_st2 = dirty_st2
&& (is_fill_st2
|| (!force_miss_st2 && is_snp_st2));
wire mshr_push_st2 = miss_st2 || force_miss_st2;
wire crsq_push_st2 = core_req_hit_st2 && !mem_rw_st2;
wire do_writeback_st2 = (WRITE_THROUGH && mem_rw_st2)
|| (!WRITE_THROUGH && dirty_st2 && is_fill_st2);
wire dreq_push_st2 = do_fill_req_st2 || do_writeback_st2;
wire srsq_push_st2 = is_snp_st2 && !force_miss_st2;
wire mshr_push_st2 = (miss_st2 || force_miss_st2)
&& !(WRITE_THROUGH && mem_rw_st2);
wire crsq_push_st2 = core_req_hit_st2 && !mem_rw_st2;
VX_generic_register #(
.N(1 + 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + 1 + WORD_SIZE + `WORD_WIDTH + `BANK_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH),
.N(1 + 1+ 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `TAG_SELECT_BITS + BANK_LINE_SIZE + 1 + WORD_SIZE + `WORD_WIDTH + `BANK_LINE_WIDTH + `REQS_BITS + `REQ_TAG_WIDTH),
.R(1)
) pipe_reg2 (
.clk (clk),
.reset (reset),
.stall (pipeline_stall),
.flush (1'b0),
.data_in ({valid_st2, mshr_push_st2, crsq_push_st2, dreq_push_st2, srsq_push_st2, do_writeback_st2, incoming_fill_qual_st2, force_miss_st2, is_mshr_st2, is_snp_st2, snp_inv_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, dirtyb_st2, mem_rw_st2, byteen_st2, readword_st2, readdata_st2, req_tid_st2, tag_st2}),
.data_out ({valid_st3, mshr_push_st3, crsq_push_st3, dreq_push_st3, srsq_push_st3, do_writeback_st3, incoming_fill_st3, force_miss_st3, is_mshr_st3, is_snp_st3, snp_inv_st3, addr_st3, wsel_st3, writeword_st3, readtag_st3, miss_st3, dirtyb_st3, mem_rw_st3, byteen_st3, readword_st3, readdata_st3, req_tid_st3, tag_st3})
.data_in ({valid_st2, mshr_push_st2, crsq_push_st2, dreq_push_st2, do_writeback_st2, incoming_fill_qual_st2, force_miss_st2, is_mshr_st2, addr_st2, wsel_st2, writeword_st2, readtag_st2, miss_st2, dirtyb_st2, mem_rw_st2, byteen_st2, readword_st2, readdata_st2, req_tid_st2, tag_st2}),
.data_out ({valid_st3, mshr_push_st3, crsq_push_st3, dreq_push_st3, do_writeback_st3, incoming_fill_st3, force_miss_st3, is_mshr_st3, addr_st3, wsel_st3, writeword_st3, readtag_st3, miss_st3, dirtyb_st3, mem_rw_st3, byteen_st3, readword_st3, readdata_st3, req_tid_st3, tag_st3})
);
`ifdef DBG_CACHE_REQ_INFO
@ -677,8 +581,7 @@ end
wire mshr_push = mshr_push_unqual
&& !crsq_push_stall
&& !dreq_push_stall
&& !srsq_push_stall;
&& !dreq_push_stall;
wire mshr_full;
always @(posedge clk) begin
@ -707,8 +610,7 @@ end
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS),
.MSHR_SIZE (MSHR_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.SNP_TAG_WIDTH (SNP_TAG_WIDTH)
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) miss_resrv (
.clk (clk),
.reset (reset),
@ -727,7 +629,7 @@ end
// enqueue
.enqueue_st3 (mshr_push),
.enqueue_addr_st3 (addr_st3),
.enqueue_data_st3 ({writeword_st3, req_tid_st3, tag_st3, mem_rw_st3, byteen_st3, wsel_st3, is_snp_st3, snp_inv_st3}),
.enqueue_data_st3 ({writeword_st3, req_tid_st3, tag_st3, mem_rw_st3, byteen_st3, wsel_st3}),
.enqueue_is_mshr_st3(is_mshr_st3),
.enqueue_ready_st3 (mshr_init_ready_state_st3),
.enqueue_full (mshr_full),
@ -741,7 +643,7 @@ end
.schedule_st0 (mshr_pop),
.dequeue_valid_st0 (mshr_valid_st0),
.dequeue_addr_st0 (mshr_addr_st0),
.dequeue_data_st0 ({mshr_writeword_st0, mshr_tid_st0, mshr_tag_st0, mshr_rw_st0, mshr_byteen_st0, mshr_wsel_st0, mshr_is_snp_st0, mshr_snp_inv_st0}),
.dequeue_data_st0 ({mshr_writeword_st0, mshr_tid_st0, mshr_tag_st0, mshr_rw_st0, mshr_byteen_st0, mshr_wsel_st0}),
.dequeue_st3 (mshr_dequeue_st3)
);
end else begin
@ -749,10 +651,8 @@ end
`UNUSED_VAR (mshr_push)
`UNUSED_VAR (wsel_st3)
`UNUSED_VAR (writeword_st3)
`UNUSED_VAR (snp_inv_st3)
`UNUSED_VAR (mem_rw_st3)
`UNUSED_VAR (byteen_st3)
`UNUSED_VAR (is_snp_st3)
`UNUSED_VAR (incoming_fill_st3)
assign mshr_pending_hazard_unqual_st0 = 0;
assign mshr_full = 0;
@ -764,8 +664,6 @@ end
assign mshr_tag_st0 = 0;
assign mshr_rw_st0 = 0;
assign mshr_byteen_st0 = 0;
assign mshr_is_snp_st0 = 0;
assign mshr_snp_inv_st0 = 0;
end
// Enqueue core response
@ -778,8 +676,7 @@ end
wire crsq_push = crsq_push_unqual
&& !crsq_full
&& !mshr_push_stall
&& !dreq_push_stall
&& !srsq_push_stall;
&& !dreq_push_stall;
wire crsq_pop = core_rsp_valid && core_rsp_ready;
@ -817,15 +714,14 @@ end
&& (do_writeback_st3 || !incoming_fill_qual_st3)
&& !dreq_full
&& !mshr_push_stall
&& !crsq_push_stall
&& !srsq_push_stall;
&& !crsq_push_stall;
wire dreq_pop = dram_req_valid && dram_req_ready;
wire writeback = WRITE_ENABLE && do_writeback_st3;
wire [`LINE_ADDR_WIDTH-1:0] dreq_addr = writeback ? {readtag_st3, addr_st3[`LINE_SELECT_BITS-1:0]} :
addr_st3;
wire [`LINE_ADDR_WIDTH-1:0] dreq_addr = (WRITE_THROUGH || !writeback) ? addr_st3 :
{readtag_st3, addr_st3[`LINE_SELECT_BITS-1:0]};
wire [BANK_LINE_SIZE-1:0] dreq_byteen = writeback ? dirtyb_st3 : {BANK_LINE_SIZE{1'b1}};
@ -864,67 +760,18 @@ end
assign dram_req_data = 0;
end
assign dram_req_valid = !dreq_empty;
// Enqueue snoop response
wire srsq_empty, srsq_full;
wire srsq_push_unqual = valid_st3 && srsq_push_st3;
assign srsq_push_stall = srsq_push_unqual && srsq_full;
wire srsq_push = srsq_push_unqual
&& !srsq_full
&& !mshr_push_stall
&& !crsq_push_stall
&& !dreq_push_stall;
wire srsq_pop = snp_rsp_valid && snp_rsp_ready;
wire [SNP_TAG_WIDTH-1:0] srsq_tag_st3 = SNP_TAG_WIDTH'(tag_st3);
if (FLUSH_ENABLE) begin
VX_generic_queue #(
.DATAW (SNP_TAG_WIDTH),
.SIZE (SRSQ_SIZE),
.BUFFERED (1),
.FASTRAM (1)
) snp_rsp_queue (
.clk (clk),
.reset (reset),
.push (srsq_push),
.pop (srsq_pop),
.data_in (srsq_tag_st3),
.data_out(snp_rsp_tag),
.empty (srsq_empty),
.full (srsq_full),
`UNUSED_PIN (size)
);
end else begin
`UNUSED_VAR (srsq_push)
`UNUSED_VAR (srsq_pop)
`UNUSED_VAR (srsq_tag_st3)
`UNUSED_VAR (snp_rsp_ready)
assign srsq_empty = 1;
assign srsq_full = 0;
assign snp_rsp_tag = 0;
end
assign snp_rsp_valid = !srsq_empty
&& dreq_empty; // ensure all writebacks are sent
assign dram_req_valid = !dreq_empty;
// bank pipeline stall
assign pipeline_stall = mshr_push_stall
|| crsq_push_stall
|| dreq_push_stall
|| srsq_push_stall;
|| dreq_push_stall;
`SCOPE_ASSIGN (valid_st0, valid_st0);
`SCOPE_ASSIGN (valid_st1, valid_st1);
`SCOPE_ASSIGN (valid_st2, valid_st2);
`SCOPE_ASSIGN (valid_st3, valid_st3);
`SCOPE_ASSIGN (is_fill_st0, is_fill_st0);
`SCOPE_ASSIGN (is_snp_st0, is_snp_st0);
`SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0);
`SCOPE_ASSIGN (miss_st1, miss_st1);
`SCOPE_ASSIGN (dirty_st1, dirty_st1);
@ -951,7 +798,7 @@ end
assert(!is_mshr_st3);
end
if (pipeline_stall) begin
$display("%t: cache%0d:%0d pipeline-stall: msrq=%b, cwbq=%b, dwbq=%b, snpq=%b", $time, CACHE_ID, BANK_ID, mshr_push_stall, crsq_push_stall, dreq_push_stall, srsq_push_stall);
$display("%t: cache%0d:%0d pipeline-stall: msrq=%b, cwbq=%b, dwbq=%b", $time, CACHE_ID, BANK_ID, mshr_push_stall, crsq_push_stall, dreq_push_stall);
end
if (drsq_pop) begin
$display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), drsq_filldata_st0);
@ -962,9 +809,6 @@ end
else
$display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), creq_tag_st0, creq_tid_st0, creq_byteen_st0, debug_wid_st0, debug_pc_st0);
end
if (sreq_pop) begin
$display("%t: cache%0d:%0d snp-req: addr=%0h, tag=%0h, invalidate=%0d", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), sreq_tag_st0, sreq_inv_st0);
end
if (crsq_push) begin
$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), crsq_tag_st3, crsq_tid_st3, crsq_data_st3, debug_wid_st3, debug_pc_st3);
end
@ -974,9 +818,6 @@ end
else
$display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), debug_wid_st3, debug_pc_st3);
end
if (srsq_push) begin
$display("%t: cache%0d:%0d snp-rsp: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), srsq_tag_st3);
end
end
`endif

119
hw/rtl/cache/VX_cache.v vendored
View file

@ -19,25 +19,21 @@ module VX_cache #(
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 8,
// DRAM Response Queue Size
parameter DRSQ_SIZE = 4,
// Snoop Request Queue Size
parameter SREQ_SIZE = 4,
parameter DRSQ_SIZE = 4,
// Core Response Queue Size
parameter CRSQ_SIZE = 4,
// DRAM Request Queue Size
parameter DREQ_SIZE = 4,
// Snoop Response Size
parameter SRSQ_SIZE = 4,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
// Enable dram update
parameter DRAM_ENABLE = 1,
// Enable cache flush
parameter FLUSH_ENABLE = 1,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
// Enable write-through
parameter WRITE_THROUGH = 1,
// core request tag size
parameter CORE_TAG_WIDTH = $clog2(MSHR_SIZE),
@ -46,10 +42,7 @@ module VX_cache #(
parameter CORE_TAG_ID_BITS = 0,
// dram request tag size
parameter DRAM_TAG_WIDTH = (32 - $clog2(BANK_LINE_SIZE)),
// Snooping request tag width
parameter SNP_TAG_WIDTH = 1
parameter DRAM_TAG_WIDTH = (32 - $clog2(BANK_LINE_SIZE))
) (
`SCOPE_IO_VX_cache
@ -89,19 +82,7 @@ module VX_cache #(
input wire dram_rsp_valid,
input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
output wire dram_rsp_ready,
output wire [NUM_BANKS-1:0] miss_vec
);
@ -127,12 +108,6 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_snp_req_ready;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid;
wire [NUM_BANKS-1:0][SNP_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_miss;
assign miss_vec = per_bank_miss;
@ -141,13 +116,7 @@ module VX_cache #(
wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
wire [NUM_BANKS-1:0] perf_pipe_stall_per_bank;
`endif
if (NUM_BANKS == 1) begin
assign snp_req_ready = per_bank_snp_req_ready;
end else begin
assign snp_req_ready = per_bank_snp_req_ready[`DRAM_ADDR_BANK(snp_req_addr)];
end
`endif
VX_cache_core_req_bank_sel #(
.BANK_LINE_SIZE (BANK_LINE_SIZE),
@ -205,16 +174,6 @@ module VX_cache #(
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_rsp_addr;
wire curr_bank_dram_rsp_ready;
wire curr_bank_snp_req_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr;
wire curr_bank_snp_req_inv;
wire [SNP_TAG_WIDTH-1:0] curr_bank_snp_req_tag;
wire curr_bank_snp_req_ready;
wire curr_bank_snp_rsp_valid;
wire [SNP_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag;
wire curr_bank_snp_rsp_ready;
wire curr_bank_miss;
// Core Req
@ -257,23 +216,6 @@ module VX_cache #(
assign curr_bank_dram_rsp_data = dram_rsp_data;
assign per_bank_dram_rsp_ready[i] = curr_bank_dram_rsp_ready;
// Snoop request
if (NUM_BANKS == 1) begin
assign curr_bank_snp_req_valid = snp_req_valid;
assign curr_bank_snp_req_addr = snp_req_addr;
end else begin
assign curr_bank_snp_req_valid = snp_req_valid && (`DRAM_ADDR_BANK(snp_req_addr) == i);
assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr);
end
assign curr_bank_snp_req_inv = snp_req_inv;
assign curr_bank_snp_req_tag = snp_req_tag;
assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready;
// Snoop response
assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid;
assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag;
assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i];
//Misses
assign per_bank_miss[i] = curr_bank_miss;
@ -288,16 +230,13 @@ module VX_cache #(
.CREQ_SIZE (CREQ_SIZE),
.MSHR_SIZE (MSHR_SIZE),
.DRSQ_SIZE (DRSQ_SIZE),
.SREQ_SIZE (SREQ_SIZE),
.CRSQ_SIZE (CRSQ_SIZE),
.DREQ_SIZE (DREQ_SIZE),
.SRSQ_SIZE (SRSQ_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.FLUSH_ENABLE (FLUSH_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE),
.WRITE_THROUGH (WRITE_THROUGH),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.SNP_TAG_WIDTH (SNP_TAG_WIDTH)
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) bank (
`SCOPE_BIND_VX_cache_bank(i)
@ -342,18 +281,6 @@ module VX_cache #(
.perf_pipe_stalls (perf_pipe_stall_per_bank[i]),
`endif
// Snoop request
.snp_req_valid (curr_bank_snp_req_valid),
.snp_req_addr (curr_bank_snp_req_addr),
.snp_req_inv (curr_bank_snp_req_inv),
.snp_req_tag (curr_bank_snp_req_tag),
.snp_req_ready (curr_bank_snp_req_ready),
// Snoop response
.snp_rsp_valid (curr_bank_snp_rsp_valid),
.snp_rsp_tag (curr_bank_snp_rsp_tag),
.snp_rsp_ready (curr_bank_snp_rsp_ready),
//Misses
.misses (curr_bank_miss)
);
@ -414,30 +341,6 @@ module VX_cache #(
`UNUSED_VAR (dram_req_ready)
end
if (FLUSH_ENABLE) begin
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (SNP_TAG_WIDTH),
.BUFFERED (1)
) snp_rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (per_bank_snp_rsp_valid),
.data_in (per_bank_snp_rsp_tag),
.ready_in (per_bank_snp_rsp_ready),
.valid_out (snp_rsp_valid),
.data_out (snp_rsp_tag),
.ready_out (snp_rsp_ready)
);
end else begin
`UNUSED_VAR (per_bank_snp_rsp_valid)
`UNUSED_VAR (per_bank_snp_rsp_tag)
assign per_bank_snp_rsp_ready = 0;
assign snp_rsp_valid = 0;
assign snp_rsp_tag = 0;
`UNUSED_VAR (snp_rsp_ready)
end
`ifdef PERF_ENABLE
// per cycle: core_reads, core_writes
reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle, perf_core_writes_per_cycle;

6
hw/rtl/cache/VX_cache_config.vh vendored
View file

@ -7,15 +7,15 @@
`include "VX_define.vh"
`endif
`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_TAG_WIDTH)
`define REQ_TAG_WIDTH CORE_TAG_WIDTH
`define REQS_BITS `LOG2UP(NUM_REQS)
// tag rw byteen tid
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// data metadata word_sel is_snp snp_inv
`define MSHR_DATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1 + 1)
// data metadata word_sel
`define MSHR_DATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH))
`define BANK_BITS `LOG2UP(NUM_BANKS)

41
hw/rtl/cache/VX_data_access.v vendored
View file

@ -14,7 +14,10 @@ module VX_data_access #(
parameter WORD_SIZE = 1,
// Enable cache writeable
parameter WRITE_ENABLE = 0,
parameter WRITE_ENABLE = 1,
// Enable write-through
parameter WRITE_THROUGH = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
@ -54,9 +57,9 @@ module VX_data_access #(
wire [BANK_LINE_SIZE-1:0] read_dirtyb_out;
wire [`BANK_LINE_WIDTH-1:0] read_data;
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable;
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable;
wire [`BANK_LINE_WIDTH-1:0] write_data;
wire write_enable;
wire [`BANK_LINE_WIDTH-1:0] write_data;
wire [`LINE_SELECT_BITS-1:0] addrline = addr_in[`LINE_SELECT_BITS-1:0];
@ -92,18 +95,32 @@ module VX_data_access #(
end
end
for (genvar i = 0; i < `BANK_LINE_WORDS; i++) begin
wire word_sel = (`WORD_SELECT_WIDTH == 0) || (wordsel_in == `UP(`WORD_SELECT_WIDTH)'(i));
assign byte_enable[i] = is_fill_in ? {WORD_SIZE{1'b1}} :
word_sel ? byteen_in : {WORD_SIZE{1'b0}};
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] byte_enable_w;
wire [`BANK_LINE_WIDTH-1:0] write_data_w;
assign write_data[i * `WORD_WIDTH +: `WORD_WIDTH] = is_fill_in ? writedata_in[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_in;
end
if (`WORD_SELECT_WIDTH != 0) begin
for (genvar i = 0; i < `BANK_LINE_WORDS; i++) begin
assign byte_enable_w[i] = (wordsel_in == `WORD_SELECT_WIDTH'(i)) ? byteen_in : {WORD_SIZE{1'b0}};
assign write_data_w[i * `WORD_WIDTH +: `WORD_WIDTH] = writeword_in;
end
end else begin
assign byte_enable_w = byteen_in;
assign write_data_w = writeword_in;
end
assign byte_enable = is_fill_in ? {BANK_LINE_SIZE{1'b1}} : byte_enable_w;
assign write_data = is_fill_in ? writedata_in : write_data_w;
assign write_enable = valid_in && writeen_in && !stall;
assign dirtyb_out = read_dirtyb_out;
assign readdata_out = read_data;
if (WRITE_THROUGH) begin
`UNUSED_VAR (read_dirtyb_out)
assign dirtyb_out = byte_enable_w;
assign readdata_out = write_data_w;
end else begin
assign dirtyb_out = read_dirtyb_out;
assign readdata_out = read_data;
end
`ifdef DBG_PRINT_CACHE_DATA
always @(posedge clk) begin

2
hw/rtl/cache/VX_miss_resrv.v vendored
View file

@ -16,8 +16,6 @@ module VX_miss_resrv #(
parameter MSHR_SIZE = 1,
// core request tag size
parameter CORE_TAG_WIDTH = 1,
// Snooping request tag width
parameter SNP_TAG_WIDTH = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
) (

249
hw/rtl/cache/VX_snp_forwarder.v vendored
View file

@ -1,249 +0,0 @@
`include "VX_cache_config.vh"
module VX_snp_forwarder #(
parameter CACHE_ID = 0,
parameter SRC_ADDR_WIDTH = 1,
parameter DST_ADDR_WIDTH = 1,
parameter NUM_REQS = 1,
parameter SREQ_SIZE = 1,
parameter TAG_IN_WIDTH = 1,
parameter TAG_OUT_WIDTH = `LOG2UP(SREQ_SIZE),
parameter BUFFERED = 0
) (
input wire clk,
input wire reset,
// Snoop request
input wire snp_req_valid,
input wire [SRC_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [TAG_IN_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [SRC_ADDR_WIDTH-1:0] snp_rsp_addr,
output wire snp_rsp_inv,
output wire [TAG_IN_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// Snoop Forwarding out
output wire [NUM_REQS-1:0] snp_fwdout_valid,
output wire [NUM_REQS-1:0][DST_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_REQS-1:0] snp_fwdout_inv,
output wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] snp_fwdout_tag,
input wire [NUM_REQS-1:0] snp_fwdout_ready,
// Snoop forwarding in
input wire [NUM_REQS-1:0] snp_fwdin_valid,
input wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] snp_fwdin_tag,
output wire [NUM_REQS-1:0] snp_fwdin_ready
);
localparam ADDR_DIFF = DST_ADDR_WIDTH - SRC_ADDR_WIDTH;
localparam NUM_REQUESTS_QUAL = NUM_REQS * (1 << ADDR_DIFF);
localparam REQ_QUAL_BITS = `LOG2UP(NUM_REQUESTS_QUAL);
if (NUM_REQS > 1) begin
reg [REQ_QUAL_BITS:0] pending_cntrs [SREQ_SIZE-1:0];
wire [TAG_IN_WIDTH-1:0] snp_rsp_tag_unqual;
wire [SRC_ADDR_WIDTH-1:0] snp_rsp_addr_unqual;
wire snp_rsp_inv_unqual;
wire snp_rsp_ready_unqual;
wire [TAG_OUT_WIDTH-1:0] sfq_write_addr, sfq_read_addr;
wire sfq_full;
wire [TAG_OUT_WIDTH-1:0] fwdin_tag;
wire fwdin_valid;
wire fwdin_ready = snp_rsp_ready_unqual || (1 != pending_cntrs[sfq_read_addr]);
wire fwdin_fire = fwdin_valid && fwdin_ready;
wire snp_rsp_valid_unqual = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]);
assign sfq_read_addr = fwdin_tag;
wire sfq_acquire = snp_req_valid && snp_req_ready;
wire sfq_release = snp_rsp_valid_unqual && snp_rsp_ready_unqual;
VX_index_buffer #(
.DATAW (SRC_ADDR_WIDTH + 1 + TAG_IN_WIDTH),
.SIZE (SREQ_SIZE),
.FASTRAM (1)
) req_metadata_buf (
.clk (clk),
.reset (reset),
.write_addr (sfq_write_addr),
.acquire_slot (sfq_acquire),
.read_addr (sfq_read_addr),
.write_data ({snp_req_tag, snp_req_addr, snp_req_inv}),
.read_data ({snp_rsp_tag_unqual, snp_rsp_addr_unqual, snp_rsp_inv_unqual}),
.release_addr (sfq_read_addr),
.release_slot (sfq_release),
.full (sfq_full)
);
wire fwdout_valid;
wire [TAG_OUT_WIDTH-1:0] fwdout_tag;
wire [DST_ADDR_WIDTH-1:0] fwdout_addr;
wire fwdout_inv;
wire fwdout_ready;
wire dispatch_hold;
if (ADDR_DIFF != 0) begin
reg [TAG_OUT_WIDTH-1:0] fwdout_tag_r;
reg [DST_ADDR_WIDTH-1:0] fwdout_addr_r;
reg fwdout_inv_r;
reg dispatch_hold_r;
always @(posedge clk) begin
if (reset) begin
dispatch_hold_r <= 0;
end else begin
if (snp_req_valid && snp_req_ready) begin
dispatch_hold_r <= 1;
end
if (dispatch_hold_r
&& fwdout_ready
&& (fwdout_addr[ADDR_DIFF-1:0] == ((1 << ADDR_DIFF)-1))) begin
dispatch_hold_r <= 0;
end
end
if (fwdout_valid && fwdout_ready) begin
fwdout_addr_r <= fwdout_addr + DST_ADDR_WIDTH'(1'b1);
end
if (snp_req_valid && snp_req_ready) begin
fwdout_inv_r <= snp_req_inv;
fwdout_tag_r <= sfq_write_addr;
end
end
assign fwdout_valid = dispatch_hold_r || (snp_req_valid && !sfq_full);
assign fwdout_tag = dispatch_hold_r ? fwdout_tag_r : sfq_write_addr;
assign fwdout_addr = dispatch_hold_r ? fwdout_addr_r : {snp_req_addr, ADDR_DIFF'(0)};
assign fwdout_inv = dispatch_hold_r ? fwdout_inv_r : snp_req_inv;
assign dispatch_hold = dispatch_hold_r;
end else begin
assign fwdout_valid = snp_req_valid && !sfq_full;
assign fwdout_tag = sfq_write_addr;
assign fwdout_addr = snp_req_addr;
assign fwdout_inv = snp_req_inv;
assign dispatch_hold = 1'b0;
end
always @(posedge clk) begin
if (sfq_acquire) begin
pending_cntrs[sfq_write_addr] <= NUM_REQUESTS_QUAL;
end
if (fwdin_fire) begin
pending_cntrs[sfq_read_addr] <= pending_cntrs[sfq_read_addr] - 1;
end
end
reg [NUM_REQS-1:0] snp_fwdout_ready_other;
wire [NUM_REQS-1:0] fwdout_ready_unqual;
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (DST_ADDR_WIDTH + 1 + TAG_OUT_WIDTH),
.PASSTHRU (!BUFFERED)
) fwdout_buffer (
.clk (clk),
.reset (reset),
.valid_in (fwdout_valid && snp_fwdout_ready_other[i]),
.data_in ({fwdout_addr, fwdout_inv, fwdout_tag}),
.ready_in (fwdout_ready_unqual[i]),
.valid_out (snp_fwdout_valid[i]),
.data_out ({snp_fwdout_addr[i], snp_fwdout_inv[i], snp_fwdout_tag[i]}),
.ready_out (snp_fwdout_ready[i])
);
end
always @(*) begin
snp_fwdout_ready_other = {NUM_REQS{1'b1}};
for (integer i = 0; i < NUM_REQS; i++) begin
for (integer j = 0; j < NUM_REQS; j++) begin
if (i != j)
snp_fwdout_ready_other[i] &= fwdout_ready_unqual[j];
end
end
end
assign fwdout_ready = (& fwdout_ready_unqual);
assign snp_req_ready = fwdout_ready && !sfq_full && !dispatch_hold;
VX_stream_arbiter #(
.NUM_REQS (NUM_REQS),
.DATAW (TAG_OUT_WIDTH)
) snp_fwdin_arb (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid),
.data_in (snp_fwdin_tag),
.ready_in (snp_fwdin_ready),
.valid_out (fwdin_valid),
.data_out (fwdin_tag),
.ready_out (fwdin_ready)
);
VX_skid_buffer #(
.DATAW (TAG_IN_WIDTH + SRC_ADDR_WIDTH + 1),
.PASSTHRU (!BUFFERED)
) rsp_buffer (
.clk (clk),
.reset (reset),
.valid_in (snp_rsp_valid_unqual),
.data_in ({snp_rsp_tag_unqual, snp_rsp_addr_unqual, snp_rsp_inv_unqual}),
.ready_in (snp_rsp_ready_unqual),
.valid_out (snp_rsp_valid),
.data_out ({snp_rsp_tag, snp_rsp_addr, snp_rsp_inv}),
.ready_out (snp_rsp_ready)
);
`ifdef DBG_PRINT_CACHE_SNP
always @(posedge clk) begin
if (fwdin_valid && fwdin_ready) begin
$display("%t: cache%0d snp-fwd-in: tag=%0h", $time, CACHE_ID, fwdin_tag);
end
end
`endif
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign snp_fwdout_valid = snp_req_valid;
assign snp_fwdout_addr = snp_req_addr;
assign snp_fwdout_inv = snp_req_inv;
assign snp_fwdout_tag = snp_req_tag;
assign snp_req_ready = snp_fwdout_ready;
assign snp_rsp_valid = snp_fwdin_valid;
assign snp_rsp_addr = snp_req_addr;
assign snp_rsp_inv = snp_req_inv;
assign snp_rsp_tag = snp_fwdin_tag;
assign snp_fwdin_ready = snp_rsp_ready;
end
`ifdef DBG_PRINT_CACHE_SNP
always @(posedge clk) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: cache%0d snp-fwd-req: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, `TO_FULL_ADDR(snp_req_addr), snp_req_inv, snp_req_tag);
end
if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
$display("%t: cache%0d snp-fwd-out: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, `TO_FULL_ADDR(snp_fwdout_addr[0]), snp_fwdout_inv[0], snp_fwdout_tag[0]);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: cache%0d snp-fwd-rsp: addr=%0h, invalidate=%0d, tag=%0h", $time, CACHE_ID, snp_rsp_addr, snp_rsp_inv, snp_rsp_tag);
end
end
`endif
endmodule

15
hw/rtl/cache/VX_tag_access.v vendored
View file

@ -16,9 +16,6 @@ module VX_tag_access #(
// Enable cache writeable
parameter WRITE_ENABLE = 0,
// Enable cache flush
parameter FLUSH_ENABLE = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
) (
@ -41,8 +38,6 @@ module VX_tag_access #(
input wire[`LINE_ADDR_WIDTH-1:0] addr_in,
input wire is_write_in,
input wire is_fill_in,
input wire is_snp_in,
input wire snp_inv_in,
input wire force_miss_in,
// Outputs
@ -90,7 +85,6 @@ module VX_tag_access #(
assign do_write = WRITE_ENABLE
&& valid_in
&& tags_match
&& !is_snp_in
&& !is_fill_in
&& is_write_in
&& !force_miss_in
@ -100,17 +94,10 @@ module VX_tag_access #(
&& is_fill_in
&& !stall;
assign do_invalidate = FLUSH_ENABLE
&& valid_in
&& tags_match
&& is_snp_in
&& (read_dirty || snp_inv_in)
&& !force_miss_in
&& !stall;
assign do_invalidate = 0;
assign miss_out = valid_in
&& !tags_match
&& !is_snp_in
&& !is_fill_in;
assign dirty_out = WRITE_ENABLE

19
hw/rtl/interfaces/VX_cache_snp_req_if.v
View file

@ -1,19 +0,0 @@
`ifndef VX_CACHE_SNP_REQ_IF
`define VX_CACHE_SNP_REQ_IF
`include "../cache/VX_cache_config.vh"
interface VX_cache_snp_req_if #(
parameter DRAM_ADDR_WIDTH = 0,
parameter SNP_TAG_WIDTH = 0
) ();
wire valid;
wire [DRAM_ADDR_WIDTH-1:0] addr;
wire invalidate;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
endinterface
`endif

16
hw/rtl/interfaces/VX_cache_snp_rsp_if.v
View file

@ -1,16 +0,0 @@
`ifndef VX_CACHE_SNP_RSP_IF
`define VX_CACHE_SNP_RSP_IF
`include "../cache/VX_cache_config.vh"
interface VX_cache_snp_rsp_if #(
parameter SNP_TAG_WIDTH = 0
) ();
wire valid;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
endinterface
`endif

114
hw/simulate/simulator.cpp
View file

@ -62,21 +62,15 @@ void Simulator::reset() {
dram_rsp_vec_.clear();
dram_rsp_active_ = false;
snp_req_active_ = false;
csr_req_active_ = false;
snp_req_size_ = 0;
pending_snp_reqs_ = 0;
csr_rsp_value_ = nullptr;
vortex_->dram_rsp_valid = 0;
vortex_->dram_req_ready = 0;
//vortex_->io_req_ready = 0;
//vortex_->io_rsp_valid = 0;
vortex_->snp_req_valid = 0;
vortex_->snp_rsp_ready = 0;
vortex_->csr_io_req_valid = 0;
vortex_->csr_io_rsp_ready = 0;
vortex_->csr_req_valid = 0;
vortex_->csr_rsp_ready = 0;
vortex_->reset = 1;
@ -97,8 +91,7 @@ void Simulator::step() {
this->eval();
dram_rsp_ready_ = vortex_->dram_rsp_ready;
snp_req_ready_ = vortex_->snp_req_ready;
csr_io_req_ready_ = vortex_->csr_io_req_ready;
csr_req_ready_ = vortex_->csr_req_ready;
vortex_->clk = 1;
this->eval();
@ -106,7 +99,6 @@ void Simulator::step() {
this->eval_dram_bus();
this->eval_io_bus();
this->eval_csr_bus();
this->eval_snp_bus();
#ifndef NDEBUG
fflush(stdout);
@ -220,63 +212,30 @@ void Simulator::eval_io_bus() {
vortex_->io_rsp_valid = 0;*/
}
void Simulator::eval_snp_bus() {
if (snp_req_active_) {
if (vortex_->snp_req_valid && snp_req_ready_) {
assert(snp_req_size_);
#ifdef DBG_PRINT_CACHE_SNP
std::cout << std::dec << timestamp << ": [sim] SNP Req: addr=" << std::hex << vortex_->snp_req_addr << " tag=" << vortex_->snp_req_tag << " remain=" << (snp_req_size_-1) << std::endl;
#endif
++vortex_->snp_req_addr;
++vortex_->snp_req_tag;
++pending_snp_reqs_;
--snp_req_size_;
if (0 == snp_req_size_) {
vortex_->snp_req_valid = false;
}
}
if (vortex_->snp_rsp_valid && vortex_->snp_rsp_ready) {
assert(pending_snp_reqs_ > 0);
--pending_snp_reqs_;
if (!vortex_->snp_req_valid && 0 == pending_snp_reqs_) {
vortex_->snp_rsp_ready = false;
snp_req_active_ = false;
}
#ifdef DBG_PRINT_CACHE_SNP
std::cout << std::dec << timestamp << ": [sim] SNP Rsp: tag=" << std::hex << vortex_->snp_rsp_tag << " pending=" << pending_snp_reqs_ << std::endl;
#endif
}
} else {
vortex_->snp_req_valid = 0;
vortex_->snp_rsp_ready = 0;
}
}
void Simulator::eval_csr_bus() {
if (csr_req_active_) {
if (vortex_->csr_io_req_valid && csr_io_req_ready_) {
if (vortex_->csr_req_valid && csr_req_ready_) {
#ifndef NDEBUG
if (vortex_->csr_io_req_rw)
std::cout << std::dec << timestamp << ": [sim] CSR Wr Req: core=" << (int)vortex_->csr_io_req_coreid << ", addr=" << std::hex << vortex_->csr_io_req_addr << ", value=" << vortex_->csr_io_req_data << std::endl;
if (vortex_->csr_req_rw)
std::cout << std::dec << timestamp << ": [sim] CSR Wr Req: core=" << (int)vortex_->csr_req_coreid << ", addr=" << std::hex << vortex_->csr_req_addr << ", value=" << vortex_->csr_req_data << std::endl;
else
std::cout << std::dec << timestamp << ": [sim] CSR Rd Req: core=" << (int)vortex_->csr_io_req_coreid << ", addr=" << std::hex << vortex_->csr_io_req_addr << std::endl;
std::cout << std::dec << timestamp << ": [sim] CSR Rd Req: core=" << (int)vortex_->csr_req_coreid << ", addr=" << std::hex << vortex_->csr_req_addr << std::endl;
#endif
vortex_->csr_io_req_valid = 0;
if (vortex_->csr_io_req_rw)
vortex_->csr_req_valid = 0;
if (vortex_->csr_req_rw)
csr_req_active_ = false;
}
if (vortex_->csr_io_rsp_valid && vortex_->csr_io_rsp_ready) {
*csr_rsp_value_ = vortex_->csr_io_rsp_data;
vortex_->csr_io_rsp_ready = 0;
if (vortex_->csr_rsp_valid && vortex_->csr_rsp_ready) {
*csr_rsp_value_ = vortex_->csr_rsp_data;
vortex_->csr_rsp_ready = 0;
csr_req_active_ = false;
#ifndef NDEBUG
std::cout << std::dec << timestamp << ": [sim] CSR Rsp: value=" << vortex_->csr_io_rsp_data << std::endl;
std::cout << std::dec << timestamp << ": [sim] CSR Rsp: value=" << vortex_->csr_rsp_data << std::endl;
#endif
}
} else {
vortex_->csr_io_req_valid = 0;
vortex_->csr_io_rsp_ready = 0;
vortex_->csr_req_valid = 0;
vortex_->csr_rsp_ready = 0;
}
}
@ -290,48 +249,27 @@ bool Simulator::is_busy() const {
return vortex_->busy;
}
bool Simulator::snp_req_active() const {
return snp_req_active_;
}
bool Simulator::csr_req_active() const {
return csr_req_active_;
}
void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
if (0 == size)
return;
assert(!vortex_->snp_rsp_valid);
vortex_->snp_req_addr = mem_addr / GLOBAL_BLOCK_SIZE;
vortex_->snp_req_tag = 0;
vortex_->snp_req_valid = 1;
vortex_->snp_rsp_ready = 1;
snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
pending_snp_reqs_ = 0;
snp_req_active_ = true;
}
void Simulator::set_csr(int core_id, int addr, unsigned value) {
vortex_->csr_io_req_valid = 1;
vortex_->csr_io_req_coreid = core_id;
vortex_->csr_io_req_addr = addr;
vortex_->csr_io_req_rw = 1;
vortex_->csr_io_req_data = value;
vortex_->csr_io_rsp_ready = 0;
vortex_->csr_req_valid = 1;
vortex_->csr_req_coreid = core_id;
vortex_->csr_req_addr = addr;
vortex_->csr_req_rw = 1;
vortex_->csr_req_data = value;
vortex_->csr_rsp_ready = 0;
csr_req_active_ = true;
}
void Simulator::get_csr(int core_id, int addr, unsigned *value) {
vortex_->csr_io_req_valid = 1;
vortex_->csr_io_req_coreid = core_id;
vortex_->csr_io_req_addr = addr;
vortex_->csr_io_req_rw = 0;
vortex_->csr_io_rsp_ready = 1;
vortex_->csr_req_valid = 1;
vortex_->csr_req_coreid = core_id;
vortex_->csr_req_addr = addr;
vortex_->csr_req_rw = 0;
vortex_->csr_rsp_ready = 1;
csr_rsp_value_ = value;

11
hw/simulate/simulator.h
View file

@ -30,14 +30,12 @@ public:
bool is_busy() const;
bool snp_req_active() const;
bool csr_req_active() const;
void reset();
void step();
void wait(uint32_t cycles);
void flush_caches(uint32_t mem_addr, uint32_t size);
void set_csr(int core_id, int addr, unsigned value);
void get_csr(int core_id, int addr, unsigned *value);
@ -62,20 +60,13 @@ private:
void eval_dram_bus();
void eval_io_bus();
void eval_csr_bus();
void eval_snp_bus();
std::list<dram_req_t> dram_rsp_vec_;
bool dram_rsp_active_;
bool dram_rsp_ready_;
bool snp_req_ready_;
bool csr_io_req_ready_;
bool snp_req_active_;
bool csr_req_ready_;
bool csr_req_active_;
uint32_t snp_req_size_;
uint32_t pending_snp_reqs_;
uint32_t* csr_rsp_value_;
RAM *ram_;