mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-25 06:17:38 -04:00
385 lines
No EOL
9.3 KiB
C++
385 lines
No EOL
9.3 KiB
C++
#include "simulator.h"
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 24
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#define DRAM_RQ_SIZE 16
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#define DRAM_STALLS_MODULO 16
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#define VL_WDATA_GETW(lwp, i, n, w) \
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VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w)
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uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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Simulator::Simulator() {
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// force random values for unitialized signals
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Verilated::randReset(2);
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Verilated::randSeed(50);
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// Turn off assertion before reset
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Verilated::assertOn(false);
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ram_ = nullptr;
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vortex_ = new VVortex();
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC();
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vortex_->trace(trace_, 99);
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trace_->open("trace.vcd");
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#endif
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// reset the device
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this->reset();
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}
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Simulator::~Simulator() {
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for (auto& buf : print_bufs_) {
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auto str = buf.second.str();
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if (str.size()) {
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std::cout << "#" << buf.first << ": " << buf.second.str() << std::endl;
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}
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}
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#ifdef VCD_OUTPUT
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trace_->close();
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#endif
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delete vortex_;
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}
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void Simulator::attach_ram(RAM* ram) {
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ram_ = ram;
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dram_rsp_vec_.clear();
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}
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void Simulator::reset() {
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print_bufs_.clear();
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dram_rsp_vec_.clear();
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dram_rsp_active_ = false;
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csr_req_active_ = false;
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csr_rsp_value_ = nullptr;
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vortex_->dram_rsp_valid = 0;
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vortex_->dram_req_ready = 0;
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//vortex_->io_req_ready = 0;
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//vortex_->io_rsp_valid = 0;
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vortex_->csr_req_valid = 0;
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vortex_->csr_rsp_ready = 0;
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vortex_->reset = 1;
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vortex_->clk = 0;
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this->eval();
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vortex_->clk = 1;
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this->eval();
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vortex_->reset = 0;
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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void Simulator::step() {
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vortex_->clk = 0;
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this->eval();
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dram_rsp_ready_ = vortex_->dram_rsp_ready;
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csr_req_ready_ = vortex_->csr_req_ready;
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vortex_->clk = 1;
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this->eval();
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this->eval_dram_bus();
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this->eval_io_bus();
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this->eval_csr_bus();
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#ifndef NDEBUG
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fflush(stdout);
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#endif
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}
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void Simulator::eval() {
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vortex_->eval();
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#ifdef VCD_OUTPUT
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trace_->dump(timestamp);
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#endif
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++timestamp;
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}
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void Simulator::eval_dram_bus() {
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if (ram_ == nullptr) {
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vortex_->dram_req_ready = 0;
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return;
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}
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// update DRAM responses schedule
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for (auto& rsp : dram_rsp_vec_) {
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if (rsp.cycles_left > 0)
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rsp.cycles_left -= 1;
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}
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// schedule DRAM responses in FIFO order
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std::list<dram_req_t>::iterator dram_rsp_it(dram_rsp_vec_.end());
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if (!dram_rsp_vec_.empty()
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&& (0 == dram_rsp_vec_.begin()->cycles_left)) {
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dram_rsp_it = dram_rsp_vec_.begin();
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}
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// send DRAM response
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if (dram_rsp_active_
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&& vortex_->dram_rsp_valid && dram_rsp_ready_) {
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dram_rsp_active_ = false;
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}
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if (!dram_rsp_active_) {
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if (dram_rsp_it != dram_rsp_vec_.end()) {
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vortex_->dram_rsp_valid = 1;
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memcpy((uint8_t*)vortex_->dram_rsp_data, dram_rsp_it->block.data(), GLOBAL_BLOCK_SIZE);
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vortex_->dram_rsp_tag = dram_rsp_it->tag;
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dram_rsp_vec_.erase(dram_rsp_it);
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dram_rsp_active_ = true;
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} else {
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vortex_->dram_rsp_valid = 0;
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}
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}
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// handle DRAM stalls
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bool dram_stalled = false;
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#ifdef ENABLE_DRAM_STALLS
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if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) {
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dram_stalled = true;
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} else
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if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) {
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dram_stalled = true;
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}
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#endif
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// process DRAM requests
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if (!dram_stalled) {
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if (vortex_->dram_req_valid) {
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if (vortex_->dram_req_rw) {
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uint64_t byteen = vortex_->dram_req_byteen;
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unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
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uint8_t* data = (uint8_t*)(vortex_->dram_req_data);
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for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
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}
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}
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} else {
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dram_req_t dram_req;
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dram_req.tag = vortex_->dram_req_tag;
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dram_req.addr = vortex_->dram_req_addr;
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ram_->read(vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.block.data());
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dram_req.cycles_left = DRAM_LATENCY;
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for (auto& rsp : dram_rsp_vec_) {
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if (dram_req.addr == rsp.addr) {
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dram_req.cycles_left = rsp.cycles_left;
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break;
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}
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}
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dram_rsp_vec_.emplace_back(dram_req);
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}
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}
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}
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vortex_->dram_req_ready = !dram_stalled;
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}
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void Simulator::eval_io_bus() {
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/*for (int i = 0; i < NUM_THREADS; ++i) {
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if (((vortex_->io_req_valid >> i) & 0x1)
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&& ((VL_WDATA_GETW(vortex_->io_req_addr, i, NUM_THREADS, 30) << 2) == IO_BUS_ADDR_COUT)) {
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assert(vortex_->io_req_rw);
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int data = vortex_->io_req_data[i];
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int tid = data >> 16;
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char c = data & 0xff;
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auto& ss_buf = print_bufs_[tid];
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ss_buf << c;
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if (c == '\n') {
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std::cout << std::dec << "#" << tid << ": " << ss_buf.str() << std::flush;
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ss_buf.str("");
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}
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}
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}
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vortex_->io_req_ready = 1;
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vortex_->io_rsp_valid = 0;*/
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}
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void Simulator::eval_csr_bus() {
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if (csr_req_active_) {
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if (vortex_->csr_req_valid && csr_req_ready_) {
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#ifndef NDEBUG
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if (vortex_->csr_req_rw)
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std::cout << std::dec << timestamp << ": [sim] CSR Wr Req: core=" << (int)vortex_->csr_req_coreid << ", addr=" << std::hex << vortex_->csr_req_addr << ", value=" << vortex_->csr_req_data << std::endl;
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else
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std::cout << std::dec << timestamp << ": [sim] CSR Rd Req: core=" << (int)vortex_->csr_req_coreid << ", addr=" << std::hex << vortex_->csr_req_addr << std::endl;
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#endif
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vortex_->csr_req_valid = 0;
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if (vortex_->csr_req_rw)
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csr_req_active_ = false;
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}
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if (vortex_->csr_rsp_valid && vortex_->csr_rsp_ready) {
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*csr_rsp_value_ = vortex_->csr_rsp_data;
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vortex_->csr_rsp_ready = 0;
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csr_req_active_ = false;
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#ifndef NDEBUG
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std::cout << std::dec << timestamp << ": [sim] CSR Rsp: value=" << vortex_->csr_rsp_data << std::endl;
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#endif
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}
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} else {
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vortex_->csr_req_valid = 0;
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vortex_->csr_rsp_ready = 0;
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}
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}
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void Simulator::wait(uint32_t cycles) {
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for (int i = 0; i < cycles; ++i) {
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this->step();
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}
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}
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bool Simulator::is_busy() const {
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return vortex_->busy;
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}
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bool Simulator::csr_req_active() const {
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return csr_req_active_;
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}
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void Simulator::set_csr(int core_id, int addr, unsigned value) {
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vortex_->csr_req_valid = 1;
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vortex_->csr_req_coreid = core_id;
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vortex_->csr_req_addr = addr;
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vortex_->csr_req_rw = 1;
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vortex_->csr_req_data = value;
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vortex_->csr_rsp_ready = 0;
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csr_req_active_ = true;
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}
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void Simulator::get_csr(int core_id, int addr, unsigned *value) {
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vortex_->csr_req_valid = 1;
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vortex_->csr_req_coreid = core_id;
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vortex_->csr_req_addr = addr;
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vortex_->csr_req_rw = 0;
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vortex_->csr_rsp_ready = 1;
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csr_rsp_value_ = value;
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csr_req_active_ = true;
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}
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void Simulator::run() {
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#ifndef NDEBUG
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std::cout << std::dec << timestamp << ": [sim] run()" << std::endl;
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#endif
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// execute program
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while (vortex_->busy
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&& !vortex_->ebreak) {
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this->step();
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}
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// wait 5 cycles to flush the pipeline
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this->wait(5);
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}
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int Simulator::get_last_wb_value(int reg) const {
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return (int)vortex_->Vortex->genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
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}
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void Simulator::load_bin(const char* program_file) {
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if (ram_ == nullptr)
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return;
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std::ifstream ifs(program_file);
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if (!ifs) {
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std::cout << "error: " << program_file << " not found" << std::endl;
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}
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ifs.seekg(0, ifs.end);
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auto size = ifs.tellg();
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std::vector<uint8_t> content(size);
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ifs.seekg(0, ifs.beg);
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ifs.read((char*)content.data(), size);
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ram_->write(STARTUP_ADDR, size, content.data());
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}
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void Simulator::load_ihex(const char* program_file) {
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if (ram_ == nullptr)
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return;
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auto hti = [&](char c)->uint32_t {
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if (c >= 'A' && c <= 'F')
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return c - 'A' + 10;
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if (c >= 'a' && c <= 'f')
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return c - 'a' + 10;
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return c - '0';
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};
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auto hToI = [&](const char *c, uint32_t size)->uint32_t {
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uint32_t value = 0;
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for (uint32_t i = 0; i < size; i++) {
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value += hti(c[i]) << ((size - i - 1) * 4);
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}
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return value;
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};
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std::ifstream ifs(program_file);
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if (!ifs) {
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std::cout << "error: " << program_file << " not found" << std::endl;
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}
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ifs.seekg(0, ifs.end);
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uint32_t size = ifs.tellg();
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std::vector<char> content(size);
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ifs.seekg(0, ifs.beg);
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ifs.read(content.data(), size);
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int offset = 0;
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char *line = content.data();
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while (true) {
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if (line[0] == ':') {
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uint32_t byteCount = hToI(line + 1, 2);
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uint32_t nextAddr = hToI(line + 3, 4) + offset;
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uint32_t key = hToI(line + 7, 2);
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switch (key) {
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case 0:
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for (uint32_t i = 0; i < byteCount; i++) {
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(*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2);
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}
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break;
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case 2:
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offset = hToI(line + 9, 4) << 4;
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break;
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case 4:
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offset = hToI(line + 9, 4) << 16;
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break;
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default:
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break;
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}
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}
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while (*line != '\n' && size != 0) {
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++line;
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--size;
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}
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if (size <= 1)
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break;
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++line;
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--size;
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}
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}
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void Simulator::print_stats(std::ostream& out) {
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out << std::left;
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out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl;
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} |