mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
fixed opencl benchmarks
This commit is contained in:
Blaise Tine
parent
857bb54f3f
commit
717a75ade8
64 changed files with 235418 additions and 1511751 deletions
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@ -62,12 +62,11 @@ Basic Instructions to build the OpenCL Compiler for Vortex
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Build LLVM for RiscV
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$ git clone -b release_90 https://github.com/llvm-mirror/llvm.git llvm
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$ git clone -b release_90 https://github.com/llvm-mirror/clang.git llvm/tools/clang
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$ git clone -b release/10.x https://github.com/llvm/llvm-project.git llvm
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$ cd llvm
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$ mkdir build
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$ cd build
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$ cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DBUILD_SHARED_LIBS=True -DLLVM_USE_SPLIT_DWARF=True -DCMAKE_INSTALL_PREFIX=$RISC_GNU_TOOLS_PATH -DLLVM_OPTIMIZED_TABLEGEN=True -DLLVM_BUILD_TESTS=True -DDEFAULT_SYSROOT=$RISC_GNU_TOOLS_PATH/riscv32-unknown-elf -DLLVM_DEFAULT_TARGET_TRIPLE="riscv32-unknown-elf" -DLLVM_TARGETS_TO_BUILD="RISCV" ..
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$ cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_ENABLE_PROJECTS="clang" -DBUILD_SHARED_LIBS=True -DLLVM_USE_SPLIT_DWARF=True -DCMAKE_INSTALL_PREFIX=$RISC_GNU_TOOLS_PATH -DLLVM_OPTIMIZED_TABLEGEN=True -DLLVM_BUILD_TESTS=True -DDEFAULT_SYSROOT=$RISC_GNU_TOOLS_PATH/riscv32-unknown-elf -DLLVM_DEFAULT_TARGET_TRIPLE="riscv32-unknown-elf" -DLLVM_TARGETS_TO_BUILD="RISCV" ..
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$ cmake --build . --target install
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Build pocl for RISCV
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@ -78,8 +77,8 @@ Build pocl for RISCV
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$ cd build
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$ export POCL_CC_PATH=$PWD/../drops_riscv_cc
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$ export POCL_RT_PATH=$PWD/../drops_riscv_rt
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$ cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_CC_PATH -DCMAKE_BUILD_TYPE=Debug -DWITH_LLVM_CONFIG=$RISC_GNU_TOOLS_PATH/bin/llvm-config -DLLC_HOST_CPU= -DNEWLIB_BSP=ON -DNEWLIB_DEVICE_ADDRESS_BIT=32 -DBUILD_TESTS=OFF -DPOCL_DEBUG_MESSAGES=ON ..
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$ cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_CC_PATH -DCMAKE_BUILD_TYPE=Debug -DWITH_LLVM_CONFIG=$RISC_GNU_TOOLS_PATH/bin/llvm-config -DNEWLIB_BSP=ON -DNEWLIB_DEVICE_ADDRESS_BIT=32 -DNEWLIB_DEVICE_MARCH=rv32im -DBUILD_TESTS=OFF -DPOCL_DEBUG_MESSAGES=ON ..
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$ cmake --build . --target install
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$ rm -rf *
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$ cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_RT_PATH -DCMAKE_BUILD_TYPE=Debug -DOCS_AVAILABLE=OFF -DBUILD_SHARED_LIBS=OFF -DNEWLIB_BSP=ON -DNEWLIB_DEVICE_ADDRESS_BIT=32 -DBUILD_TESTS=OFF -DHOST_DEVICE_BUILD_HASH=basic-riscv32-unknown-elf -DCMAKE_TOOLCHAIN_FILE=../RISCV_newlib.cmake -DENABLE_TRACING=OFF -DENABLE_ICD=OFF -DPOCL_DEBUG_MESSAGES=ON ..
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$ cmake -G Ninja -DCMAKE_INSTALL_PREFIX=$POCL_RT_PATH -DCMAKE_BUILD_TYPE=Debug -DOCS_AVAILABLE=OFF -DBUILD_SHARED_LIBS=OFF -DNEWLIB_BSP=ON -DNEWLIB_DEVICE_ADDRESS_BIT=32 -DNEWLIB_DEVICE_MARCH=rv32im -DBUILD_TESTS=OFF -DHOST_DEVICE_BUILD_HASH=basic-riscv32-unknown-elf -DCMAKE_TOOLCHAIN_FILE=../RISCV_newlib.cmake -DENABLE_TRACING=OFF -DENABLE_ICD=OFF -DPOCL_DEBUG_MESSAGES=ON ..
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$ cmake --build . --target install
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@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
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CXXFLAGS += -I$(POCL_INC_PATH) -I.
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VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
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QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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PROJECT=BlackScholes
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@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
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CXXFLAGS += -I$(POCL_INC_PATH) -I.
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VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
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QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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PROJECT=DotProduct
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@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
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CXXFLAGS += -I$(POCL_INC_PATH) -I.
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VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
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QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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PROJECT=VectorHypot
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@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
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CXXFLAGS += -I$(POCL_INC_PATH)
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VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
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QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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PROJECT = bfs
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68
benchmarks/opencl/convolution/Makefile
Normal file
68
benchmarks/opencl/convolution/Makefile
Normal file
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@ -0,0 +1,68 @@
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RISCV_TOOL_PATH ?= $(wildcard ../../../../riscv-gnu-toolchain/drops)
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POCL_CC_PATH ?= $(wildcard ../../../../pocl/drops_riscv_cc)
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POCL_INC_PATH ?= $(wildcard ../include)
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POCL_LIB_PATH ?= $(wildcard ../lib)
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VX_RT_PATH ?= $(wildcard ../../../runtime)
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VX_SIMX_PATH ?= $(wildcard ../../../simX/obj_dir)
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CC = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-gcc
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CXX = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-g++
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DMP = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-objdump
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HEX = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-objcopy
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GDB = $(RISCV_TOOL_PATH)/bin/riscv32-unknown-elf-gdb
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VX_SRCS = $(VX_RT_PATH)/newlib/newlib.c
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VX_SRCS += $(VX_RT_PATH)/startup/vx_start.s
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VX_SRCS += $(VX_RT_PATH)/intrinsics/vx_intrinsics.s
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VX_SRCS += $(VX_RT_PATH)/io/vx_io.s $(VX_RT_PATH)/io/vx_io.c
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VX_SRCS += $(VX_RT_PATH)/fileio/fileio.s
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VX_SRCS += $(VX_RT_PATH)/tests/tests.c
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VX_SRCS += $(VX_RT_PATH)/vx_api/vx_api.c
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VX_SRCS += $(VX_STR) $(VX_FIO) $(VX_NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST)
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VX_CFLAGS = -nostartfiles -Wl,-Bstatic,-T,$(VX_RT_PATH)/mains/vortex_link.ld
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CXXFLAGS = -g -O0 -march=rv32im -mabi=ilp32
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CXXFLAGS += -ffreestanding # program may not begin at main()
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CXXFLAGS += -Wl,--gc-sections # enable garbage collection of unused input sections
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CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
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CXXFLAGS += -I$(POCL_INC_PATH)
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VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
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PROJECT = convolution
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SRCS = main.cpp utils.cpp
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all: $(PROJECT).dump $(PROJECT).hex
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lib$(PROJECT).a: kernel.cl
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POCL_DEBUG=all POCL_DEBUG_LLVM_PASSES=1 LD_LIBRARY_PATH=$(RISCV_TOOL_PATH)/lib:$(POCL_CC_PATH)/lib $(POCL_CC_PATH)/bin/poclcc -o lib$(PROJECT).a kernel.cl
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$(PROJECT).elf: $(SRCS) lib$(PROJECT).a
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$(CXX) $(CXXFLAGS) $(VX_CFLAGS) $(VX_SRCS) $(SRCS) $(VX_LIBS) -o $(PROJECT).elf
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$(PROJECT).qemu: $(SRCS) lib$(PROJECT).a
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$(CXX) $(CXXFLAGS) $(SRCS) $(QEMU_LIBS) -o $(PROJECT).qemu
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$(PROJECT).hex: $(PROJECT).elf
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$(HEX) -O ihex $(PROJECT).elf $(PROJECT).hex
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$(PROJECT).dump: $(PROJECT).elf
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$(DMP) -D $(PROJECT).elf > $(PROJECT).dump
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run: $(PROJECT).hex
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POCL_DEBUG=all $(VX_SIMX_PATH)/Vcache_simX -E -a rv32i --core $(PROJECT).hex -s -b 1> emulator.debug
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qemu: $(PROJECT).qemu
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POCL_DEBUG=all $(RISCV_TOOL_PATH)/bin/qemu-riscv32 -d in_asm -D debug.log $(PROJECT).qemu
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gdb-s: $(PROJECT).qemu
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POCL_DEBUG=all $(RISCV_TOOL_PATH)/bin/qemu-riscv32 -g 1234 -d in_asm -D debug.log $(PROJECT).qemu
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gdb-c: $(PROJECT).qemu
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$(GDB) $(PROJECT).qemu
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clean:
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rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug
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BIN
benchmarks/opencl/convolution/input.bmp
Normal file
BIN
benchmarks/opencl/convolution/input.bmp
Normal file
Binary file not shown.
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After Width: | Height: | Size: 44 KiB |
54
benchmarks/opencl/convolution/kernel.cl
Executable file
54
benchmarks/opencl/convolution/kernel.cl
Executable file
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@ -0,0 +1,54 @@
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__kernel
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void convolution(
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__read_only image2d_t sourceImage,
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__write_only image2d_t outputImage,
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int rows,
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int cols,
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__constant float* filter,
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int filterWidth,
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sampler_t sampler)
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{
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// Store each work-item’s unique row and column
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int column = get_global_id(0);
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int row = get_global_id(1);
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// Half the width of the filter is needed for indexing
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// memory later
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int halfWidth = (int)(filterWidth/2);
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// All accesses to images return data as four-element vector
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// (i.e., float4), although only the 'x' component will contain
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// meaningful data in this code
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float4 sum = {0.0f, 0.0f, 0.0f, 0.0f};
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// Iterator for the filter
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int filterIdx = 0;
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// Each work-item iterates around its local area based on the
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// size of the filter
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int2 coords; // Coordinates for accessing the image
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// Iterate the filter rows
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for(int i = -halfWidth; i <= halfWidth; i++) {
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coords.y = row + i;
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// Iterate over the filter columns
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for(int j = -halfWidth; j <= halfWidth; j++) {
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coords.x = column + j;
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float4 pixel;
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// Read a pixel from the image. A single channel image
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// stores the pixel in the 'x' coordinate of the returned
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// vector.
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pixel = read_imagef(sourceImage, sampler, coords);
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sum.x += pixel.x * filter[filterIdx++];
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}
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}
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// Copy the data to the output image if the
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// work-item is in bounds
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if(row < rows && column < cols) {
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coords.x = column;
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coords.y = row;
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write_imagef(outputImage, coords, sum);
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}
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}
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261
benchmarks/opencl/convolution/main.cpp
Executable file
261
benchmarks/opencl/convolution/main.cpp
Executable file
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@ -0,0 +1,261 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <CL/cl.h>
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#include "utils.h"
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// This function takes a positive integer and rounds it up to
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// the nearest multiple of another provided integer
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unsigned int roundUp(unsigned int value, unsigned int multiple) {
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// Determine how far past the nearest multiple the value is
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unsigned int remainder = value % multiple;
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// Add the difference to make the value a multiple
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if(remainder != 0) {
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value += (multiple-remainder);
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}
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return value;
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}
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// This function reads in a text file and stores it as a char pointer
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char* readSource(char* kernelPath) {
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cl_int status;
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FILE *fp;
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char *source;
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long int size;
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printf("Program file is: %s\n", kernelPath);
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fp = fopen(kernelPath, "rb");
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if(!fp) {
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printf("Could not open kernel file\n");
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exit(-1);
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}
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status = fseek(fp, 0, SEEK_END);
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if(status != 0) {
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printf("Error seeking to end of file\n");
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exit(-1);
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}
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size = ftell(fp);
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if(size < 0) {
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printf("Error getting file position\n");
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exit(-1);
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}
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rewind(fp);
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source = (char *)malloc(size + 1);
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int i;
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for (i = 0; i < size+1; i++) {
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source[i]='\0';
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}
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if(source == NULL) {
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printf("Error allocating space for the kernel source\n");
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exit(-1);
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}
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fread(source, 1, size, fp);
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source[size] = '\0';
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return source;
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}
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void chk(cl_int status, const char* cmd) {
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if(status != CL_SUCCESS) {
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printf("%s failed (%d)\n", cmd, status);
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exit(-1);
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}
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}
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int main() {
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int i, j, k, l;
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// Rows and columns in the input image
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int imageHeight;
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int imageWidth;
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const char* inputFile = "input.bmp";
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const char* outputFile = "output.bmp";
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// Homegrown function to read a BMP from file
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float* inputImage = readImage(inputFile, &imageWidth,
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&imageHeight);
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// Size of the input and output images on the host
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int dataSize = imageHeight*imageWidth*sizeof(float);
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// Output image on the host
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float* outputImage = NULL;
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outputImage = (float*)malloc(dataSize);
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float* refImage = NULL;
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refImage = (float*)malloc(dataSize);
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// 45 degree motion blur
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float filter[49] =
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{0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0,
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0, 0, -1, 0, 1, 0, 0,
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0, 0, -2, 0, 2, 0, 0,
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0, 0, -1, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0};
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// The convolution filter is 7x7
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int filterWidth = 7;
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int filterSize = filterWidth*filterWidth; // Assume a square kernel
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// Set up the OpenCL environment
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cl_int status;
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// Discovery platform
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cl_platform_id platform;
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status = clGetPlatformIDs(1, &platform, NULL);
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chk(status, "clGetPlatformIDs");
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// Discover device
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cl_device_id device;
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clGetDeviceIDs(platform, CL_DEVICE_TYPE_ALL, 1, &device, NULL);
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chk(status, "clGetDeviceIDs");
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// Create context
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cl_context_properties props[3] = {CL_CONTEXT_PLATFORM,
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(cl_context_properties)(platform), 0};
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cl_context context;
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context = clCreateContext(props, 1, &device, NULL, NULL, &status);
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chk(status, "clCreateContext");
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// Create command queue
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cl_command_queue queue;
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queue = clCreateCommandQueue(context, device, 0, &status);
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chk(status, "clCreateCommandQueue");
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// The image format describes how the data will be stored in memory
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cl_image_format format;
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format.image_channel_order = CL_R; // single channel
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format.image_channel_data_type = CL_FLOAT; // float data type
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// Create space for the source image on the device
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cl_mem d_inputImage = clCreateImage2D(context, 0, &format, imageWidth,
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imageHeight, 0, NULL, &status);
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chk(status, "clCreateImage2D");
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// Create space for the output image on the device
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cl_mem d_outputImage = clCreateImage2D(context, 0, &format, imageWidth,
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imageHeight, 0, NULL, &status);
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chk(status, "clCreateImage2D");
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// Create space for the 7x7 filter on the device
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cl_mem d_filter = clCreateBuffer(context, 0, filterSize*sizeof(float),
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NULL, &status);
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chk(status, "clCreateBuffer");
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// Copy the source image to the device
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size_t origin[3] = {0, 0, 0}; // Offset within the image to copy from
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size_t region[3] = {imageWidth, imageHeight, 1}; // Elements to per dimension
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status = clEnqueueWriteImage(queue, d_inputImage, CL_FALSE, origin, region,
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0, 0, inputImage, 0, NULL, NULL);
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chk(status, "clEnqueueWriteImage");
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// Copy the 7x7 filter to the device
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status = clEnqueueWriteBuffer(queue, d_filter, CL_FALSE, 0,
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filterSize*sizeof(float), filter, 0, NULL, NULL);
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chk(status, "clEnqueueWriteBuffer");
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// Create the image sampler
|
||||
cl_sampler sampler = clCreateSampler(context, CL_FALSE,
|
||||
CL_ADDRESS_CLAMP_TO_EDGE, CL_FILTER_NEAREST, &status);
|
||||
chk(status, "clCreateSampler");
|
||||
|
||||
const char* source = readSource("kernel.cl");
|
||||
|
||||
// Create a program object with source and build it
|
||||
cl_program program;
|
||||
program = clCreateProgramWithSource(context, 1, &source, NULL, NULL);
|
||||
chk(status, "clCreateProgramWithSource");
|
||||
status = clBuildProgram(program, 1, &device, NULL, NULL, NULL);
|
||||
chk(status, "clBuildProgram");
|
||||
|
||||
// Create the kernel object
|
||||
cl_kernel kernel;
|
||||
kernel = clCreateKernel(program, "convolution", &status);
|
||||
chk(status, "clCreateKernel");
|
||||
|
||||
// Set the kernel arguments
|
||||
status = clSetKernelArg(kernel, 0, sizeof(cl_mem), &d_inputImage);
|
||||
status |= clSetKernelArg(kernel, 1, sizeof(cl_mem), &d_outputImage);
|
||||
status |= clSetKernelArg(kernel, 2, sizeof(int), &imageHeight);
|
||||
status |= clSetKernelArg(kernel, 3, sizeof(int), &imageWidth);
|
||||
status |= clSetKernelArg(kernel, 4, sizeof(cl_mem), &d_filter);
|
||||
status |= clSetKernelArg(kernel, 5, sizeof(int), &filterWidth);
|
||||
status |= clSetKernelArg(kernel, 6, sizeof(cl_sampler), &sampler);
|
||||
chk(status, "clSetKernelArg");
|
||||
|
||||
// Set the work item dimensions
|
||||
size_t globalSize[2] = {imageWidth, imageHeight};
|
||||
status = clEnqueueNDRangeKernel(queue, kernel, 2, NULL, globalSize, NULL, 0,
|
||||
NULL, NULL);
|
||||
chk(status, "clEnqueueNDRange");
|
||||
|
||||
// Read the image back to the host
|
||||
status = clEnqueueReadImage(queue, d_outputImage, CL_TRUE, origin,
|
||||
region, 0, 0, outputImage, 0, NULL, NULL);
|
||||
chk(status, "clEnqueueReadImage");
|
||||
|
||||
// Write the output image to file
|
||||
storeImage(outputImage, outputFile, imageHeight, imageWidth, inputFile);
|
||||
|
||||
// Compute the reference image
|
||||
for(i = 0; i < imageHeight; i++) {
|
||||
for(j = 0; j < imageWidth; j++) {
|
||||
refImage[i*imageWidth+j] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Iterate over the rows of the source image
|
||||
int halfFilterWidth = filterWidth/2;
|
||||
float sum;
|
||||
for(i = 0; i < imageHeight; i++) {
|
||||
// Iterate over the columns of the source image
|
||||
for(j = 0; j < imageWidth; j++) {
|
||||
sum = 0; // Reset sum for new source pixel
|
||||
// Apply the filter to the neighborhood
|
||||
for(k = - halfFilterWidth; k <= halfFilterWidth; k++) {
|
||||
for(l = - halfFilterWidth; l <= halfFilterWidth; l++) {
|
||||
if(i+k >= 0 && i+k < imageHeight &&
|
||||
j+l >= 0 && j+l < imageWidth) {
|
||||
sum += inputImage[(i+k)*imageWidth + j+l] *
|
||||
filter[(k+halfFilterWidth)*filterWidth +
|
||||
l+halfFilterWidth];
|
||||
}
|
||||
}
|
||||
}
|
||||
refImage[i*imageWidth+j] = sum;
|
||||
}
|
||||
}
|
||||
|
||||
int failed = 0;
|
||||
for(i = 0; i < imageHeight; i++) {
|
||||
for(j = 0; j < imageWidth; j++) {
|
||||
if(abs(outputImage[i*imageWidth+j]-refImage[i*imageWidth+j]) > 0.01) {
|
||||
printf("Results are INCORRECT\n");
|
||||
printf("Pixel mismatch at <%d,%d> (%f vs. %f)\n", i, j,
|
||||
outputImage[i*imageWidth+j], refImage[i*imageWidth+j]);
|
||||
failed = 1;
|
||||
}
|
||||
if(failed) break;
|
||||
}
|
||||
if(failed) break;
|
||||
}
|
||||
if(!failed) {
|
||||
printf("Results are correct\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
180
benchmarks/opencl/convolution/utils.cpp
Normal file
180
benchmarks/opencl/convolution/utils.cpp
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "utils.h"
|
||||
|
||||
void storeImage(float *imageOut,
|
||||
const char *filename,
|
||||
int rows,
|
||||
int cols,
|
||||
const char* refFilename) {
|
||||
|
||||
FILE *ifp, *ofp;
|
||||
unsigned char tmp;
|
||||
int offset;
|
||||
unsigned char *buffer;
|
||||
int i, j;
|
||||
|
||||
int bytes;
|
||||
|
||||
int height, width;
|
||||
|
||||
ifp = fopen(refFilename, "rb");
|
||||
if(ifp == NULL) {
|
||||
perror(filename);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
fseek(ifp, 10, SEEK_SET);
|
||||
fread(&offset, 4, 1, ifp);
|
||||
|
||||
fseek(ifp, 18, SEEK_SET);
|
||||
fread(&width, 4, 1, ifp);
|
||||
fread(&height, 4, 1, ifp);
|
||||
|
||||
fseek(ifp, 0, SEEK_SET);
|
||||
|
||||
buffer = (unsigned char *)malloc(offset);
|
||||
if(buffer == NULL) {
|
||||
perror("malloc");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
fread(buffer, 1, offset, ifp);
|
||||
|
||||
printf("Writing output image to %s\n", filename);
|
||||
ofp = fopen(filename, "wb");
|
||||
if(ofp == NULL) {
|
||||
perror("opening output file");
|
||||
exit(-1);
|
||||
}
|
||||
bytes = fwrite(buffer, 1, offset, ofp);
|
||||
if(bytes != offset) {
|
||||
printf("error writing header!\n");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
// NOTE bmp formats store data in reverse raster order (see comment in
|
||||
// readImage function), so we need to flip it upside down here.
|
||||
int mod = width % 4;
|
||||
if(mod != 0) {
|
||||
mod = 4 - mod;
|
||||
}
|
||||
// printf("mod = %d\n", mod);
|
||||
for(i = height-1; i >= 0; i--) {
|
||||
for(j = 0; j < width; j++) {
|
||||
tmp = (unsigned char)imageOut[i*cols+j];
|
||||
fwrite(&tmp, sizeof(char), 1, ofp);
|
||||
}
|
||||
// In bmp format, rows must be a multiple of 4-bytes.
|
||||
// So if we're not at a multiple of 4, add junk padding.
|
||||
for(j = 0; j < mod; j++) {
|
||||
fwrite(&tmp, sizeof(char), 1, ofp);
|
||||
}
|
||||
}
|
||||
|
||||
fclose(ofp);
|
||||
fclose(ifp);
|
||||
|
||||
free(buffer);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read bmp image and convert to byte array. Also output the width and height
|
||||
*/
|
||||
float* readImage(const char *filename, int* widthOut, int* heightOut) {
|
||||
|
||||
uchar* imageData;
|
||||
|
||||
int height, width;
|
||||
uchar tmp;
|
||||
int offset;
|
||||
int i, j;
|
||||
|
||||
printf("Reading input image from %s\n", filename);
|
||||
FILE *fp = fopen(filename, "rb");
|
||||
if(fp == NULL) {
|
||||
perror(filename);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
fseek(fp, 10, SEEK_SET);
|
||||
fread(&offset, 4, 1, fp);
|
||||
|
||||
fseek(fp, 18, SEEK_SET);
|
||||
fread(&width, 4, 1, fp);
|
||||
fread(&height, 4, 1, fp);
|
||||
|
||||
printf("width = %d\n", width);
|
||||
printf("height = %d\n", height);
|
||||
|
||||
*widthOut = width;
|
||||
*heightOut = height;
|
||||
|
||||
imageData = (uchar*)malloc(width*height);
|
||||
if(imageData == NULL) {
|
||||
perror("malloc");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
fseek(fp, offset, SEEK_SET);
|
||||
fflush(NULL);
|
||||
|
||||
int mod = width % 4;
|
||||
if(mod != 0) {
|
||||
mod = 4 - mod;
|
||||
}
|
||||
|
||||
// NOTE bitmaps are stored in upside-down raster order. So we begin
|
||||
// reading from the bottom left pixel, then going from left-to-right,
|
||||
// read from the bottom to the top of the image. For image analysis,
|
||||
// we want the image to be right-side up, so we'll modify it here.
|
||||
|
||||
// First we read the image in upside-down
|
||||
|
||||
// Read in the actual image
|
||||
for(i = 0; i < height; i++) {
|
||||
|
||||
// add actual data to the image
|
||||
for(j = 0; j < width; j++) {
|
||||
fread(&tmp, sizeof(char), 1, fp);
|
||||
imageData[i*width + j] = tmp;
|
||||
}
|
||||
// For the bmp format, each row has to be a multiple of 4,
|
||||
// so I need to read in the junk data and throw it away
|
||||
for(j = 0; j < mod; j++) {
|
||||
fread(&tmp, sizeof(char), 1, fp);
|
||||
}
|
||||
}
|
||||
|
||||
// Then we flip it over
|
||||
int flipRow;
|
||||
for(i = 0; i < height/2; i++) {
|
||||
flipRow = height - (i+1);
|
||||
for(j = 0; j < width; j++) {
|
||||
tmp = imageData[i*width+j];
|
||||
imageData[i*width+j] = imageData[flipRow*width+j];
|
||||
imageData[flipRow*width+j] = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
fclose(fp);
|
||||
|
||||
// Input image on the host
|
||||
float* floatImage = NULL;
|
||||
floatImage = (float*)malloc(sizeof(float)*width*height);
|
||||
if(floatImage == NULL) {
|
||||
perror("malloc");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
// Convert the BMP image to float (not required)
|
||||
for(i = 0; i < height; i++) {
|
||||
for(j = 0; j < width; j++) {
|
||||
floatImage[i*width+j] = (float)imageData[i*width+j];
|
||||
}
|
||||
}
|
||||
|
||||
free(imageData);
|
||||
return floatImage;
|
||||
}
|
||||
11
benchmarks/opencl/convolution/utils.h
Normal file
11
benchmarks/opencl/convolution/utils.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef __UTILS__
|
||||
#define __UTILS__
|
||||
|
||||
typedef unsigned char uchar;
|
||||
|
||||
float* readImage(const char *filename, int* widthOut, int* heightOut);
|
||||
|
||||
void storeImage(float *imageOut, const char *filename, int rows, int cols,
|
||||
const char* refFilename);
|
||||
|
||||
#endif
|
||||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = cutcp
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = gaussian
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = kmeans
|
||||
SRCS = main.cc read_input.c rmse.c cluster.c kmeans_clustering.c
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = lbm
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = mri-q
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = nearn
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT=reduce0
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = sad
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = saxpy
|
||||
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ int main(int argc, char **argv) {
|
|||
}
|
||||
|
||||
cl_event kernel_completion;
|
||||
size_t global_work_size[1] = {NUM_DATA/2,NUM_DATA/2};
|
||||
size_t global_work_size[] = {NUM_DATA/2,NUM_DATA/2};
|
||||
printf("attempting to enqueue kernel\n");
|
||||
fflush(stdout);
|
||||
CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, global_work_size,
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = sfilter
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = sgemm
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = spmv
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = stencil
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH) -I.
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT=transpose
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ CXXFLAGS += -fno-rtti -fno-non-call-exceptions # disable RTTI and exceptions
|
|||
CXXFLAGS += -I$(POCL_INC_PATH)
|
||||
|
||||
VX_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
QEMU_LIBS = -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/qemu/libOpenCL.a
|
||||
QEMU_LIBS = $(VX_RT_PATH)/qemu/vx_api.c -Wl,--whole-archive lib$(PROJECT).a -Wl,--no-whole-archive $(POCL_LIB_PATH)/libOpenCL.a
|
||||
|
||||
PROJECT = vecadd
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -31,6 +31,28 @@
|
|||
_ret; \
|
||||
})
|
||||
|
||||
/*#include <cstdint>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
int _pocl_register_kernel(const char* name, const void* pfn, uint32_t num_args, uint32_t num_locals, const uint8_t* arg_types, const uint32_t* local_sizes);
|
||||
void _pocl_kernel_vecadd_workgroup(uint8_t* args, uint8_t*, uint32_t, uint32_t, uint32_t);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
namespace {
|
||||
class auto_register_kernel_t {
|
||||
public:
|
||||
auto_register_kernel_t() {
|
||||
static uint8_t arg_types[] = {1, 1, 1};
|
||||
static uint32_t local_sizes[] = {};
|
||||
_pocl_register_kernel("vecadd", (void*)_pocl_kernel_vecadd_workgroup, 3, 0, arg_types, local_sizes);
|
||||
}
|
||||
};
|
||||
static auto_register_kernel_t __x__;
|
||||
}*/
|
||||
|
||||
int exitcode = 0;
|
||||
cl_context context = NULL;
|
||||
cl_command_queue commandQueue = NULL;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Binary file not shown.
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
BIN
runtime/mains/nativevecadd/vx_pocl_main.elf
Normal file → Executable file
BIN
runtime/mains/nativevecadd/vx_pocl_main.elf
Normal file → Executable file
Binary file not shown.
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
BIN
runtime/mains/vecadd/vx_pocl_main.elf
Normal file → Executable file
BIN
runtime/mains/vecadd/vx_pocl_main.elf
Normal file → Executable file
Binary file not shown.
File diff suppressed because it is too large
Load diff
36
runtime/qemu/vx_api.c
Normal file
36
runtime/qemu/vx_api.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct pocl_context_t {
|
||||
uint32_t num_groups[3];
|
||||
uint32_t global_offset[3];
|
||||
uint32_t local_size[3];
|
||||
uint8_t *printf_buffer;
|
||||
uint32_t *printf_buffer_position;
|
||||
uint32_t printf_buffer_capacity;
|
||||
uint32_t work_dim;
|
||||
};
|
||||
|
||||
typedef void (*pocl_workgroup_func) (
|
||||
void * /* args */,
|
||||
void * /* pocl_context */,
|
||||
uint32_t /* group_x */,
|
||||
uint32_t /* group_y */,
|
||||
uint32_t /* group_z */
|
||||
);
|
||||
|
||||
void pocl_spawn(struct pocl_context_t * ctx, const pocl_workgroup_func pfn, void * arguments) {
|
||||
uint32_t x, y, z;
|
||||
for (z = 0; z < ctx->num_groups[2]; ++z)
|
||||
for (y = 0; y < ctx->num_groups[1]; ++y)
|
||||
for (x = 0; x < ctx->num_groups[0]; ++x)
|
||||
(pfn)(arguments, ctx, x, y, z);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2,8 +2,8 @@
|
|||
# HARPtools by Chad D. Kersey, Summer 2011 #
|
||||
################################################################################
|
||||
|
||||
CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
|
||||
# CXXFLAGS ?= -std=c++11 -fPIC -O0 -g -Wall -Wextra -pedantic # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
|
||||
CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
|
||||
#CXXFLAGS ?= -std=c++11 -fPIC -g -O0 -Wall -Wextra -pedantic -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
|
||||
|
||||
LIB_OBJS=simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp
|
||||
|
||||
|
|
@ -28,7 +28,7 @@ all: simX
|
|||
|
||||
simX:
|
||||
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) $(DEB)
|
||||
(cd obj_dir && make -j -f Vcache_simX.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
|
||||
(cd obj_dir && make -j`nproc` -f Vcache_simX.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
|
||||
|
||||
clean:
|
||||
rm -rf *~ \#* *.o *.a *.so include/*~ include/\#* simX.run obj_dir
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ namespace Harp {
|
|||
public:
|
||||
struct Undefined {};
|
||||
|
||||
ArchDef(const std::string &s) {
|
||||
ArchDef(const std::string &s, bool cpu_mode = false)
|
||||
: cpu_mode_(cpu_mode) {
|
||||
std::istringstream iss(s.c_str());
|
||||
|
||||
wordSize = 4;
|
||||
|
|
@ -98,6 +99,10 @@ namespace Harp {
|
|||
ThdNum getNWarps() const {
|
||||
if (extent < EXT_WARPS) throw Undefined(); else return nWarps;
|
||||
}
|
||||
|
||||
bool is_cpu_mode() const {
|
||||
return cpu_mode_;
|
||||
}
|
||||
|
||||
private:
|
||||
enum Extent {
|
||||
|
|
@ -110,6 +115,7 @@ namespace Harp {
|
|||
ThdNum nThds, nWarps;
|
||||
RegNum nRegs, nPRegs;
|
||||
char encChar;
|
||||
bool cpu_mode_;
|
||||
};
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -841,90 +841,100 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
|
|||
case SYS_INST:
|
||||
//std::cout << "SYS_INST\n";
|
||||
temp = reg[rsrc[0]];
|
||||
// if (immsrc == 0x20) // ThreadID
|
||||
// {
|
||||
// reg[rdest] = t;
|
||||
// D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]);
|
||||
// } else if (immsrc == 0x21) // WarpID
|
||||
// {
|
||||
// reg[rdest] = c.id;
|
||||
// D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]);
|
||||
// } else if (immsrc == 0x25)
|
||||
// {
|
||||
// reg[rdest] = c.core->num_instructions;
|
||||
// } else if (immsrc == 0x26)
|
||||
// {
|
||||
// reg[rdest] = c.core->num_cycles;
|
||||
// }
|
||||
switch (func3)
|
||||
{
|
||||
case 1:
|
||||
// printf("Case 1\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = temp;
|
||||
|
||||
break;
|
||||
case 2:
|
||||
// printf("Case 2\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
// printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
// printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
|
||||
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
|
||||
|
||||
break;
|
||||
case 3:
|
||||
// printf("Case 3\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
|
||||
|
||||
break;
|
||||
case 5:
|
||||
// printf("Case 5\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0];
|
||||
|
||||
break;
|
||||
case 6:
|
||||
// printf("Case 6\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
|
||||
|
||||
break;
|
||||
case 7:
|
||||
// printf("Case 7\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
|
||||
|
||||
break;
|
||||
case 0:
|
||||
if (immsrc < 2)
|
||||
|
||||
if (!c.core->a.is_cpu_mode()) {
|
||||
//
|
||||
// GPGPU CSR extension
|
||||
//
|
||||
if (immsrc == 0x20) // ThreadID
|
||||
{
|
||||
//std::cout << "INTERRUPT ECALL/EBREAK\n";
|
||||
nextActiveThreads = 0;
|
||||
c.spawned = false;
|
||||
// c.interrupt(0);
|
||||
reg[rdest] = t;
|
||||
D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]);
|
||||
}
|
||||
else if (immsrc == 0x21) // WarpID
|
||||
{
|
||||
reg[rdest] = c.id;
|
||||
D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]);
|
||||
}
|
||||
else if (immsrc == 0x25)
|
||||
{
|
||||
reg[rdest] = c.core->num_instructions;
|
||||
}
|
||||
else if (immsrc == 0x26)
|
||||
{
|
||||
reg[rdest] = c.core->num_cycles;
|
||||
}
|
||||
} else {
|
||||
switch (func3)
|
||||
{
|
||||
case 1:
|
||||
// printf("Case 1\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = temp;
|
||||
|
||||
break;
|
||||
case 2:
|
||||
// printf("Case 2\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
// printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
// printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
|
||||
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
|
||||
|
||||
break;
|
||||
case 3:
|
||||
// printf("Case 3\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
|
||||
|
||||
break;
|
||||
case 5:
|
||||
// printf("Case 5\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0];
|
||||
|
||||
break;
|
||||
case 6:
|
||||
// printf("Case 6\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
|
||||
|
||||
break;
|
||||
case 7:
|
||||
// printf("Case 7\n");
|
||||
if (rdest != 0)
|
||||
{
|
||||
reg[rdest] = c.csr[immsrc & 0x00000FFF];
|
||||
}
|
||||
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
|
||||
|
||||
break;
|
||||
case 0:
|
||||
if (immsrc < 2)
|
||||
{
|
||||
//std::cout << "INTERRUPT ECALL/EBREAK\n";
|
||||
nextActiveThreads = 0;
|
||||
c.spawned = false;
|
||||
// c.interrupt(0);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case TRAP:
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,43 +1,43 @@
|
|||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
|
||||
S 26 1407374883617647 1583036691 972658000 1583036691 972658000 "../rtl/./VX_define_synth.v"
|
||||
S 283 1407374883617640 1583036691 969666100 1583036691 969666100 "../rtl/VX_countones.v"
|
||||
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/VX_define.v"
|
||||
S 8325 1407374883617648 1583036691 973655300 1583036691 973655300 "../rtl/VX_dmem_controller.v"
|
||||
S 517 1407374883617652 1583036691 975649300 1583036691 975649300 "../rtl/VX_generic_priority_encoder.v"
|
||||
S 683 1407374883617664 1583036691 981634100 1583036691 981634100 "../rtl/VX_priority_encoder_w_mask.v"
|
||||
S 8590 1407374883617675 1583036691 985623400 1583036691 985623400 "../rtl/cache/VX_Cache_Bank.v"
|
||||
S 748 1407374883617676 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_bank_valid.v"
|
||||
S 7349 1407374883617677 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_data.v"
|
||||
S 6476 1407374883617678 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_cache_data_per_index.v"
|
||||
S 14645 1407374883617679 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_d_cache.v"
|
||||
S 393 1407374883617692 1583036691 993601900 1583036691 993601900 "../rtl/interfaces/VX_dcache_request_inter.v"
|
||||
S 215 1407374883617693 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dcache_response_inter.v"
|
||||
S 870 1407374883617694 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
|
||||
S 354 1407374883617709 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_request_inter.v"
|
||||
S 212 1407374883617710 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_response_inter.v"
|
||||
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/shared_memory/../VX_define.v"
|
||||
S 676 1407374883617754 1583036692 20529900 1583036692 20529900 "../rtl/shared_memory/VX_bank_valids.v"
|
||||
S 3038 1407374883617755 1583036692 21526400 1583036692 21526400 "../rtl/shared_memory/VX_priority_encoder_sm.v"
|
||||
S 4962 1407374883617756 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory.v"
|
||||
S 3207 1407374883617757 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory_block.v"
|
||||
S 26 1407374883678355 1576858113 365285900 1576858113 365285900 "../rtl/./VX_define_synth.v"
|
||||
S 283 1407374883678346 1576858113 363291200 1576858113 363291200 "../rtl/VX_countones.v"
|
||||
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/VX_define.v"
|
||||
S 8325 1407374883678357 1576858113 366283200 1576858113 366283200 "../rtl/VX_dmem_controller.v"
|
||||
S 517 1407374883678365 1576858113 368277800 1576858113 368277800 "../rtl/VX_generic_priority_encoder.v"
|
||||
S 683 1407374883678386 1576858113 374262300 1576858113 374262300 "../rtl/VX_priority_encoder_w_mask.v"
|
||||
S 8590 1407374883678402 1576858113 378252100 1576858113 378252100 "../rtl/cache/VX_Cache_Bank.v"
|
||||
S 748 1407374883678406 1576858113 379248400 1576858113 379248400 "../rtl/cache/VX_cache_bank_valid.v"
|
||||
S 7349 1407374883678408 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data.v"
|
||||
S 6476 1407374883678409 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data_per_index.v"
|
||||
S 14645 1407374883678410 1576858113 381243100 1576858113 381243100 "../rtl/cache/VX_d_cache.v"
|
||||
S 393 1407374883678432 1576858113 386229700 1576858113 386229700 "../rtl/interfaces/VX_dcache_request_inter.v"
|
||||
S 215 1407374883678434 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dcache_response_inter.v"
|
||||
S 870 1407374883678435 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
|
||||
S 354 1407374883678447 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_request_inter.v"
|
||||
S 212 1407374883678448 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_response_inter.v"
|
||||
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/shared_memory/../VX_define.v"
|
||||
S 676 1407374883678497 1576858113 417147000 1576858113 417147000 "../rtl/shared_memory/VX_bank_valids.v"
|
||||
S 3038 1407374883678498 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_priority_encoder_sm.v"
|
||||
S 4962 1407374883678499 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_shared_memory.v"
|
||||
S 3207 1407374883678500 1576858113 419141900 1576858113 419141900 "../rtl/shared_memory/VX_shared_memory_block.v"
|
||||
S 5279832 1125899907857040 1579658333 790142700 1519110675 0 "/usr/bin/verilator_bin"
|
||||
S 3144 1407374883617983 1583036693 278327800 1583036693 278327800 "cache_simX.v"
|
||||
T 390173 4222124650721525 1583038884 772480200 1583038884 772480200 "obj_dir/Vcache_simX.cpp"
|
||||
T 28278 5066549580853492 1583038884 765499600 1583038884 765499600 "obj_dir/Vcache_simX.h"
|
||||
T 2365 18858823439675736 1583038884 803378700 1583038884 803378700 "obj_dir/Vcache_simX.mk"
|
||||
T 643931 2533274790457603 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
|
||||
T 23659 2533274790457602 1583038884 788131800 1583038884 788131800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
|
||||
T 578414 2533274790457601 1583038884 787134700 1583038884 787134700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
|
||||
T 23321 4222124650721534 1583038884 776161100 1583038884 776161100 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
|
||||
T 1024 2251799813746939 1583038884 775163700 1583038884 775163700 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
|
||||
T 1561 5348024557564153 1583038884 774165800 1583038884 774165800 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
|
||||
T 999 2533274790457592 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
|
||||
T 1557 2814749767168246 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
|
||||
T 6004 14073748835594442 1583038884 720643500 1583038884 720643500 "obj_dir/Vcache_simX__Syms.cpp"
|
||||
T 2455 3096224743878468 1583038884 719619200 1583038884 719619200 "obj_dir/Vcache_simX__Syms.h"
|
||||
T 1114242 5066549580853489 1583038884 763504200 1583038884 763504200 "obj_dir/Vcache_simX__Trace.cpp"
|
||||
T 1433229 3377699720589552 1583038884 745891000 1583038884 745891000 "obj_dir/Vcache_simX__Trace__Slow.cpp"
|
||||
T 1439 1688849860325816 1583038884 804364500 1583038884 804364500 "obj_dir/Vcache_simX__ver.d"
|
||||
T 0 0 1583038884 836313300 1583038884 836313300 "obj_dir/Vcache_simX__verFiles.dat"
|
||||
T 1392 2251799813746948 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_classes.mk"
|
||||
S 3144 1407374883678789 1576858114 576047000 1576858114 576047000 "cache_simX.v"
|
||||
T 390173 22236523160217637 1583612769 755410900 1583612769 755410900 "obj_dir/Vcache_simX.cpp"
|
||||
T 28278 15481123719153127 1583612769 748398500 1583612769 748398500 "obj_dir/Vcache_simX.h"
|
||||
T 2365 10133099161813405 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX.mk"
|
||||
T 643931 3940649674155161 1583612769 783340900 1583612769 783340900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
|
||||
T 23659 5348024557708078 1583612769 771372900 1583612769 771372900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
|
||||
T 578414 15481123719285399 1583612769 770399200 1583612769 770399200 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
|
||||
T 23321 11258999068615501 1583612769 760411300 1583612769 760411300 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
|
||||
T 1024 8725724278219266 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
|
||||
T 1561 50102545854682183 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
|
||||
T 999 10414574138447661 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
|
||||
T 1557 6755399441176779 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
|
||||
T 6004 11821949021903061 1583612769 706686400 1583612769 706686400 "obj_dir/Vcache_simX__Syms.cpp"
|
||||
T 2455 32088147345022597 1583612769 705722700 1583612769 705722700 "obj_dir/Vcache_simX__Syms.h"
|
||||
T 1114242 10414574138355386 1583612769 747434700 1583612769 747434700 "obj_dir/Vcache_simX__Trace.cpp"
|
||||
T 1433229 12103423998619303 1583612769 729412200 1583612769 729412200 "obj_dir/Vcache_simX__Trace__Slow.cpp"
|
||||
T 1439 6755399441290555 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX__ver.d"
|
||||
T 0 0 1583612769 844870300 1583612769 844870300 "obj_dir/Vcache_simX__verFiles.dat"
|
||||
T 1392 4785074604292692 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX_classes.mk"
|
||||
|
|
|
|||
Binary file not shown.
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Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -55,8 +55,10 @@ HarpToolMode findMode(int argc, char** argv) {
|
|||
}
|
||||
|
||||
int emu_main(int argc, char **argv) {
|
||||
string archString("rv32i"), imgFileName("a.dsfsdout.bin");
|
||||
string archString("rv32i");
|
||||
string imgFileName("a.dsfsdout.bin");
|
||||
bool showHelp, showStats, basicMachine, batch;
|
||||
bool cpu_mode(false);
|
||||
|
||||
/* Read the command line arguments. */
|
||||
CommandLineArgFlag fh("-h", "--help", "", showHelp);
|
||||
|
|
@ -65,15 +67,17 @@ int emu_main(int argc, char **argv) {
|
|||
CommandLineArgFlag fs("-s", "--stats", "", showStats);
|
||||
CommandLineArgFlag fb("-b", "--basic", "", basicMachine);
|
||||
CommandLineArgFlag fi("-i", "--batch", "", batch);
|
||||
CommandLineArgFlag fx("-x", "--cpu", "", cpu_mode);
|
||||
|
||||
CommandLineArg::readArgs(argc, argv);
|
||||
|
||||
if (showHelp) {
|
||||
cout << Help::emuHelp;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Instantiate a Core, RAM, and console output. */
|
||||
ArchDef arch(archString);
|
||||
ArchDef arch(archString, cpu_mode);
|
||||
|
||||
Decoder *dec;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,142 @@
|
|||
make
|
||||
cd obj_dir
|
||||
echo start > results.txt
|
||||
|
||||
# echo ../kernel/vortex_test.hex
|
||||
make
|
||||
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
|
||||
#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
|
||||
cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/priya/Desktop/new_vortex/Vortex/rvvector/benchmark_temp/vx_vec_benchmark.hex -s -b 1> emulator.debug
|
||||
echo ./riscv_tests/rv32ui-p-add.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-and.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-or.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt
|
||||
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-div.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt
|
||||
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt
|
||||
|
||||
|
|
|
|||
17
simX/test_runtime.sh
Executable file
17
simX/test_runtime.sh
Executable file
|
|
@ -0,0 +1,17 @@
|
|||
make
|
||||
make -C ../runtime/mains/dev
|
||||
make -C ../runtime/mains/hello
|
||||
make -C ../runtime/mains/nativevecadd
|
||||
make -C ../runtime/mains/simple
|
||||
make -C ../runtime/mains/vecadd
|
||||
|
||||
cd obj_dir
|
||||
echo start > results.txt
|
||||
|
||||
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
|
||||
|
||||
#./Vcache_simX -E -a rv32i --core ../../runtime/mains/dev/vx_dev_main.hex -s -b 1> emulator.debug
|
||||
#./Vcache_simX -E -a rv32i --core ../../runtime/mains/hello/hello.hex -s -b 1> emulator.debug
|
||||
./Vcache_simX -E -a rv32i --core ../../runtime/mains/nativevecadd/vx_pocl_main.hex -s -b 1> emulator.debug
|
||||
./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
|
||||
./Vcache_simX -E -a rv32i --core ../../runtime/mains/vecadd/vx_pocl_main.hex -s -b 1> emulator.debug
|
||||
|
|
@ -1,145 +0,0 @@
|
|||
make
|
||||
cd obj_dir
|
||||
echo start > results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-add.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-and.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-or.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
|
||||
|
||||
echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt
|
||||
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
|
||||
|
||||
|
||||
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-div.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
|
||||
|
||||
# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt
|
||||
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt
|
||||
|
||||
23400
syn/191017.log
23400
syn/191017.log
File diff suppressed because it is too large
Load diff
BIN
syn/Vortex.ddc
BIN
syn/Vortex.ddc
Binary file not shown.
907
syn/dc.log
907
syn/dc.log
|
|
@ -1,907 +0,0 @@
|
|||
|
||||
Design Compiler Graphical
|
||||
DC Ultra (TM)
|
||||
DFTMAX (TM)
|
||||
Power Compiler (TM)
|
||||
DesignWare (R)
|
||||
DC Expert (TM)
|
||||
Design Vision (TM)
|
||||
HDL Compiler (TM)
|
||||
VHDL Compiler (TM)
|
||||
DFT Compiler
|
||||
Design Compiler(R)
|
||||
|
||||
Version O-2018.06-SP3 for linux64 - Oct 18, 2018
|
||||
|
||||
Copyright (c) 1988 - 2018 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
Initializing...
|
||||
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
|
||||
/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db
|
||||
set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb]
|
||||
* sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb
|
||||
set symbol_library {}
|
||||
set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]
|
||||
sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db
|
||||
set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v ]
|
||||
VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v
|
||||
# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v # ]
|
||||
set top_level Vortex
|
||||
Vortex
|
||||
analyze -format sverilog $verilog_files
|
||||
Running PRESTO HDLC
|
||||
Compiling source file ../rtl/VX_countones.v
|
||||
Compiling source file ../rtl/VX_priority_encoder_w_mask.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/interfaces/VX_dram_req_rsp_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_dram_req_rsp_inter.v:10: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/cache/VX_cache_data_per_index.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/cache/VX_Cache_Bank.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/cache/VX_cache_data.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/cache/VX_d_cache.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/shared_memory/VX_bank_valids.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/shared_memory/VX_priority_encoder_sm.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/shared_memory/VX_shared_memory.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/shared_memory/VX_shared_memory_block.v
|
||||
Compiling source file ../rtl/VX_dmem_controller.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_generic_priority_encoder.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/VX_generic_stack.v
|
||||
Compiling source file ../rtl/interfaces/VX_join_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_join_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/VX_csr_wrapper.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/interfaces/VX_csr_req_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_csr_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_csr_wb_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_csr_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/VX_gpgpu_inst.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/interfaces/VX_gpu_inst_req_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_gpu_inst_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_wstall_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_wstall_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_inst_exec_wb_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_inst_exec_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/VX_lsu.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_execute_unit.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Warning: ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Warning: ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Warning: ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Warning: ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Compiling source file ../rtl/VX_lsu_addr_gen.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_inst_multiplex.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/interfaces/VX_exec_unit_req_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_exec_unit_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_lsu_req_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_lsu_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/VX_alu.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_back_end.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_gpr_stage.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/interfaces/VX_gpr_data_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_gpr_data_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/VX_csr_handler.v
|
||||
Compiling source file ../rtl/VX_decode.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Warning: ../rtl/VX_csr_handler.v:34: The statements in initial blocks are ignored. (VER-281)
|
||||
Compiling source file ../rtl/VX_define.v
|
||||
Compiling source file ../rtl/VX_scheduler.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_fetch.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_front_end.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_generic_register.v
|
||||
Compiling source file ../rtl/VX_gpr.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_gpr_wrapper.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_priority_encoder.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_warp_scheduler.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/VX_writeback.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/byte_enabled_simple_dual_port_ram.v
|
||||
Opening include file ../rtl//VX_define.v
|
||||
Compiling source file ../rtl/interfaces/VX_branch_response_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_branch_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_dcache_request_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_dcache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_dcache_response_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_dcache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_frE_to_bckE_req_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_frE_to_bckE_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_gpr_clone_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_gpr_clone_inter.v:9: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_gpr_jal_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_gpr_jal_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_gpr_read_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_gpr_read_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_gpr_wspawn_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_gpr_wspawn_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_icache_request_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_icache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_icache_response_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_icache_response_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_inst_mem_wb_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_inst_mem_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_inst_meta_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_inst_meta_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_jal_response_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_jal_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_mem_req_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_mem_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_mw_wb_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_mw_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_warp_ctl_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_warp_ctl_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/interfaces/VX_wb_inter.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Information: ../rtl/interfaces/VX_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988)
|
||||
Compiling source file ../rtl/pipe_regs/VX_d_e_reg.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/pipe_regs/VX_f_d_reg.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/Vortex.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Compiling source file ../rtl/cache/VX_cache_bank_valid.v
|
||||
Opening include file ../rtl/interfaces/../VX_define.v
|
||||
Presto compilation completed successfully.
|
||||
Loading db file '/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db'
|
||||
Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db'
|
||||
Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db'
|
||||
Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db'
|
||||
Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db'
|
||||
Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb'
|
||||
1
|
||||
elaborate Vortex
|
||||
Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/gtech.db'
|
||||
Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/standard.sldb'
|
||||
Loading link library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c'
|
||||
Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
|
||||
Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
|
||||
Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
|
||||
Loading link library 'USERLIB_ss_0p81v_0p81v_m40c'
|
||||
Loading link library 'gtech'
|
||||
Running PRESTO HDLC
|
||||
Presto compilation completed successfully.
|
||||
Elaborated 1 design.
|
||||
Current design is now 'Vortex'.
|
||||
Information: Building the design 'VX_front_end' instantiated from design 'Vortex' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%schedule_delay%)(N%icache_response_fe%I%WORK/VX_icache_response_inter%%)(N%icache_request_fe%I%WORK/VX_icache_request_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%fetch_ebreak%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Warning: Filename too long >255 chars. Renaming file:
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__.mr'
|
||||
to
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_35FE527370C98E3C09E2E6E2555D7EE6F02ECB4FA9775364_000.mr'
|
||||
Information: Building the design 'VX_scheduler' instantiated from design 'Vortex' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%memory_delay%)(N%gpr_stage_delay%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%schedule_delay%))". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__ line 52 in file
|
||||
'../rtl/VX_scheduler.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| rename_table_reg | Flip-flop | 256 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Statistics for MUX_OPs
|
||||
================================================================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
================================================================================================================================
|
||||
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/24 | 8 | 32 | 3 |
|
||||
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/24 | 32 | 1 | 5 |
|
||||
| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/25 | 32 | 1 | 5 |
|
||||
================================================================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_back_end' instantiated from design 'Vortex' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_mem_delay%)(N%gpr_stage_delay%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Warning: Filename too long >255 chars. Renaming file:
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__.mr'
|
||||
to
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I__B458045CB598257C352A6473E41AFB0017DAE536C3121AF6_000.mr'
|
||||
Information: Building the design 'VX_dmem_controller' instantiated from design 'Vortex' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%VX_dram_req_rsp%I%WORK/VX_dram_req_rsp_inter%%NUMBER_BANKS=4,NUM_WORDS_PER_BLOCK=4)(N%VX_dram_req_rsp_icache%I%WORK/VX_dram_req_rsp_inter%%NUMBER_BANKS=1,NUM_WORDS_PER_BLOCK=4)(N%VX_icache_req%I%WORK/VX_icache_request_inter%%)(N%VX_icache_rsp%I%WORK/VX_icache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%))". (HDL-193)
|
||||
Warning: ../rtl/VX_dmem_controller.v:94: signed to unsigned conversion occurs. (VER-318)
|
||||
Warning: ../rtl/VX_dmem_controller.v:140: signed to unsigned conversion occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Warning: Filename too long >255 chars. Renaming file:
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_DMEM_CONTROLLER_I_VX_DRAM_REQ_RSP_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_DRAM_REQ_RSP_ICACHE_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_ICACHE_REQ_VX_ICACHE_REQUEST_INTER__I_VX_ICACHE_RSP_VX_ICACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__.mr'
|
||||
to
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_DMEM_CONTROLLER_I_VX_DRAM_REQ_RSP_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_DRAM_REQ_RSP_ICACHE_VX_DRAM_REQ_RSP_INTER__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_ICACHE_REQ_VX__40031EEB97323B6857B566A3D5CC469DED662C572979AF0C_000.mr'
|
||||
Information: Building the design 'VX_fetch' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%)(N%schedule_delay%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%icache_response%I%WORK/VX_icache_response_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%icache_request%I%WORK/VX_icache_request_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%out_ebreak%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Warning: Filename too long >255 chars. Renaming file:
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_FE_INST_META_FD_VX_INST_META_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__.mr'
|
||||
to
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RS_86A42238AAF2AFE24C53E826055B694A355B7E541802DCF6_000.mr'
|
||||
Information: Building the design 'VX_f_d_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%in_freeze%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%)(N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_decode' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
||||
the parameters "|((N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%))". (HDL-193)
|
||||
Warning: ../rtl/VX_decode.v:152: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_decode.v:300: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
|
||||
Warning: ../rtl/VX_decode.v:315: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
|
||||
|
||||
Statistics for case statements in always block at line 159 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 160 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 190 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 191 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 244 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 245 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 258 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 259 | auto/auto |
|
||||
| 264 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 298 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 300 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 313 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 315 | auto/auto |
|
||||
===============================================
|
||||
|
||||
Statistics for case statements in always block at line 330 in file
|
||||
'../rtl/VX_decode.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 331 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_d_e_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%in_branch_stall%)(N%in_freeze%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_mw_wb_inter'. (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_mem_req_inter'. (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_gpr_stage' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%memory_delay%)(N%gpr_stage_delay%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_lsu' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%out_delay%)(N%no_slot_mem%))". (HDL-193)
|
||||
Warning: ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Warning: ../rtl/VX_lsu.v:59: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Warning: ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
Warning: ../rtl/VX_lsu.v:63: Invalid escape sequence '\x' in call to '$display'. (VER-941)
|
||||
$display output: Reading addr: val: ??
|
||||
$display output: Writing addr: val: ??
|
||||
$display output: Reading addr: val: ??
|
||||
$display output: Writing addr: val: ??
|
||||
$display output: Reading addr: val: ??
|
||||
$display output: Writing addr: val: ??
|
||||
$display output: Reading addr: val: ??
|
||||
$display output: Writing addr: val: ??
|
||||
Warning: ../rtl/VX_lsu.v:55: Netlist for always block is empty. (ELAB-985)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_execute_unit' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
||||
the parameters "|((N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%))". (HDL-193)
|
||||
Warning: ../rtl/VX_execute_unit.v:108: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_execute_unit.v:115: signed to unsigned assignment occurs. (VER-318)
|
||||
|
||||
Statistics for case statements in always block at line 74 in file
|
||||
'../rtl/VX_execute_unit.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 76 | auto/auto |
|
||||
===============================================
|
||||
Statistics for MUX_OPs
|
||||
===========================================================================================================================================================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
===========================================================================================================================================================================================================================
|
||||
| VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__/71 | 4 | 64 | 2 |
|
||||
===========================================================================================================================================================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_gpgpu_inst' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
||||
the parameters "|((N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_csr_wrapper' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
||||
the parameters "|((N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_writeback' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with
|
||||
the parameters "|((N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%no_slot_mem%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_shared_memory' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_dram_req_rsp_icache_VX_dram_req_rsp_inter__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_icache_req_VX_icache_request_inter__I_VX_icache_rsp_VX_icache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
|
||||
the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_shared_memory_NB7_BITS_PER_BANK3 line 86 in file
|
||||
'../rtl/shared_memory/VX_shared_memory.v'.
|
||||
===========================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===========================================================================
|
||||
| temp_out_data_reg | Latch | 128 | Y | N | N | N | - | - | - |
|
||||
| shm_write_reg | Latch | 1 | N | N | N | N | - | - | - |
|
||||
| temp_out_valid_reg | Latch | 4 | Y | N | N | N | - | - | - |
|
||||
===========================================================================
|
||||
Statistics for MUX_OPs
|
||||
=============================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
=============================================================================
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 |
|
||||
=============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_dram_req_rsp_icache_VX_dram_req_rsp_inter__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_icache_req_VX_icache_request_inter__I_VX_icache_rsp_VX_icache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
|
||||
the parameters "CACHE_SIZE=4096,CACHE_WAYS=2,CACHE_BLOCK=64,CACHE_BANKS=4,LOG_NUM_BANKS=2,NUM_REQ=4,LOG_NUM_REQ=2,NUM_IND=128,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=18,IND_SIZE_START=0,IND_SIZE_END=6,ADDR_TAG_START=13,ADDR_TAG_END=31,ADDR_OFFSET_START=4,ADDR_OFFSET_END=5,ADDR_IND_START=6,ADDR_IND_END=12,MEM_ADDR_REQ_MASK=32'hffffffc0". (HDL-193)
|
||||
Warning: ../rtl/cache/VX_d_cache.v:237: signed to unsigned assignment occurs. (VER-318)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0 line 251 in file
|
||||
'../rtl/cache/VX_d_cache.v'.
|
||||
===================================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===================================================================================
|
||||
| global_way_to_evict_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
|
||||
| final_data_read_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N |
|
||||
| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
||||
| stored_valid_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
||||
| miss_addr_reg | Flip-flop | 30 | Y | N | Y | N | N | N | N |
|
||||
===================================================================================
|
||||
Statistics for MUX_OPs
|
||||
===================================================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
===================================================================================================================
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/279 | 4 | 2 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/279 | 4 | 30 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/298 | 4 | 30 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/342 | 4 | 32 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/298 | 4 | 30 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/342 | 4 | 32 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/298 | 4 | 30 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/342 | 4 | 32 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/298 | 4 | 30 | 2 |
|
||||
| VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0/342 | 4 | 32 | 2 |
|
||||
===================================================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__NUMBER_BANKS_4_NUM_WORDS_PER_BLOCK_4I_VX_dram_req_rsp_icache_VX_dram_req_rsp_inter__NUMBER_BANKS_1_NUM_WORDS_PER_BLOCK_4I_VX_icache_req_VX_icache_request_inter__I_VX_icache_rsp_VX_icache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with
|
||||
the parameters "CACHE_SIZE=1024,CACHE_WAYS=2,CACHE_BLOCK=16,CACHE_BANKS=1,LOG_NUM_BANKS=1,NUM_REQ=1,LOG_NUM_REQ=1,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4,ADDR_TAG_START=9,ADDR_TAG_END=31,ADDR_OFFSET_START=2,ADDR_OFFSET_END=3,ADDR_IND_START=4,ADDR_IND_END=8,MEM_ADDR_REQ_MASK=32'hfffffff0". (HDL-193)
|
||||
Warning: ../rtl/cache/VX_d_cache.v:237: signed to unsigned assignment occurs. (VER-318)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0 line 251 in file
|
||||
'../rtl/cache/VX_d_cache.v'.
|
||||
===================================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===================================================================================
|
||||
| global_way_to_evict_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
|
||||
| final_data_read_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
||||
| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
||||
| stored_valid_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
|
||||
| miss_addr_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
||||
===================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_warp_scheduler'. (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_warp_scheduler line 117 in file
|
||||
'../rtl/VX_warp_scheduler.v'.
|
||||
==================================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
==================================================================================
|
||||
| warp_stalled_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N |
|
||||
| didnt_split_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
|
||||
| barrier_stall_mask_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
||||
| use_wsapwn_pc_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N |
|
||||
| use_wsapwn_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N |
|
||||
| warp_pcs_reg | Flip-flop | 227 | Y | N | Y | N | N | N | N |
|
||||
| warp_pcs_reg | Flip-flop | 29 | Y | N | N | Y | N | N | N |
|
||||
| warp_active_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N |
|
||||
| warp_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N |
|
||||
| visible_active_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N |
|
||||
| visible_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N |
|
||||
| thread_masks_reg | Flip-flop | 24 | Y | N | Y | N | N | N | N |
|
||||
| thread_masks_reg | Flip-flop | 8 | Y | N | N | Y | N | N | N |
|
||||
==================================================================================
|
||||
Statistics for MUX_OPs
|
||||
===========================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
===========================================================
|
||||
| VX_warp_scheduler/227 | 4 | 8 | 2 |
|
||||
| VX_warp_scheduler/245 | 8 | 4 | 3 |
|
||||
| VX_warp_scheduler/249 | 8 | 37 | 3 |
|
||||
| VX_warp_scheduler/278 | 8 | 3 | 3 |
|
||||
| VX_warp_scheduler/286 | 8 | 32 | 3 |
|
||||
| VX_warp_scheduler/287 | 8 | 4 | 3 |
|
||||
===========================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' with
|
||||
the parameters "N=71". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N71 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 71 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with
|
||||
the parameters "N=240". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N240 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 240 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_gpr_wrapper' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_gpr_jal%I%WORK/VX_gpr_jal_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193)
|
||||
Statistics for MUX_OPs
|
||||
==========================================================================================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
==========================================================================================================================================================
|
||||
| VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__/42 | 8 | 256 | 3 |
|
||||
==========================================================================================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_inst_multiplex' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "|((N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_gpr_data%I%WORK/VX_gpr_data_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "N=1". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N1 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 1 | N | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "N=256". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N256 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 256 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "N=84". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N84 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 84 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "N=231". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N231 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 231 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "N=43". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N43 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 43 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with
|
||||
the parameters "N=60". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N60 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 60 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_lsu_addr_gen'. (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_alu'. (HDL-193)
|
||||
Warning: ../rtl/VX_alu.v:40: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_alu.v:49: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_alu.v:50: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_alu.v:56: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_alu.v:61: signed to unsigned assignment occurs. (VER-318)
|
||||
Warning: ../rtl/VX_alu.v:66: signed to unsigned conversion occurs. (VER-318)
|
||||
Warning: ../rtl/VX_alu.v:68: signed to unsigned conversion occurs. (VER-318)
|
||||
|
||||
Statistics for case statements in always block at line 47 in file
|
||||
'../rtl/VX_alu.v'
|
||||
===============================================
|
||||
| Line | full/ parallel |
|
||||
===============================================
|
||||
| 48 | auto/auto |
|
||||
===============================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' with
|
||||
the parameters "N=4". (HDL-193)
|
||||
Warning: ../rtl/VX_generic_priority_encoder.v:22: signed to unsigned part selection occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_countones' instantiated from design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' with
|
||||
the parameters "N=4". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_priority_encoder_sm' instantiated from design 'VX_shared_memory_NB7_BITS_PER_BANK3' with
|
||||
the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_priority_encoder_sm_NB7_BITS_PER_BANK3 line 104 in file
|
||||
'../rtl/shared_memory/VX_priority_encoder_sm.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| left_requests_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Statistics for MUX_OPs
|
||||
==================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
==================================================================================
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 |
|
||||
==================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_shared_memory_block'. (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_cache_bank_valid' instantiated from design 'VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0' with
|
||||
the parameters "NUMBER_BANKS=4,LOG_NUM_BANKS=2,NUM_REQ=4". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_priority_encoder_w_mask' instantiated from design 'VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0' with
|
||||
the parameters "N=4". (HDL-193)
|
||||
Warning: ../rtl/VX_priority_encoder_w_mask.v:23: signed to unsigned part selection occurs. (VER-318)
|
||||
Warning: ../rtl/VX_priority_encoder_w_mask.v:31: signed to unsigned assignment occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_Cache_Bank' instantiated from design 'VX_d_cache_4096_2_64_4_2_4_2_128_1_4_0_1_0_18_0_6_13_31_4_5_6_12_ffffffc0' with
|
||||
the parameters "CACHE_SIZE=4096,CACHE_WAYS=2,CACHE_BLOCK=64,CACHE_BANKS=4,LOG_NUM_BANKS=2,NUM_REQ=4,LOG_NUM_REQ=2,NUM_IND=128,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=18,IND_SIZE_START=0,IND_SIZE_END=6,ADDR_TAG_START=13,ADDR_TAG_END=31,ADDR_OFFSET_START=4,ADDR_OFFSET_END=5,ADDR_IND_START=6,ADDR_IND_END=12". (HDL-193)
|
||||
Warning: ../rtl/cache/VX_Cache_Bank.v:216: Net way_to_update[0] or a directly connected net may be driven by more than one process or block. (ELAB-405)
|
||||
Statistics for MUX_OPs
|
||||
=======================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
=======================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12/158 | 4 | 32 | 2 |
|
||||
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12/158 | 4 | 24 | 2 |
|
||||
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12/158 | 4 | 16 | 2 |
|
||||
| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12/158 | 4 | 8 | 2 |
|
||||
=======================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Warning: Filename too long >255 chars. Renaming file:
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_CACHE_BANK_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12.mr'
|
||||
to
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_CACHE_BANK_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE__882FB6297E42F542C0AF530517BB2B1CE826960222199217_000.mr'
|
||||
Information: Building the design 'VX_cache_bank_valid' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
|
||||
the parameters "NUMBER_BANKS=1,LOG_NUM_BANKS=1,NUM_REQ=1". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_priority_encoder_w_mask' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
|
||||
the parameters "N=1". (HDL-193)
|
||||
Warning: ../rtl/VX_priority_encoder_w_mask.v:23: signed to unsigned part selection occurs. (VER-318)
|
||||
Warning: ../rtl/VX_priority_encoder_w_mask.v:31: signed to unsigned assignment occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
|
||||
the parameters "N=1". (HDL-193)
|
||||
Warning: ../rtl/VX_generic_priority_encoder.v:22: signed to unsigned part selection occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_Cache_Bank' instantiated from design 'VX_d_cache_1024_2_16_1_1_1_1_32_1_4_0_1_0_22_0_4_9_31_2_3_4_8_fffffff0' with
|
||||
the parameters "CACHE_SIZE=1024,CACHE_WAYS=2,CACHE_BLOCK=16,CACHE_BANKS=1,LOG_NUM_BANKS=1,NUM_REQ=1,LOG_NUM_REQ=1,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,OFFSET_SIZE_START=0,OFFSET_SIZE_END=1,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4,ADDR_TAG_START=9,ADDR_TAG_END=31,ADDR_OFFSET_START=2,ADDR_OFFSET_END=3,ADDR_IND_START=4,ADDR_IND_END=8". (HDL-193)
|
||||
Warning: ../rtl/cache/VX_Cache_Bank.v:216: Net way_to_update[0] or a directly connected net may be driven by more than one process or block. (ELAB-405)
|
||||
Statistics for MUX_OPs
|
||||
====================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
| block name/line | Inputs | Outputs | # sel inputs |
|
||||
====================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 | 4 | 32 | 2 |
|
||||
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 | 4 | 24 | 2 |
|
||||
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 | 4 | 16 | 2 |
|
||||
| VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8/158 | 4 | 8 | 2 |
|
||||
====================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
Presto compilation completed successfully.
|
||||
Warning: Filename too long >255 chars. Renaming file:
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_CACHE_BANK_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8.mr'
|
||||
to
|
||||
'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_CACHE_BANK_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_S_EDF18E249C9AFC7FAE86B4E8AC90C60B5789F786DECF7FD1_000.mr'
|
||||
Information: Building the design 'VX_countones' instantiated from design 'VX_warp_scheduler' with
|
||||
the parameters "N=8". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_stack' instantiated from design 'VX_warp_scheduler' with
|
||||
the parameters "WIDTH=37,DEPTH=3". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_stack_WIDTH37_DEPTH3 line 21 in file
|
||||
'../rtl/VX_generic_stack.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| stack_reg | Flip-flop | 259 | Y | N | N | N | N | N | N |
|
||||
| ptr_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_priority_encoder'. (HDL-193)
|
||||
Warning: ../rtl/VX_priority_encoder.v:15: signed to unsigned part selection occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with
|
||||
the parameters "3". (HDL-193)
|
||||
|
||||
Inferred memory devices in process
|
||||
in routine VX_generic_register_N3 line 21 in file
|
||||
'../rtl/VX_generic_register.v'.
|
||||
===============================================================================
|
||||
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
|
||||
===============================================================================
|
||||
| value_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N |
|
||||
===============================================================================
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_gpr' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with
|
||||
the parameters "|((N%clk%)(N%reset%)(N%valid_write_request%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_bank_valids' instantiated from design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' with
|
||||
the parameters "NB=7,BITS_PER_BANK=3". (HDL-193)
|
||||
Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
|
||||
Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
|
||||
Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_cache_data_per_index' instantiated from design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12' with
|
||||
the parameters "CACHE_WAYS=2,NUM_IND=128,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=18,IND_SIZE_START=0,IND_SIZE_END=6". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_cache_data_per_index' instantiated from design 'VX_Cache_Bank_CACHE_SIZE1024_CACHE_WAYS2_CACHE_BLOCK16_CACHE_BANKS1_LOG_NUM_BANKS1_NUM_REQ1_LOG_NUM_REQ1_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_ADDR_TAG_START9_ADDR_TAG_END31_ADDR_OFFSET_START2_ADDR_OFFSET_END3_ADDR_IND_START4_ADDR_IND_END8' with
|
||||
the parameters "CACHE_WAYS=2,NUM_IND=32,CACHE_WAY_INDEX=1,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6' with
|
||||
the parameters "N=2". (HDL-193)
|
||||
Warning: ../rtl/VX_generic_priority_encoder.v:22: signed to unsigned part selection occurs. (VER-318)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_cache_data' instantiated from design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6' with
|
||||
the parameters "NUM_IND=128,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=18,IND_SIZE_START=0,IND_SIZE_END=6". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Information: Building the design 'VX_cache_data' instantiated from design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND32_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4' with
|
||||
the parameters "NUM_IND=32,NUM_WORDS_PER_BLOCK=4,TAG_SIZE_START=0,TAG_SIZE_END=22,IND_SIZE_START=0,IND_SIZE_END=4". (HDL-193)
|
||||
Presto compilation completed successfully.
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Information: Building the design 'rf2_32x19_wm0'. (HDL-193)
|
||||
Warning: Cannot find the design 'rf2_32x19_wm0' in the library 'WORK'. (LBR-1)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Error: Width mismatch on port 'TAA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-3)
|
||||
Error: Width mismatch on port 'TAA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-3)
|
||||
Warning: Design 'Vortex' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
|
||||
1
|
||||
link
|
||||
|
||||
Linking design 'Vortex'
|
||||
Using the following designs and libraries:
|
||||
--------------------------------------------------------------------------
|
||||
* (55 designs) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/Vortex.db, etc
|
||||
sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (library) /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db
|
||||
USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db
|
||||
USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db
|
||||
USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db
|
||||
USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db
|
||||
dw_foundation.sldb (library) /tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb
|
||||
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Information: Building the design 'rf2_32x19_wm0'. (HDL-193)
|
||||
Warning: Cannot find the design 'rf2_32x19_wm0' in the library 'WORK'. (LBR-1)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Error: Width mismatch on port 'TAA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
|
||||
Error: Width mismatch on port 'TAA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (LINK-5)
|
||||
0
|
||||
set clk_freq 100
|
||||
100
|
||||
set clk_period [expr 1000.0 / $clk_freq / 1.0]
|
||||
10.0
|
||||
create_clock [get_ports clk] -period $clk_period
|
||||
Warning: Design 'Vortex' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
|
||||
1
|
||||
set_max_fanout 20 [get_ports clk]
|
||||
1
|
||||
set_ideal_network [get_ports clk]
|
||||
Warning: Design 'Vortex' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
|
||||
1
|
||||
set_max_fanout 20 [get_ports reset]
|
||||
1
|
||||
set_false_path -from [get_ports reset]
|
||||
Warning: Design 'Vortex' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
|
||||
1
|
||||
# set_register_merging Vortex FALSE
|
||||
# set compile_seqmap_propagate_constants false
|
||||
# set compile_seqmap_propagate_high_effort false
|
||||
compile_ultra -no_autoungroup
|
||||
Warning: Design 'Vortex' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
|
||||
Information: Performing power optimization. (PWR-850)
|
||||
Alib files are up-to-date.
|
||||
Information: Evaluating DesignWare library utilization. (UISN-27)
|
||||
|
||||
============================================================================
|
||||
| DesignWare Building Block Library | Version | Available |
|
||||
============================================================================
|
||||
| Basic DW Building Blocks | O-2018.06-DWBB_201806.3 | * |
|
||||
| Licensed DW Building Blocks | O-2018.06-DWBB_201806.3 | * |
|
||||
============================================================================
|
||||
|
||||
Information: Sequential output inversion is enabled. SVF file must be used for formal verification. (OPT-1208)
|
||||
|
||||
Information: There are 8821 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
|
||||
|
||||
Information: Uniquified 4 instances of design 'VX_alu'. (OPT-1056)
|
||||
Information: Uniquified 10 instances of design 'VX_generic_priority_encoder_N4'. (OPT-1056)
|
||||
Information: Uniquified 9 instances of design 'VX_countones_N4'. (OPT-1056)
|
||||
Information: Uniquified 8 instances of design 'VX_shared_memory_block'. (OPT-1056)
|
||||
Information: Uniquified 4 instances of design 'VX_priority_encoder_w_mask_N4'. (OPT-1056)
|
||||
Information: Uniquified 4 instances of design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS2_CACHE_BLOCK64_CACHE_BANKS4_LOG_NUM_BANKS2_NUM_REQ4_LOG_NUM_REQ2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_OFFSET_SIZE_START0_OFFSET_SIZE_END1_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_ADDR_TAG_START13_ADDR_TAG_END31_ADDR_OFFSET_START4_ADDR_OFFSET_END5_ADDR_IND_START6_ADDR_IND_END12'. (OPT-1056)
|
||||
Information: Uniquified 2 instances of design 'VX_countones_N8'. (OPT-1056)
|
||||
Information: Uniquified 8 instances of design 'VX_generic_stack_WIDTH37_DEPTH3'. (OPT-1056)
|
||||
Information: Uniquified 8 instances of design 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__'. (OPT-1056)
|
||||
Information: Uniquified 4 instances of design 'VX_cache_data_per_index_CACHE_WAYS2_NUM_IND128_CACHE_WAY_INDEX1_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (OPT-1056)
|
||||
Information: Uniquified 10 instances of design 'VX_generic_priority_encoder_N2'. (OPT-1056)
|
||||
Information: Uniquified 8 instances of design 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6'. (OPT-1056)
|
||||
Information: Uniquified 2 instances of design 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4'. (OPT-1056)
|
||||
Simplifying Design 'Vortex'
|
||||
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_7'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_7'. (LINK-5)
|
||||
Information: Building the design 'rf2_32x19_wm0'. (HDL-193)
|
||||
Warning: Cannot find the design 'rf2_32x19_wm0' in the library 'WORK'. (LBR-1)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_6'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_6'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_5'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_5'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_4'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_4'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_3'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_3'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_2'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_2'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_1'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_1'. (LINK-5)
|
||||
Error: Width mismatch on port 'AA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_0'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_0'. (LINK-5)
|
||||
Error: Width mismatch on port 'TAA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_1'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_1'. (LINK-5)
|
||||
Error: Width mismatch on port 'TAA' of reference to 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_0'. (LINK-3)
|
||||
Warning: Unable to resolve reference 'rf2_32x128_wm1' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_0'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_7'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_6'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_5'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_4'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_3'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_2'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_1'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND128_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END18_IND_SIZE_START0_IND_SIZE_END6_0'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_1'. (LINK-5)
|
||||
Warning: Unable to resolve reference 'rf2_32x19_wm0' in 'VX_cache_data_NUM_IND32_NUM_WORDS_PER_BLOCK4_TAG_SIZE_START0_TAG_SIZE_END22_IND_SIZE_START0_IND_SIZE_END4_0'. (LINK-5)
|
||||
Loaded alib file './alib-52/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db.alib'
|
||||
Information: State dependent leakage is now switched from on to off.
|
||||
|
||||
Beginning Pass 1 Mapping
|
||||
------------------------
|
||||
Processing 'VX_shared_memory_NB7_BITS_PER_BANK3'
|
||||
726463
syn/dc_1GHz.log
726463
syn/dc_1GHz.log
File diff suppressed because it is too large
Load diff
523776
syn/dc_noOpt.log
523776
syn/dc_noOpt.log
File diff suppressed because it is too large
Load diff
2830
syn/vortex_syn.log
2830
syn/vortex_syn.log
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue