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remove temp files

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This commit is contained in:
Blaise Tine 2020-03-01 00:30:36 -05:00
parent ef2c8f3cb9
commit 857bb54f3f
31 changed files with 19684 additions and 12542 deletions
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simX/obj_dir/Vcache_simX
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simX/obj_dir/Vcache_simX.cpp
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87
simX/obj_dir/Vcache_simX.h
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@ -11,10 +11,10 @@
#include "verilated.h"
class Vcache_simX__Syms;
class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_Cache_Bank__pi8;
class Vcache_simX_VX_Cache_Bank__pi9;
class VerilatedVcd;
//----------
@ -24,13 +24,17 @@ VL_MODULE(Vcache_simX) {
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dcache_request_inter* __PVT__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// PORTS
// The application code writes and reads these signals to
@ -101,37 +105,27 @@ VL_MODULE(Vcache_simX) {
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update,0,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way,1,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way,31,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata,511,0,16);
@ -162,33 +156,21 @@ VL_MODULE(Vcache_simX) {
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank,127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use,22,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write,127,0,4);
VL_SIG64(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way,45,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way,255,0,8);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way,255,0,8);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4],3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1],0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],22,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],22,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[4],0,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
@ -219,6 +201,9 @@ VL_MODULE(Vcache_simX) {
static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[16],1,0);
static VL_ST_SIG8(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[16],0,0);
static VL_ST_SIG(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[16],31,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1,6,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2,6,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids,15,0);
@ -239,9 +224,15 @@ VL_MODULE(Vcache_simX) {
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(__Vtableidx1,3,0);
VL_SIG8(__Vtableidx2,3,0);
VL_SIG8(__Vtableidx3,3,0);
@ -251,10 +242,12 @@ VL_MODULE(Vcache_simX) {
VL_SIG8(__Vtableidx7,3,0);
VL_SIG8(__Vtableidx8,3,0);
VL_SIG8(__Vtableidx9,3,0);
VL_SIG8(__Vtableidx10,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address,127,0,4);
VL_SIG(__Vm_traceActivity,31,0);

6
simX/obj_dir/Vcache_simX.mk
View file

@ -12,9 +12,9 @@ PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
SYSTEMC_INCLUDE ?= /opt/systemc/include
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
SYSTEMC_LIBDIR ?= /opt/systemc/lib
### Switches...
# SystemC output mode? 0/1 (from --sc)
@ -33,7 +33,7 @@ VM_PREFIX = Vcache_simX
VM_MODPREFIX = Vcache_simX
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fPIC -O3 \
-std=c++11 -fPIC -O3 -Wall -Wextra -pedantic \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \

3934
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp
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File diff suppressed because it is too large Load diff

46
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h
View file

@ -40,10 +40,14 @@ VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
VL_SIG8(__PVT__valid_use,0,0);
VL_SIG8(__PVT__access,0,0);
VL_SIG8(__PVT__write_from_mem,0,0);
VL_SIG8(__PVT__miss,0,0);
VL_SIG8(__PVT__way_to_update,0,0);
VL_SIG8(__PVT__sb_mask,3,0);
VL_SIG16(__PVT__we,15,0);
VL_SIG8(__PVT__genblk1__BRA__0__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__genblk1__BRA__1__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__genblk1__BRA__2__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__genblk1__BRA__3__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__data_structures__DOT__valid_use_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__dirty_use_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__hit_per_way,1,0);
@ -54,8 +58,6 @@ VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
VL_SIG8(__PVT__data_structures__DOT__invalid_index,0,0);
VL_SIG8(__PVT__data_structures__DOT__way_use_Qual,0,0);
VL_SIG8(__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG(__PVT__tag_use,20,0);
VL_SIG(__PVT__data_unQual,31,0);
VL_SIG(__PVT__use_write_data,31,0);
@ -77,109 +79,149 @@ VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
// LOCAL VARIABLES
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VL_SIG8(data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use,0,0);
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VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
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VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,0,0);

36
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp
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@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,i_m_readdata);
}

53
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h
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@ -1,53 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
public:
// PORTS
// LOCAL SIGNALS
VL_SIGW(i_m_readdata,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset();
public:
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

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2
simX/obj_dir/Vcache_simX__ALLcls.cpp
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@ -2,6 +2,6 @@
#define VL_INCLUDE_OPT include
#include "Vcache_simX.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
#include "Vcache_simX_VX_dcache_request_inter.cpp"
#include "Vcache_simX_VX_Cache_Bank__pi9.cpp"
#include "Vcache_simX_VX_Cache_Bank__pi8.cpp"

7
simX/obj_dir/Vcache_simX__ALLcls.d
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@ -3,9 +3,8 @@ Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi9.h \
Vcache_simX_VX_Cache_Bank__pi8.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \
Vcache_simX_VX_dcache_request_inter.cpp \
Vcache_simX_VX_Cache_Bank__pi8.cpp
Vcache_simX_VX_Cache_Bank__pi9.cpp Vcache_simX_VX_Cache_Bank__pi8.cpp

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6
simX/obj_dir/Vcache_simX__ALLsup.d
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@ -5,6 +5,6 @@ Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
/usr/share/verilator/include/verilated_config.h Vcache_simX__Syms.h \
/usr/share/verilator/include/verilated.h Vcache_simX.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \
Vcache_simX__Syms.cpp Vcache_simX__Trace__Slow.cpp
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi9.h \
Vcache_simX_VX_Cache_Bank__pi8.h Vcache_simX__Syms.cpp \
Vcache_simX__Trace__Slow.cpp

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16
simX/obj_dir/Vcache_simX__Syms.cpp
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@ -4,8 +4,8 @@
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi9.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// FUNCTIONS
@ -22,6 +22,10 @@ Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[0].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[3].bank_structure"))
{
// Pointer to top level
TOPp = topp;
@ -33,13 +37,21 @@ Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
}

8
simX/obj_dir/Vcache_simX__Syms.h
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@ -11,8 +11,8 @@
// INCLUDE MODULE CLASSES
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi9.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// SYMS CLASS
@ -28,11 +28,15 @@ class Vcache_simX__Syms : public VerilatedSyms {
Vcache_simX* TOPp;
Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// CREATORS
Vcache_simX__Syms(Vcache_simX* topp, const char* namep);

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2
simX/obj_dir/Vcache_simX__ver.d
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@ -1 +1 @@
obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v
obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v

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simX/obj_dir/Vcache_simX__verFiles.dat
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@ -1,43 +1,43 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 4200738 1579395713 628434579 1579395713 628434579 "../rtl/./VX_define_synth.v"
S 283 4200733 1579395713 624434332 1579395713 624434332 "../rtl/VX_countones.v"
S 7240 4200737 1579395713 628434579 1579395713 628434579 "../rtl/VX_define.v"
S 8325 4200739 1579395713 628434579 1579395713 628434579 "../rtl/VX_dmem_controller.v"
S 517 4200743 1579395713 628434579 1579395713 628434579 "../rtl/VX_generic_priority_encoder.v"
S 683 4200754 1579395713 628434579 1579395713 628434579 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 4200764 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_Cache_Bank.v"
S 748 4200765 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 4200766 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_data.v"
S 6476 4200767 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 4200768 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_d_cache.v"
S 393 4200780 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 4200781 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 4200782 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 4200791 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 4200792 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_icache_response_inter.v"
S 7240 4200737 1579395713 628434579 1579395713 628434579 "../rtl/shared_memory/../VX_define.v"
S 676 4200836 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 4200837 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 4200838 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 4200839 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5279832 2492902 1578745602 593855204 1519110675 0 "/usr/bin/verilator_bin"
S 3144 4201058 1579395714 588493892 1579395714 588493892 "cache_simX.v"
T 606556 4194579 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX.cpp"
T 31121 4194577 1579629057 321619018 1579629057 321619018 "obj_dir/Vcache_simX.h"
T 2305 4196430 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX.mk"
T 539818 4194597 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 19062 4194595 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 1024 4194591 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 4194589 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 4194587 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
T 1556 4194585 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
T 999 4194583 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 4194581 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 3807 4194517 1579629057 293619017 1579629057 293619017 "obj_dir/Vcache_simX__Syms.cpp"
T 1918 4194514 1579629057 293619017 1579629057 293619017 "obj_dir/Vcache_simX__Syms.h"
T 704422 4194575 1579629057 317619018 1579629057 317619018 "obj_dir/Vcache_simX__Trace.cpp"
T 921157 4194573 1579629057 309619018 1579629057 309619018 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1461 4196431 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX__ver.d"
T 0 0 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX__verFiles.dat"
T 1403 4196429 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX_classes.mk"
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 1407374883617647 1583036691 972658000 1583036691 972658000 "../rtl/./VX_define_synth.v"
S 283 1407374883617640 1583036691 969666100 1583036691 969666100 "../rtl/VX_countones.v"
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/VX_define.v"
S 8325 1407374883617648 1583036691 973655300 1583036691 973655300 "../rtl/VX_dmem_controller.v"
S 517 1407374883617652 1583036691 975649300 1583036691 975649300 "../rtl/VX_generic_priority_encoder.v"
S 683 1407374883617664 1583036691 981634100 1583036691 981634100 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 1407374883617675 1583036691 985623400 1583036691 985623400 "../rtl/cache/VX_Cache_Bank.v"
S 748 1407374883617676 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 1407374883617677 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_data.v"
S 6476 1407374883617678 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 1407374883617679 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_d_cache.v"
S 393 1407374883617692 1583036691 993601900 1583036691 993601900 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 1407374883617693 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 1407374883617694 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 1407374883617709 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 1407374883617710 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_response_inter.v"
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/shared_memory/../VX_define.v"
S 676 1407374883617754 1583036692 20529900 1583036692 20529900 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 1407374883617755 1583036692 21526400 1583036692 21526400 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 1407374883617756 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 1407374883617757 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5279832 1125899907857040 1579658333 790142700 1519110675 0 "/usr/bin/verilator_bin"
S 3144 1407374883617983 1583036693 278327800 1583036693 278327800 "cache_simX.v"
T 390173 4222124650721525 1583038884 772480200 1583038884 772480200 "obj_dir/Vcache_simX.cpp"
T 28278 5066549580853492 1583038884 765499600 1583038884 765499600 "obj_dir/Vcache_simX.h"
T 2365 18858823439675736 1583038884 803378700 1583038884 803378700 "obj_dir/Vcache_simX.mk"
T 643931 2533274790457603 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 23659 2533274790457602 1583038884 788131800 1583038884 788131800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 578414 2533274790457601 1583038884 787134700 1583038884 787134700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
T 23321 4222124650721534 1583038884 776161100 1583038884 776161100 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
T 1024 2251799813746939 1583038884 775163700 1583038884 775163700 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 5348024557564153 1583038884 774165800 1583038884 774165800 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 2533274790457592 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 2814749767168246 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 6004 14073748835594442 1583038884 720643500 1583038884 720643500 "obj_dir/Vcache_simX__Syms.cpp"
T 2455 3096224743878468 1583038884 719619200 1583038884 719619200 "obj_dir/Vcache_simX__Syms.h"
T 1114242 5066549580853489 1583038884 763504200 1583038884 763504200 "obj_dir/Vcache_simX__Trace.cpp"
T 1433229 3377699720589552 1583038884 745891000 1583038884 745891000 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1439 1688849860325816 1583038884 804364500 1583038884 804364500 "obj_dir/Vcache_simX__ver.d"
T 0 0 1583038884 836313300 1583038884 836313300 "obj_dir/Vcache_simX__verFiles.dat"
T 1392 2251799813746948 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_classes.mk"

2
simX/obj_dir/Vcache_simX_classes.mk
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@ -17,8 +17,8 @@ VM_TRACE = 1
VM_CLASSES_FAST += \
Vcache_simX \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \
Vcache_simX_VX_dcache_request_inter \
Vcache_simX_VX_Cache_Bank__pi9 \
Vcache_simX_VX_Cache_Bank__pi8 \
# Generated module classes, non-fast-path, compile with low/medium optimization

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simX/obj_dir/core.o
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1
simX/obj_dir/emulator.debug
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@ -1 +0,0 @@
../rvvector/basic/vx_vector_main.hex not found

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simX/obj_dir/enc.o
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simX/obj_dir/instruction.o
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simX/obj_dir/mem.o
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simX/obj_dir/simX.o
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simX/out
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@ -1,2 +0,0 @@
verilator --compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS '-std=c++11 -fPIC -O3' -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1
Makefile:26: recipe for target 'simX' failed

1
simX/reading_data.txt
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@ -1 +0,0 @@
hello this is the data read from a file!

1
simX/results.txt
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@ -1 +0,0 @@
start

0
simX/test_rv32ui.sh Normal file → Executable file
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