mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
simx lkg build
This commit is contained in:
Blaise Tine
parent
10a994d11a
commit
71e9745e68
7 changed files with 240 additions and 498 deletions
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@ -159,7 +159,7 @@ public:
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}
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int set_csr(int core_id, int addr, unsigned value) {
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cores_.at(core_id)->set_csr(addr, value);
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cores_.at(core_id)->set_csr(addr, value, 0, 0);
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return 0;
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}
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@ -78,7 +78,7 @@ static const char* op_string(const Instr &instr) {
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}
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case Opcode::I_INST:
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switch (func3) {
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case 0: return func7 ? "SUBI" : "ADDI";
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case 0: return "ADDI";
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case 1: return "SLLI";
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case 2: return "SLTI";
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case 3: return "SLTIU";
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@ -163,10 +163,10 @@ static const char* op_string(const Instr &instr) {
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default:
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std::abort();
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}
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case 0x60: return rs2 ? "FCVT.WU" : "FCVT.W";
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case 0x68: return rs2 ? "FCVT.S" : "FCVT.S";
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case 0x60: return rs2 ? "FCVT.WU.S" : "FCVT.W.S";
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case 0x68: return rs2 ? "FCVT.S.WU" : "FCVT.S.W";
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case 0x70: return func3 ? "FLASS" : "FMV.X.W";
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case 0x78: return "FMV.W";
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case 0x78: return "FMV.W.X";
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default:
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std::abort();
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}
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@ -283,11 +283,18 @@ std::shared_ptr<Instr> Decoder::decode(Word code) {
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case InstType::R_TYPE:
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if (op == Opcode::FCI) {
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instr->setSrcFReg(rs1);
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switch (func7) {
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case 0x68: // FCVT.S.W, FCVT.S.WU
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case 0x78: // FMV.W.X
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instr->setSrcReg(rs1);
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break;
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default:
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instr->setSrcFReg(rs1);
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}
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instr->setSrcFReg(rs2);
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switch (func7) {
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case 0x50: // FLE, FLT, FEQ
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case 0x60: // FCVT.WU, FCVT.W
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case 0x60: // FCVT.WU.S, FCVT.W.S
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case 0x70: // FLASS, FMV.X.W
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instr->setDestReg(rd);
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break;
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@ -304,12 +311,11 @@ std::shared_ptr<Instr> Decoder::decode(Word code) {
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break;
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case InstType::I_TYPE: {
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if (op == Opcode::FCI || op == Opcode::FL) {
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instr->setDestFReg(rd);
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instr->setSrcFReg(rs1);
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instr->setSrcReg(rs1);
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if (op == Opcode::FL) {
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instr->setDestFReg(rd);
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} else {
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instr->setDestReg(rd);
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instr->setSrcReg(rs1);
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}
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instr->setFunc3(func3);
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instr->setFunc7(func7);
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@ -320,12 +326,11 @@ std::shared_ptr<Instr> Decoder::decode(Word code) {
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}
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} break;
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case InstType::S_TYPE: {
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case InstType::S_TYPE: {
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instr->setSrcReg(rs1);
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if (op == Opcode::FS) {
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instr->setSrcFReg(rs1);
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instr->setSrcFReg(rs2);
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} else {
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instr->setSrcReg(rs1);
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instr->setSrcReg(rs2);
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}
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instr->setFunc3(func3);
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501
simX/execute.cpp
501
simX/execute.cpp
File diff suppressed because it is too large
Load diff
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@ -1,9 +0,0 @@
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#!/bin/bash
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echo start > results.txt
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make
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printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
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#./simX -a rv32i -i ../benchmarks/vector/vecadd/vx_vec_vecadd.hex -s 1> emulator.debug
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#./simX -a rv32i -i ../benchmarks/vector/saxpy/vx_vec_saxpy.hex -s 1> emulator.debug
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./simX -a rv32i -i ../benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.hex -s 1> emulator.debug
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@ -1,142 +0,0 @@
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#!/bin/bash
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make
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echo start > results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-add.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-add.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-addi.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-addi.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-and.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-and.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-andi.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-andi.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-auipc.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-auipc.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-beq.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-beq.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bge.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bge.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bgeu.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bgeu.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-blt.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-blt.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bltu.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bltu.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bne.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bne.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-jal.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-jal.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-jalr.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-jalr.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lb.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lb.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lbu.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lbu.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lh.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lh.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lhu.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lhu.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lui.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lui.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lw.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lw.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-or.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-or.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-ori.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-ori.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sb.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sb.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sh.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sh.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-simple.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-simple.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sll.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sll.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-slli.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-slli.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-slt.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-slt.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-slti.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-slti.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sltiu.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sltiu.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sltu.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sltu.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sra.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sra.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-srai.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-srai.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-srl.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-srl.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-srli.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-srli.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sub.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sub.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sw.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sw.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-xor.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-xor.hex -s >> results.txt
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echo ./../benchmarks/isa/riscv_tests/rv32ui-p-xori.hex >> results.txt
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./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-xori.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-div.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-div.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-divu.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-divu.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mul.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mul.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mulh.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mulh.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mulhsu.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mulhsu.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mulhu.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mulhu.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-rem.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-rem.hex -s >> results.txt
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# echo ./../benchmarks/isa/riscv_tests/rv32um-p-remu.hex >> results.txt
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# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-remu.hex -s >> results.txt
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@ -1,8 +0,0 @@
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#!/bin/bash
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echo start > results.txt
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# echo ../kernel/vortex_test.hex
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make
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printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
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./Vcache_simX -a rv32i -i ../rvvector/basic/vx_vector_main.hex -s 1> emulator.debug
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45
simX/trace.h
45
simX/trace.h
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@ -1,45 +0,0 @@
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#pragma once
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namespace vortex {
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struct trace_inst_t {
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// Warp step
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bool valid;
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unsigned PC;
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// Core scheduler
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int wid;
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// Encoder
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int irs1;
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int irs2;
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int ird;
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// Floating-point
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int frs1;
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int frs2;
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int frs3;
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int frd;
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// Vector extension
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int vrs1;
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int vrs2;
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int vrd;
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// Instruction execute
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bool is_lw;
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bool is_sw;
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unsigned * mem_addresses;
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// dmem interface
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unsigned long mem_stall_cycles;
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unsigned long fetch_stall_cycles;
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// Instruction execute
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bool stall_warp;
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bool wspawn;
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bool stalled;
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};
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}
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