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fixed cache msrq reset logic

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This commit is contained in:
Blaise Tine 2020-05-20 18:11:31 -04:00
parent cefd0d85af
commit 72d54c749c
2 changed files with 5 additions and 7 deletions
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2
driver/rtlsim/Makefile
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@ -15,7 +15,7 @@ DBG_PRINT = -DDBG_PRINT_CORE_ICACHE \
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
DEBUG = 1
#DEBUG = 1
CFLAGS += -fPIC

10
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@ -66,7 +66,7 @@ module VX_cache_miss_resrv #(
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5));
wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
`IGNORE_WARNINGS_BEGIN
wire [31:0] make_ready_push_full;
@ -125,11 +125,9 @@ module VX_cache_miss_resrv #(
end
if (mrvq_pop) begin
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
addr_table[dequeue_index] <= 0;
metadata_table[dequeue_index] <= 0;
head_ptr <= head_ptr + 1;
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
head_ptr <= head_ptr + 1;
end
if (!(mrvq_push && mrvq_pop)) begin