github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

synthesis updates

Browse source
This commit is contained in:
Blaise Tine 2024-09-20 20:35:58 -07:00
parent a61f97f6c6
commit 7938c7be5f
15 changed files with 237 additions and 179 deletions
Download patch file Download diff file Expand all files Collapse all files

114
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -40,7 +40,6 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
output t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS],
input wire avs_readdatavalid [NUM_LOCAL_MEM_BANKS]
);
localparam LMEM_DATA_WIDTH = $bits(t_local_mem_data);
localparam LMEM_DATA_SIZE = LMEM_DATA_WIDTH / 8;
localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr);
@ -50,6 +49,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8;
localparam CCI_ADDR_WIDTH = $bits(t_ccip_clAddr);
localparam RESET_CTR_WIDTH = `CLOG2(`RESET_DELAY+1);
localparam AVS_RD_QUEUE_SIZE = 32;
localparam _VX_MEM_TAG_WIDTH = `VX_MEM_TAG_WIDTH;
localparam _AVS_REQ_TAGW_VX = _VX_MEM_TAG_WIDTH + `CLOG2(LMEM_DATA_WIDTH) - `CLOG2(`VX_MEM_DATA_WIDTH);
@ -185,7 +186,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
end
if (cmd_scope_writing) begin
scope_bus_in <= 1'(cmd_scope_wdata >> scope_bus_ctr);
scope_bus_ctr <= scope_bus_ctr - 1;
scope_bus_ctr <= scope_bus_ctr - 6'd1;
if (scope_bus_ctr == 0) begin
cmd_scope_writing <= 0;
scope_bus_in <= 0;
@ -193,7 +194,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
end
if (cmd_scope_reading) begin
cmd_scope_rdata <= {cmd_scope_rdata[62:0], scope_bus_out};
scope_bus_ctr <= scope_bus_ctr - 1;
scope_bus_ctr <= scope_bus_ctr - 6'd1;
if (scope_bus_ctr == 0) begin
cmd_scope_reading <= 0;
end
@ -344,7 +345,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
wire cmd_mem_rd_done;
reg cmd_mem_wr_done;
reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
reg [RESET_CTR_WIDTH-1:0] vx_reset_ctr;
reg vx_busy_wait;
reg vx_reset = 1; // asserted at initialization
wire vx_busy;
@ -384,7 +385,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
`TRACE(2, ("%t: AFU: Goto STATE RUN\n", $time))
`endif
state <= STATE_RUN;
vx_reset_ctr <= (`RESET_DELAY-1);
vx_reset_ctr <= RESET_CTR_WIDTH'(`RESET_DELAY-1);
vx_reset <= 1;
end
default: begin
@ -414,7 +415,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
STATE_RUN: begin
if (vx_reset) begin
// wait until the reset network is ready
if (vx_reset_ctr == 0) begin
if (vx_reset_ctr == RESET_CTR_WIDTH'(0)) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%t: AFU: Begin execution\n", $time))
`endif
@ -443,8 +444,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
endcase
// ensure reset network initialization
if (vx_reset_ctr != '0) begin
vx_reset_ctr <= vx_reset_ctr - 1;
if (vx_reset_ctr != RESET_CTR_WIDTH'(0)) begin
vx_reset_ctr <= vx_reset_ctr - RESET_CTR_WIDTH'(1);
end
end
end
@ -1013,61 +1014,64 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
end
wire state_changed = (state != state_prev);
`define AFU_TRIGGERS { \
reset, \
state_changed, \
mem_req_fire, \
mem_rsp_fire, \
avs_write_fire, \
avs_read_fire, \
avs_waitrequest[0], \
avs_readdatavalid[0], \
cp2af_sRxPort.c0.mmioRdValid, \
cp2af_sRxPort.c0.mmioWrValid, \
cp2af_sRxPort.c0.rspValid, \
cp2af_sRxPort.c1.rspValid, \
af2cp_sTxPort.c0.valid, \
af2cp_sTxPort.c1.valid, \
cp2af_sRxPort.c0TxAlmFull, \
cp2af_sRxPort.c1TxAlmFull, \
af2cp_sTxPort.c2.mmioRdValid, \
cci_wr_req_fire, \
cci_wr_rsp_fire, \
cci_rd_req_fire, \
cci_rd_rsp_fire, \
cci_pending_reads_full, \
cci_pending_writes_empty, \
cci_pending_writes_full \
}
`define AFU_PROBES { \
cmd_type, \
state, \
mmio_req_hdr.address, \
cp2af_sRxPort.c0.hdr.mdata, \
af2cp_sTxPort.c0.hdr.address, \
af2cp_sTxPort.c0.hdr.mdata, \
af2cp_sTxPort.c1.hdr.address, \
avs_address[0], \
avs_byteenable[0], \
avs_burstcount[0], \
cci_mem_rd_req_ctr, \
cci_mem_wr_req_ctr, \
cci_rd_req_ctr, \
cci_rd_rsp_ctr, \
cci_wr_req_ctr, \
mem_bus_if_addr \
}
VX_scope_tap #(
.SCOPE_ID (0),
.TRIGGERW (24),
.PROBEW (431),
.TRIGGERW ($bits(`AFU_TRIGGERS)),
.PROBEW ($bits(`AFU_PROBES)),
.DEPTH (4096)
) scope_tap (
.clk(clk),
.reset(scope_reset_w[0]),
.start(1'b0),
.stop(1'b0),
.triggers({
reset,
state_changed,
mem_req_fire,
mem_rsp_fire,
avs_write_fire,
avs_read_fire,
avs_waitrequest[0],
avs_readdatavalid[0],
cp2af_sRxPort.c0.mmioRdValid,
cp2af_sRxPort.c0.mmioWrValid,
cp2af_sRxPort.c0.rspValid,
cp2af_sRxPort.c1.rspValid,
af2cp_sTxPort.c0.valid,
af2cp_sTxPort.c1.valid,
cp2af_sRxPort.c0TxAlmFull,
cp2af_sRxPort.c1TxAlmFull,
af2cp_sTxPort.c2.mmioRdValid,
cci_wr_req_fire,
cci_wr_rsp_fire,
cci_rd_req_fire,
cci_rd_rsp_fire,
cci_pending_reads_full,
cci_pending_writes_empty,
cci_pending_writes_full
}),
.probes({
cmd_type,
state,
mmio_req_hdr.address,
mmio_req_hdr.length,
cp2af_sRxPort.c0.hdr.mdata,
af2cp_sTxPort.c0.hdr.address,
af2cp_sTxPort.c0.hdr.mdata,
af2cp_sTxPort.c1.hdr.address,
avs_address[0],
avs_byteenable[0],
avs_burstcount[0],
cci_mem_rd_req_ctr,
cci_mem_wr_req_ctr,
cci_rd_req_ctr,
cci_rd_rsp_ctr,
cci_wr_req_ctr,
mem_bus_if_addr
}),
.triggers(`AFU_TRIGGERS),
.probes(`AFU_PROBES),
.bus_in(scope_bus_in_w[0]),
.bus_out(scope_bus_out_w[0])
);

44
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -301,7 +301,7 @@ module VX_afu_wrap #(
`ifdef DBG_SCOPE_AFU
`ifdef SCOPE
`define TRIGGERS { \
`define AFU_TRIGGERS { \
reset, \
ap_reset, \
ap_start, \
@ -311,41 +311,41 @@ module VX_afu_wrap #(
vx_busy_wait, \
vx_busy, \
vx_reset, \
m_axi_mem_awvalid_a, \
m_axi_mem_awready_a, \
m_axi_mem_wvalid_a, \
m_axi_mem_wready_a, \
m_axi_mem_bvalid_a, \
m_axi_mem_bready_a, \
m_axi_mem_arvalid_a, \
m_axi_mem_arready_a, \
m_axi_mem_rvalid_a, \
m_axi_mem_rready_a, \
m_axi_mem_awvalid_a[0], \
m_axi_mem_awready_a[0], \
m_axi_mem_wvalid_a[0], \
m_axi_mem_wready_a[0], \
m_axi_mem_bvalid_a[0], \
m_axi_mem_bready_a[0], \
m_axi_mem_arvalid_a[0], \
m_axi_mem_arready_a[0], \
m_axi_mem_rvalid_a[0], \
m_axi_mem_rready_a[0], \
dcr_wr_valid \
}
`define PROBES { \
`define AFU_PROBES { \
vx_pending_writes, \
m_axi_mem_awaddr_u, \
m_axi_mem_awid_a, \
m_axi_mem_bid_a, \
m_axi_mem_araddr_u, \
m_axi_mem_arid_a, \
m_axi_mem_rid_a, \
m_axi_mem_awaddr_u[0], \
m_axi_mem_awid_a[0], \
m_axi_mem_bid_a[0], \
m_axi_mem_araddr_u[0], \
m_axi_mem_arid_a[0], \
m_axi_mem_rid_a[0], \
dcr_wr_addr, \
dcr_wr_data \
}
VX_scope_tap #(
.SCOPE_ID (0),
.TRIGGERW ($bits(`TRIGGERS)),
.PROBEW ($bits(`PROBES)),
.TRIGGERW ($bits(`AFU_TRIGGERS)),
.PROBEW ($bits(`AFU_PROBES)),
.DEPTH (4096)
) scope_tap (
.clk (clk),
.reset (scope_reset_w[0]),
.start (1'b0),
.stop (1'b0),
.triggers (`TRIGGERS),
.probes (`PROBES),
.triggers (`AFU_TRIGGERS),
.probes (`AFU_PROBES),
.bus_in (scope_bus_in_w[0]),
.bus_out (scope_bus_out_w[0])
);

7
hw/rtl/core/VX_issue_top.sv
View file

@ -113,6 +113,13 @@ module VX_issue_top import VX_gpu_pkg::*; #(
issue_perf_t issue_perf = '0;
`endif
`ifdef SCOPE
wire [0:0] scope_reset_w = 1'b0;
wire [0:0] scope_bus_in_w = 1'b0;
wire [0:0] scope_bus_out_w;
`UNUSED_VAR (scope_bus_out_w)
`endif
VX_issue #(
.INSTANCE_ID (INSTANCE_ID)
) issue (

17
hw/rtl/core/VX_lsu_slice.sv
View file

@ -536,19 +536,6 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
`ifdef DBG_SCOPE_LSU
`ifdef SCOPE
`define TRIGGERS { \
mem_req_fire, \
mem_rsp_fire \
}
`define PROBES { \
mem_req_rw, \
full_addr, \
mem_req_byteen, \
mem_req_data, \
execute_if.data.uuid, \
rsp_data, \
rsp_uuid \
}
VX_scope_tap #(
.SCOPE_ID (3),
.TRIGGERW (2),
@ -559,8 +546,8 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
.reset (scope_reset),
.start (1'b0),
.stop (1'b0),
.triggers(`TRIGGERS),
.probes (`PROBES),
.triggers({mem_req_fire, mem_rsp_fire}),
.probes ({mem_req_rw, full_addr, mem_req_byteen, mem_req_data, execute_if.data.uuid, rsp_data, rsp_uuid}),
.bus_in (scope_bus_in),
.bus_out(scope_bus_out)
);

8
hw/rtl/fpu/VX_fpu_sqrt.sv
View file

@ -101,7 +101,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
.clk (clk),
.areset (1'b0),
.en (pe_enable),
.a (pe_data_in[i]),
.a (pe_data_in[i][0 +: 32]),
.q (pe_data_out[i][0 +: 32])
);
assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x;
@ -120,7 +120,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
.aclk (clk),
.aclken (pe_enable),
.s_axis_a_tvalid (1'b1),
.s_axis_a_tdata (pe_data_in[i]),
.s_axis_a_tdata (pe_data_in[i][0 +: 32]),
`UNUSED_PIN (m_axis_result_tvalid),
.m_axis_result_tdata (pe_data_out[i][0 +: 32]),
.m_axis_result_tuser (tuser)
@ -143,8 +143,8 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
dpi_fsqrt (
pe_enable,
int'(0),
{32'hffffffff, pe_data_in[i][0 +: 32]}, // a
pe_data_in[0][32 +: `INST_FRM_BITS], // frm
{32'hffffffff, pe_data_in[i][0 +: 32]}, // a
pe_data_in[0][32 +: `INST_FRM_BITS], // frm
r,
f
);

164
hw/rtl/libs/VX_scope_tap.sv
View file

@ -17,82 +17,138 @@
module VX_scope_tap #(
parameter SCOPE_ID = 0, // scope identifier
parameter SCOPE_IDW = 8, // scope identifier width
parameter TRIGGERW = 0, // trigger signals width
parameter PROBEW = 0, // probe signal width
parameter DEPTH = 256, // trace buffer depth
parameter IDLE_CTRW = 16 // idle time between triggers counter width
parameter TRIGGERW = 16, // trigger signals width
parameter PROBEW = 256, // probe signal width
parameter DEPTH = 1024, // trace buffer depth
parameter IDLE_CTRW = 16, // idle time between triggers counter width
parameter TX_DATAW = 64 // transfer data width
) (
input wire clk,
input wire reset,
input wire start,
input wire stop,
input wire [TRIGGERW-1:0] triggers,
input wire [`UP(TRIGGERW)-1:0] triggers,
input wire [PROBEW-1:0] probes,
input wire bus_in,
output wire bus_out
);
localparam TX_DATAW = 64;
localparam TX_DATA_BITS = `LOG2UP(TX_DATAW);
localparam DATAW = PROBEW + TRIGGERW;
localparam DATA_BITS = `LOG2UP(DATAW);
localparam ADDRW = `CLOG2(DEPTH);
localparam TRIGGER_ENABLE = (TRIGGERW != 0);
localparam MAX_IDLE_CTR = (2 ** IDLE_CTRW) - 1;
localparam CTR_WIDTH = 64;
localparam TX_DATA_BITS = `LOG2UP(TX_DATAW);
localparam DATAW = PROBEW + TRIGGERW;
localparam DATA_BITS = `LOG2UP(DATAW);
localparam ADDRW = `CLOG2(DEPTH);
localparam MAX_IDLE_CTR = (2 ** IDLE_CTRW) - 1;
localparam CTRL_STATE_IDLE = 2'd0;
localparam CTRL_STATE_RECV = 2'd1;
localparam CTRL_STATE_CMD = 2'd2;
localparam CTRL_STATE_SEND = 2'd3;
localparam CTRL_STATE_BITS = 2;
localparam CTRL_STATE_IDLE = 2'd0;
localparam CTRL_STATE_RECV = 2'd1;
localparam CTRL_STATE_CMD = 2'd2;
localparam CTRL_STATE_SEND = 2'd3;
localparam CTRL_STATE_BITS = 2;
localparam TAP_STATE_IDLE = 2'd0;
localparam TAP_STATE_WAIT = 2'd1;
localparam TAP_STATE_RUN = 2'd2;
localparam TAP_STATE_BITS = 2;
localparam TAP_STATE_IDLE = 2'd0;
localparam TAP_STATE_WAIT = 2'd1;
localparam TAP_STATE_RUN = 2'd2;
localparam TAP_STATE_BITS = 2;
localparam CMD_GET_WIDTH = 3'd0;
localparam CMD_GET_COUNT = 3'd1;
localparam CMD_GET_START = 3'd2;
localparam CMD_GET_DATA = 3'd3;
localparam CMD_SET_START = 3'd4;
localparam CMD_SET_STOP = 3'd5;
localparam CMD_TYPE_BITS = 3;
localparam CMD_GET_WIDTH = 3'd0;
localparam CMD_GET_COUNT = 3'd1;
localparam CMD_GET_START = 3'd2;
localparam CMD_GET_DATA = 3'd3;
localparam CMD_SET_START = 3'd4;
localparam CMD_SET_STOP = 3'd5;
localparam CMD_TYPE_BITS = 3;
localparam GET_TYPE_WIDTH = 2'd0;
localparam GET_TYPE_COUNT = 2'd1;
localparam GET_TYPE_START = 2'd2;
localparam GET_TYPE_DATA = 2'd3;
localparam GET_TYPE_BITS = 2;
localparam GET_TYPE_WIDTH = 2'd0;
localparam GET_TYPE_COUNT = 2'd1;
localparam GET_TYPE_START = 2'd2;
localparam GET_TYPE_DATA = 2'd3;
localparam GET_TYPE_BITS = 2;
`NO_RW_RAM_CHECK reg [DATAW-1:0] data_store [DEPTH-1:0];
`NO_RW_RAM_CHECK reg [IDLE_CTRW-1:0] delta_store [DEPTH-1:0];
reg [TRIGGERW-1:0] prev_triggers;
reg [`UP(TRIGGERW)-1:0] prev_triggers;
reg [IDLE_CTRW-1:0] delta;
reg [63:0] timestamp, start_time;
reg [CTR_WIDTH-1:0] timestamp, start_time;
reg [ADDRW-1:0] waddr, waddr_end;
reg write_en;
reg cmd_start, delta_flush;
reg [63:0] start_delay, delay_cntr;
reg [CTR_WIDTH-1:0] start_delay, delay_cntr;
reg [TAP_STATE_BITS-1:0] tap_state;
reg [CTRL_STATE_BITS-1:0] ctrl_state;
reg [GET_TYPE_BITS-1:0] get_type;
wire [DATAW-1:0] data_value;
wire [IDLE_CTRW-1:0] delta_value;
reg [TX_DATA_BITS-1:0] ser_tx_ctr;
reg [DATA_BITS-1:0] read_offset;
reg [ADDRW-1:0] raddr;
reg read_data;
wire [DATAW-1:0] data_in;
if (TRIGGERW != 0) begin
assign data_in = {probes, triggers};
end else begin
assign data_in = probes;
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (DEPTH),
.NO_RWCHECK (1)
) data_store (
.clk (clk),
.reset (reset),
.read (1'b1),
.wren (1'b1),
.write (write_en),
.waddr (waddr),
.wdata (data_in),
.raddr (raddr),
.rdata (data_value)
);
if (TRIGGERW != 0) begin
VX_dp_ram #(
.DATAW (IDLE_CTRW),
.SIZE (DEPTH),
.NO_RWCHECK (1)
) delta_store (
.clk (clk),
.reset (reset),
.read (1'b1),
.wren (1'b1),
.write (write_en),
.waddr (waddr),
.wdata (delta),
.raddr (raddr),
.rdata (delta_value)
);
end else begin
assign delta_value = '0;
end
//
// trace capture
//
wire [ADDRW-1:0] raddr_n = raddr + 1;
wire [ADDRW-1:0] raddr_n = raddr + ADDRW'(1);
wire [ADDRW:0] count = (ADDRW+1)'(waddr) + 1;
wire [ADDRW:0] count = (ADDRW+1)'(waddr) + (ADDRW+1)'(1);
always @(*) begin
write_en = 0;
if (tap_state == TAP_STATE_RUN) begin
if (TRIGGERW != 0) begin
if (delta_flush || (triggers != prev_triggers)) begin
write_en = 1;
end
end else begin
write_en = 1;
end
end
end
always @(posedge clk) begin
if (reset) begin
@ -105,7 +161,7 @@ module VX_scope_tap #(
read_data <= 0;
timestamp <= '0;
end else begin
timestamp <= timestamp + 1;
timestamp <= timestamp + CTR_WIDTH'(1);
case (tap_state)
TAP_STATE_IDLE: begin
@ -128,7 +184,7 @@ module VX_scope_tap #(
end
end
TAP_STATE_WAIT: begin
delay_cntr <= delay_cntr - 1;
delay_cntr <= delay_cntr - CTR_WIDTH'(1);
if (1 == delay_cntr) begin
tap_state <= TAP_STATE_RUN;
start_time <= timestamp;
@ -138,22 +194,18 @@ module VX_scope_tap #(
end
end
TAP_STATE_RUN: begin
if (TRIGGER_ENABLE != 0) begin
if (TRIGGERW != 0) begin
if (delta_flush || (triggers != prev_triggers)) begin
data_store[waddr] <= {probes, triggers};
delta_store[waddr] <= delta;
waddr <= waddr + 1;
waddr <= waddr + ADDRW'(1);
delta <= '0;
delta_flush <= 0;
end else begin
delta <= delta + 1;
delta_flush <= (delta == (MAX_IDLE_CTR-1));
delta <= delta + IDLE_CTRW'(1);
delta_flush <= (delta == IDLE_CTRW'(MAX_IDLE_CTR-1));
end
prev_triggers <= triggers;
end else begin
data_store[waddr] <= {probes, triggers};
delta_store[waddr] <= '0;
waddr <= waddr + 1;
waddr <= waddr + ADDRW'(1);
end
if (stop || (waddr >= waddr_end)) begin
waddr <= waddr;
@ -208,8 +260,8 @@ module VX_scope_tap #(
wire [SCOPE_IDW-1:0] cmd_scope_id = ser_buf_in_n[CMD_TYPE_BITS +: SCOPE_IDW];
wire [TX_DATAW-CMD_TYPE_BITS-SCOPE_IDW-1:0] cmd_data = ser_buf_in[TX_DATAW-1:CMD_TYPE_BITS+SCOPE_IDW];
wire [TX_DATAW-1:0] data_chunk = TX_DATAW'(DATAW'(data_store[raddr] >> read_offset));
wire [TX_DATAW-1:0] get_data = read_data ? data_chunk : TX_DATAW'(delta_store[raddr]);
wire [TX_DATAW-1:0] data_chunk = TX_DATAW'(DATAW'(data_value >> read_offset));
wire [TX_DATAW-1:0] get_data = read_data ? data_chunk : TX_DATAW'(delta_value);
always @(posedge clk) begin
if (reset) begin
@ -230,7 +282,7 @@ module VX_scope_tap #(
ser_tx_ctr <= TX_DATA_BITS'(TX_DATAW-1);
end
CTRL_STATE_RECV: begin
ser_tx_ctr <= ser_tx_ctr - 1;
ser_tx_ctr <= ser_tx_ctr - TX_DATA_BITS'(1);
ser_buf_in <= ser_buf_in_n;
if (ser_tx_ctr == 0) begin
ctrl_state <= (cmd_scope_id == SCOPE_ID) ? CTRL_STATE_CMD : CTRL_STATE_IDLE;
@ -262,7 +314,7 @@ module VX_scope_tap #(
`endif
end
CTRL_STATE_SEND: begin
ser_tx_ctr <= ser_tx_ctr - 1;
ser_tx_ctr <= ser_tx_ctr - TX_DATA_BITS'(1);
case (get_type)
GET_TYPE_WIDTH: begin
bus_out_r <= 1'(DATAW >> ser_tx_ctr);

10
hw/syn/altera/dut/Makefile
View file

@ -9,7 +9,7 @@ SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
.PHONY: unittest pipeline mem_unit lmem cache fpu core issue vortex top
.PHONY: unittest scope mem_unit lmem cache fpu core issue vortex top
ip-gen: $(IP_CACHE_DIR)/ip_gen.log
$(IP_CACHE_DIR)/ip_gen.log:
@ -20,10 +20,10 @@ unittest:
cp unittest/Makefile unittest/$(BUILD_DIR)
$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
pipeline:
mkdir -p pipeline/$(BUILD_DIR)
cp pipeline/Makefile pipeline/$(BUILD_DIR)
$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
scope:
mkdir -p scope/$(BUILD_DIR)
cp scope/Makefile scope/$(BUILD_DIR)
$(MAKE) -C scope/$(BUILD_DIR) clean && $(MAKE) -C scope/$(BUILD_DIR) > scope/$(BUILD_DIR)/build.log 2>&1 &
mem_unit:
mkdir -p mem_unit/$(BUILD_DIR)

7
hw/syn/altera/dut/scope/Makefile Executable file
View file

@ -0,0 +1,7 @@
PROJECT = VX_scope_tap
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs

8
hw/syn/altera/opae/Makefile
View file

@ -36,7 +36,6 @@ DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
ifeq ($(DEVICE_FAMILY), stratix10)
CONFIGS += -DALTERA_S10
@ -55,9 +54,12 @@ CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
# include paths
# include sources
RTL_PKGS = $(AFU_DIR)/local_mem_cfg_pkg.sv $(AFU_DIR)/ccip/ccip_if_pkg.sv
RTL_PKGS += $(RTL_DIR)/VX_gpu_pkg.sv $(RTL_DIR)/fpu/VX_fpu_pkg.sv
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
RTL_PKGS += $(THIRD_PARTY_DIR)/cvfpu/src/fpnew_pkg.sv $(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src/cf_math_pkg $(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/include -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src -J$(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/cvfpu/src
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
@ -96,7 +98,7 @@ ifdef PERF
endif
# ast dump flags
XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DNOPAE
XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) $(RTL_PKGS) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DPLATFORM_PROVIDES_LOCAL_MEMORY -DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=2 -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=26 -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=512 -DPLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH=4 -DNOPAE -DSV_DPI
all: swconfig ip-gen setup build

10
hw/syn/xilinx/dut/Makefile
View file

@ -5,17 +5,17 @@ PREFIX ?= build
BUILD_DIR := $(PREFIX)
.PHONY: unittest pipeline mem_unit lmem cache fpu core issue vortex top
.PHONY: unittest scope mem_unit lmem cache fpu core issue vortex top
unittest:
mkdir -p unittest/$(BUILD_DIR)
cp unittest/Makefile unittest/$(BUILD_DIR)
$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
pipeline:
mkdir -p pipeline/$(BUILD_DIR)
cp pipeline/Makefile pipeline/$(BUILD_DIR)
$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
scope:
mkdir -p scope/$(BUILD_DIR)
cp scope/Makefile scope/$(BUILD_DIR)
$(MAKE) -C scope/$(BUILD_DIR) clean && $(MAKE) -C scope/$(BUILD_DIR) > scope/$(BUILD_DIR)/build.log 2>&1 &
mem_unit:
mkdir -p mem_unit/$(BUILD_DIR)

7
hw/syn/xilinx/dut/scope/Makefile Normal file
View file

@ -0,0 +1,7 @@
PROJECT = VX_scope_tap
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs

16
hw/syn/xilinx/xrt/Makefile
View file

@ -63,10 +63,6 @@ DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_TEX
DBG_SCOPE_FLAGS += -DDBG_SCOPE_OM
DBG_SCOPE_FLAGS += -DDBG_SCOPE_RASTER
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
# cluster configuration
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
@ -78,9 +74,11 @@ CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
# include paths
# include sources
RTL_PKGS = $(RTL_DIR)/VX_gpu_pkg.sv $(RTL_DIR)/fpu/VX_fpu_pkg.sv
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
RTL_PKGS += $(THIRD_PARTY_DIR)/cvfpu/src/fpnew_pkg.sv $(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src/cf_math_pkg $(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/include -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src -J$(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/cvfpu/src
endif
TEX_INCLUDE = -I$(RTL_DIR)/tex
@ -152,7 +150,7 @@ CFLAGS += $(CONFIGS)
CFLAGS += $(RTL_INCLUDE)
# ast dump flags
XML_CFLAGS = $(filter-out -DSYNTHESIS -DVIVADO, $(CFLAGS)) -I$(DPI_DIR)
XML_CFLAGS = $(filter-out -DSYNTHESIS -DVIVADO, $(CFLAGS)) $(RTL_PKGS) -I$(DPI_DIR) -DSV_DPI
# RTL Kernel only supports Hardware and Hardware Emulation.
ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu))
@ -192,14 +190,10 @@ ifeq ($(TARGET), hw)
cp $(BUILD_DIR)/_x/logs/link/vivado.log $(BUILD_DIR)/bin/vivado.log
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_full_util_routed.rpt $(BUILD_DIR)/bin/synthesis.log
cp $(BUILD_DIR)/_x/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt $(BUILD_DIR)/bin/timing.log
[ -f "$(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx" ] && cp $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx $(BUILD_DIR)/bin/debug_nets.ltx
endif
hwserver:
debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server &
chipscope:
debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/bin/debug_nets.ltx &
debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/bin/vortex_afu.ltx &
clean:
$(RMDIR) $(BUILD_DIR)

2
hw/syn/yosys/Makefile
View file

@ -29,7 +29,7 @@ DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
# cluster configuration
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1

1
sim/opaesim/Makefile
View file

@ -30,7 +30,6 @@ DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
# AFU parameters
CONFIGS += -DPLATFORM_PROVIDES_LOCAL_MEMORY

1
sim/xrtsim/Makefile
View file

@ -30,7 +30,6 @@ DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
# AFU parameters
ifeq (,$(findstring M_AXI_MEM_NUM_BANKS,$(CONFIGS)))