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minor update

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This commit is contained in:
Blaise Tine 2024-09-20 08:09:46 -07:00
parent 63cce35c1a
commit a61f97f6c6
3 changed files with 12 additions and 12 deletions
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2
hw/rtl/afu/opae/vortex_afu.sv
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@ -79,7 +79,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
localparam COUT_TID_WIDTH = `CLOG2(`VX_MEM_BYTEEN_WIDTH);
localparam COUT_QUEUE_DATAW = COUT_TID_WIDTH + 8;
localparam COUT_QUEUE_SIZE = 64;
localparam COUT_QUEUE_SIZE = 1024;
localparam MMIO_DEV_CAPS = `AFU_IMAGE_MMIO_DEV_CAPS;
localparam MMIO_ISA_CAPS = `AFU_IMAGE_MMIO_ISA_CAPS;

4
hw/rtl/afu/xrt/vortex_afu.vh
View file

@ -15,11 +15,11 @@
`define VORTEX_AFU_VH
`ifndef M_AXI_MEM_NUM_BANKS
`define M_AXI_MEM_NUM_BANKS 4
`define M_AXI_MEM_NUM_BANKS 1
`endif
`ifndef M_AXI_MEM_ADDR_WIDTH
`define M_AXI_MEM_ADDR_WIDTH 30
`define M_AXI_MEM_ADDR_WIDTH 34
`endif
`ifndef M_AXI_MEM_DATA_WIDTH

18
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -100,15 +100,6 @@ module VX_axi_adapter #(
assign req_bank_sel = '0;
end
wire [NUM_BANKS-1:0] axi_write_ready;
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_ready
assign axi_write_ready[i] = (m_axi_awready[i] || m_axi_aw_ack[i])
&& (m_axi_wready[i] || m_axi_w_ack[i]);
end
// request ack
assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel];
wire mem_req_fire = mem_req_valid && mem_req_ready;
// AXi write request synchronization
@ -131,6 +122,15 @@ module VX_axi_adapter #(
end
end
wire [NUM_BANKS-1:0] axi_write_ready;
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_ready
assign axi_write_ready[i] = (m_axi_awready[i] || m_axi_aw_ack[i])
&& (m_axi_wready[i] || m_axi_w_ack[i]);
end
// request ack
assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel];
// AXI write request address channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_addr
assign m_axi_awvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_aw_ack[i];