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https://github.com/vortexgpgpu/vortex.git
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tex_unit address generation complete
This commit is contained in:
Blaise Tine
parent
1431ef9bc0
commit
7ff5c082bc
4 changed files with 100 additions and 80 deletions
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@ -43,52 +43,85 @@ module VX_tex_addr_gen #(
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (lod)
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wire [`FIXED_FRAC-1:0] u[`NUM_THREADS-1:0][1:0];
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wire [`FIXED_FRAC-1:0] v[`NUM_THREADS-1:0][1:0];
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// addressing mode
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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// addressing mode
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wire [31:0] u, v;
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wire [31:0] fu[1:0];
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wire [31:0] fv[1:0];
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assign fu[0] = coord_u[i] - (filter ? (`FIXED_HALF >> log2_width) : 0);
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assign fv[0] = coord_v[i] - (filter ? (`FIXED_HALF >> log2_height) : 0);
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assign fu[1] = coord_u[i] + (filter ? (`FIXED_HALF >> log2_width) : 0);
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assign fv[1] = coord_v[i] + (filter ? (`FIXED_HALF >> log2_height) : 0);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_u (
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) tex_wrap_u0 (
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.wrap_i (wrap_u),
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.coord_i (coord_u[i]),
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.coord_o (u)
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.coord_i (fu[0]),
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.coord_o (u[i][0])
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);
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_v (
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) tex_wrap_v0 (
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.wrap_i (wrap_v),
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.coord_i (coord_v[i]),
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.coord_o (v)
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.coord_i (fv[0]),
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.coord_o (v[i][0])
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);
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// texel addresses generation
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_u1 (
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.wrap_i (wrap_u),
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.coord_i (fu[1]),
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.coord_o (u[i][1])
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);
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wire [31:0] x_offset, y_offset;
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wire [31:0] addr0;
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VX_tex_wrap #(
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.CORE_ID (CORE_ID)
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) tex_wrap_v1 (
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.wrap_i (wrap_v),
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.coord_i (fv[1]),
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.coord_o (v[i][1])
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);
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end
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// addresses generation
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assign x_offset = u >> (5'(`FIXED_FRAC) - log2_width);
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assign y_offset = v >> (5'(`FIXED_FRAC) - log2_height);
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assign addr0 = base_addr + (x_offset + (y_offset << log2_width)) << log2_stride;
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wire [31:0] addr [`NUM_THREADS-1:0][3:0];
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wire [3:0] req_valids = 4'(valid_in);
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wire [3:0][31:0] req_address = {4{addr0}};
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`FIXED_FRAC-1:0] x [1:0];
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wire [`FIXED_FRAC-1:0] y [1:0];
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assign x[0] = u[i][0] >> ((`FIXED_FRAC) - log2_width);
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assign x[1] = u[i][1] >> ((`FIXED_FRAC) - log2_width);
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assign y[0] = v[i][0] >> ((`FIXED_FRAC) - log2_height);
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assign y[1] = v[i][1] >> ((`FIXED_FRAC) - log2_height);
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assign addr [i][0] = base_addr + (x[0] + (y[0] << log2_width)) << log2_stride;
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assign addr [i][1] = base_addr + (x[1] + (y[0] << log2_width)) << log2_stride;
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assign addr [i][2] = base_addr + (x[0] + (y[1] << log2_width)) << log2_stride;
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assign addr [i][3] = base_addr + (x[1] + (y[1] << log2_width)) << log2_stride;
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end
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wire stall_out = mem_req_valid && ~mem_req_ready;
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VX_pipe_register #(
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.DATAW (1 + 4 + 4 * 32 + REQ_TAG_WIDTH),
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.DATAW (1 + 4 + `NUM_THREADS * 4 * 32 + REQ_TAG_WIDTH),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valids, req_address, req_tag}),
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.data_out ({mem_req_valid, mem_req_addr, mem_req_tag})
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.data_in ({valid_in, req_tmask, filter, req_tag, addr}),
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.data_out ({mem_req_valid, mem_req_tmask, mem_req_filter, mem_req_tag, mem_req_addr})
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);
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assign ready_in = ~stall_out;
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@ -6,6 +6,7 @@
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`define FIXED_FRAC 20
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`define FIXED_INT (32 - `FIXED_FRAC)
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`define FIXED_ONE (1 << `FIXED_FRAC)
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`define FIXED_HALF (`FIXED_ONE >> 1)
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`define FIXED_MASK (`FIXED_ONE - 1)
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`define CLAMP(x,lo,hi) ((x < lo) ? lo : ((x > hi) ? hi : x))
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@ -13,8 +14,8 @@
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`define TEX_ADDR_BITS 32
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`define TEX_FORMAT_BITS 3
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`define TEX_WRAP_BITS 2
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`define TEX_WIDTH_BITS 12
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`define TEX_HEIGHT_BITS 12
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`define TEX_WIDTH_BITS 4
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`define TEX_HEIGHT_BITS 4
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`define TEX_STRIDE_BITS 2
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`define TEX_FILTER_BITS 1
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@ -1,35 +1,16 @@
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`include "VX_tex_define.vh"
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/*
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switch(addressing_mode) {
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case undefined: return is_undefined;
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case clamp_to_edge: return intdowni(max(0, min(coord, coorddim - 1)));
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case clamp_to_border: return is_border;
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case repeat:
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tile = intdowni(coord / coorddim);
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return intdowni(coord - (tile * coorddim));
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case mirrored_repeat:
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mirrored_coord = (coord < 0) ? (-coord - 1) : coord;
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tile = intdowni(mirrored_coord / coorddim);
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mirrored_coord = intdowni(mirrored_coord - (tile * coorddim));
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if (tile & 1) {
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mirrored_coord = (coorddim - 1) - mirrored_coord;
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}
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return mirrored_coord;
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}
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*/
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module VX_tex_wrap #(
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parameter CORE_ID = 0
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) (
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input wire [`TEX_WRAP_BITS-1:0] wrap_i,
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input wire [31:0] coord_i,
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input wire [`FIXED_FRAC-1:0] coord_o
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output wire [`FIXED_FRAC-1:0] coord_o
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);
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`UNUSED_PARAM (CORE_ID)
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reg [31:0] coord_r;
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reg [`FIXED_FRAC-1:0] coord_r;
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wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK);
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@ -776,46 +776,51 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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case FMSUB:
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case FMNMADD:
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case FMNMSUB: {
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// multiplicands are infinity and zero, them set FCSR
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if (fpBinIsZero(rsdata[0]) || fpBinIsZero(rsdata[1]) || fpBinIsInf(rsdata[0]) || fpBinIsInf(rsdata[1])) {
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core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
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core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
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}
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if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1]) || fpBinIsNan(rsdata[2])) {
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// if one of op is NaN, if addend is not quiet NaN, them set FCSR
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if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2) | (fpBinIsNan(rsdata[1])==2)) {
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core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
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core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
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}
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rddata = 0x7fc00000; // canonical(quiet) NaN
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// select FP format
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if (core_->get_csr(CSR_FPMODE, t, id_) == 1) {
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// CODE
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} else {
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float rs1 = intregToFloat(rsdata[0]);
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float rs2 = intregToFloat(rsdata[1]);
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float rs3 = intregToFloat(rsdata[2]);
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float fpDest(0.0);
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feclearexcept(FE_ALL_EXCEPT);
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switch (opcode) {
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case FMADD:
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// rd = (rs1*rs2)+rs3
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fpDest = (rs1 * rs2) + rs3; break;
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case FMSUB:
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// rd = (rs1*rs2)-rs3
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fpDest = (rs1 * rs2) - rs3; break;
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case FMNMADD:
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// rd = -(rs1*rs2)+rs3
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fpDest = -1*(rs1 * rs2) - rs3; break;
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case FMNMSUB:
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// rd = -(rs1*rs2)-rs3
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fpDest = -1*(rs1 * rs2) + rs3; break;
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default:
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std::abort();
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break;
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}
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// multiplicands are infinity and zero, them set FCSR
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if (fpBinIsZero(rsdata[0]) || fpBinIsZero(rsdata[1]) || fpBinIsInf(rsdata[0]) || fpBinIsInf(rsdata[1])) {
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core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
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core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
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}
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if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1]) || fpBinIsNan(rsdata[2])) {
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// if one of op is NaN, if addend is not quiet NaN, them set FCSR
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if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2) | (fpBinIsNan(rsdata[1])==2)) {
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core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
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core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
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}
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rddata = 0x7fc00000; // canonical(quiet) NaN
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} else {
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float rs1 = intregToFloat(rsdata[0]);
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float rs2 = intregToFloat(rsdata[1]);
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float rs3 = intregToFloat(rsdata[2]);
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float fpDest(0.0);
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feclearexcept(FE_ALL_EXCEPT);
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switch (opcode) {
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case FMADD:
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// rd = (rs1*rs2)+rs3
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fpDest = (rs1 * rs2) + rs3; break;
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case FMSUB:
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// rd = (rs1*rs2)-rs3
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fpDest = (rs1 * rs2) - rs3; break;
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case FMNMADD:
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// rd = -(rs1*rs2)+rs3
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fpDest = -1*(rs1 * rs2) - rs3; break;
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case FMNMSUB:
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// rd = -(rs1*rs2)-rs3
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fpDest = -1*(rs1 * rs2) + rs3; break;
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default:
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std::abort();
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break;
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}
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// update fcsrs
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update_fcrs(core_, t, id_);
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// update fcsrs
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update_fcrs(core_, t, id_);
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rddata = floatToBin(fpDest);
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rddata = floatToBin(fpDest);
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}
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}
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}
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break;
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