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bug fixes

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This commit is contained in:
tinebp 2025-01-14 02:21:17 -08:00
parent 83ba1cc3dc
commit 87297e0eca
14 changed files with 208 additions and 247 deletions
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3
hw/rtl/VX_platform.vh
View file

@ -177,6 +177,9 @@
`define PRESERVE_NET (* keep = "true" *)
`define BLACKBOX_CELL (* black_box *)
`define STRING
`ifndef SIMULATION
`define ASYNC_BRAM_PATCH
`endif
`else
`define MAX_FANOUT 8
`define FORCE_BRAM(d,w) (d >= 16 || w >= 128 || (d * w) >= 256)

20
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -35,17 +35,21 @@ module VX_afu_wrap #(
input wire s_axi_ctrl_awvalid,
output wire s_axi_ctrl_awready,
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
input wire s_axi_ctrl_wvalid,
output wire s_axi_ctrl_wready,
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
input wire s_axi_ctrl_arvalid,
output wire s_axi_ctrl_arready,
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
output wire s_axi_ctrl_rvalid,
input wire s_axi_ctrl_rready,
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
output wire [1:0] s_axi_ctrl_rresp,
output wire s_axi_ctrl_bvalid,
input wire s_axi_ctrl_bready,
output wire [1:0] s_axi_ctrl_bresp,
@ -69,20 +73,24 @@ module VX_afu_wrap #(
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
@ -217,17 +225,21 @@ module VX_afu_wrap #(
.s_axi_awvalid (s_axi_ctrl_awvalid),
.s_axi_awready (s_axi_ctrl_awready),
.s_axi_awaddr (s_axi_ctrl_awaddr),
.s_axi_wvalid (s_axi_ctrl_wvalid),
.s_axi_wready (s_axi_ctrl_wready),
.s_axi_wdata (s_axi_ctrl_wdata),
.s_axi_wstrb (s_axi_ctrl_wstrb),
.s_axi_arvalid (s_axi_ctrl_arvalid),
.s_axi_arready (s_axi_ctrl_arready),
.s_axi_araddr (s_axi_ctrl_araddr),
.s_axi_rvalid (s_axi_ctrl_rvalid),
.s_axi_rready (s_axi_ctrl_rready),
.s_axi_rdata (s_axi_ctrl_rdata),
.s_axi_rresp (s_axi_ctrl_rresp),
.s_axi_bvalid (s_axi_ctrl_bvalid),
.s_axi_bready (s_axi_ctrl_bready),
.s_axi_bresp (s_axi_ctrl_bresp),
@ -428,16 +440,16 @@ module VX_afu_wrap #(
always @(posedge clk) begin
for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
`TRACE(2, ("%t: AXI Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]))
`TRACE(2, ("%t: AXI Wr Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]))
end
if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin
`TRACE(2, ("%t: AXI Wr Req [%0d]: data=0x%h\n", $time, i, m_axi_mem_wdata_a[i]))
`TRACE(2, ("%t: AXI Wr Req [%0d]: strb=0x%h, data=0x%h\n", $time, i, m_axi_mem_wstrb_a[i], m_axi_mem_wdata_a[i]))
end
if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin
`TRACE(2, ("%t: AXI Rd Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]))
`TRACE(2, ("%t: AXI Rd Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]))
end
if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin
`TRACE(2, ("%t: AXI Rd Rsp [%0d]: data=0x%h, tag=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]))
`TRACE(2, ("%t: AXI Rd Rsp [%0d]: data=0x%h, id=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]))
end
end
end

14
hw/rtl/afu/xrt/vortex_afu.v
View file

@ -40,18 +40,22 @@ module vortex_afu #(
input wire s_axi_ctrl_awvalid,
output wire s_axi_ctrl_awready,
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
input wire s_axi_ctrl_wvalid,
output wire s_axi_ctrl_wready,
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
input wire s_axi_ctrl_arvalid,
input wire s_axi_ctrl_arvalid,
output wire s_axi_ctrl_arready,
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
output wire s_axi_ctrl_rvalid,
input wire s_axi_ctrl_rready,
input wire s_axi_ctrl_rready,
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
output wire [1:0] s_axi_ctrl_rresp,
output wire s_axi_ctrl_bvalid,
output wire s_axi_ctrl_bvalid,
input wire s_axi_ctrl_bready,
output wire [1:0] s_axi_ctrl_bresp,
@ -76,17 +80,21 @@ module vortex_afu #(
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
.s_axi_ctrl_awready (s_axi_ctrl_awready),
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
.s_axi_ctrl_wready (s_axi_ctrl_wready),
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
.s_axi_ctrl_wstrb (s_axi_ctrl_wstrb),
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
.s_axi_ctrl_arready (s_axi_ctrl_arready),
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
.s_axi_ctrl_rready (s_axi_ctrl_rready),
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
.s_axi_ctrl_bready (s_axi_ctrl_bready),
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),

6
hw/rtl/cache/VX_cache_repl.sv vendored
View file

@ -119,6 +119,9 @@ module VX_cache_repl #(
.SIZE (`CS_LINES_PER_BANK),
.WRENW (LRU_WIDTH),
.RDW_MODE ("R"),
`ifdef SIMULATION
.RESET_RAM (1),
`endif
.RADDR_REG (1)
) plru_store (
.clk (clk),
@ -160,6 +163,9 @@ module VX_cache_repl #(
.DATAW (WAY_SEL_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.RDW_MODE ("R"),
`ifdef SIMULATION
.RESET_RAM (1),
`endif
.RADDR_REG (1)
) ctr_store (
.clk (clk),

66
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -23,10 +23,10 @@ module VX_axi_adapter #(
parameter NUM_PORTS_IN = 1,
parameter NUM_BANKS_OUT = 1,
parameter INTERLEAVE = 0,
parameter TAG_BUFFER_SIZE= 32,
parameter TAG_BUFFER_SIZE= 16,
parameter ARBITER = "R",
parameter REQ_OUT_BUF = 1,
parameter RSP_OUT_BUF = 1,
parameter REQ_OUT_BUF = 0,
parameter RSP_OUT_BUF = 0,
parameter DATA_SIZE = DATA_WIDTH/8
) (
input wire clk,
@ -194,27 +194,6 @@ module VX_axi_adapter #(
assign mem_req_ready[0] = arb_ready_in[req_bank_sel[0]][0];
end
// AXi write request synchronization
wire [NUM_BANKS_OUT-1:0] m_axi_awvalid_w, m_axi_wvalid_w;
wire [NUM_BANKS_OUT-1:0] m_axi_awready_w, m_axi_wready_w;
reg [NUM_BANKS_OUT-1:0] m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_write_ready
VX_axi_write_ack axi_write_ack (
.clk (clk),
.reset (reset),
.awvalid(m_axi_awvalid_w[i]),
.awready(m_axi_awready_w[i]),
.wvalid (m_axi_wvalid_w[i]),
.wready (m_axi_wready_w[i]),
.aw_ack (m_axi_aw_ack[i]),
.w_ack (m_axi_w_ack[i]),
.tx_rdy (axi_write_ready[i]),
`UNUSED_PIN (tx_ack)
);
end
// AXI request handling
for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_write_req
@ -259,14 +238,33 @@ module VX_axi_adapter #(
.sel_out (arb_sel_out)
);
wire m_axi_arready_w;
// AXi write request handshake
assign arb_ready_out = axi_write_ready[i] || m_axi_arready_w;
wire m_axi_arvalid_w, m_axi_arready_w;
wire m_axi_awvalid_w, m_axi_awready_w;
wire m_axi_wvalid_w, m_axi_wready_w;
reg m_axi_aw_ack, m_axi_w_ack, axi_write_ready;
VX_axi_write_ack axi_write_ack (
.clk (clk),
.reset (reset),
.awvalid(m_axi_awvalid_w),
.awready(m_axi_awready_w),
.wvalid (m_axi_wvalid_w),
.wready (m_axi_wready_w),
.aw_ack (m_axi_aw_ack),
.w_ack (m_axi_w_ack),
.tx_rdy (axi_write_ready),
`UNUSED_PIN (tx_ack)
);
assign m_axi_arvalid_w = arb_valid_out && ~arb_rw_out;
assign m_axi_awvalid_w = arb_valid_out && arb_rw_out && ~m_axi_aw_ack;
assign m_axi_wvalid_w = arb_valid_out && arb_rw_out && ~m_axi_w_ack;
assign arb_ready_out = axi_write_ready || m_axi_arready_w;
// AXI write address channel
assign m_axi_awvalid_w[i] = arb_valid_out && arb_rw_out && ~m_axi_aw_ack[i];
VX_elastic_buffer #(
.DATAW (BANK_ADDR_WIDTH + WRITE_TAG_WIDTH),
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
@ -275,8 +273,8 @@ module VX_axi_adapter #(
) aw_buf (
.clk (clk),
.reset (reset),
.valid_in (m_axi_awvalid_w[i]),
.ready_in (m_axi_awready_w[i]),
.valid_in (m_axi_awvalid_w),
.ready_in (m_axi_awready_w),
.data_in ({arb_addr_out, WRITE_TAG_WIDTH'(arb_tag_out)}),
.data_out ({buf_addr_w_out, buf_tag_w_out}),
.valid_out (m_axi_awvalid[i]),
@ -296,8 +294,6 @@ module VX_axi_adapter #(
// AXI write data channel
assign m_axi_wvalid_w[i] = arb_valid_out && arb_rw_out && ~m_axi_w_ack[i];
VX_elastic_buffer #(
.DATAW (DATA_SIZE + DATA_WIDTH),
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
@ -306,8 +302,8 @@ module VX_axi_adapter #(
) w_buf (
.clk (clk),
.reset (reset),
.valid_in (m_axi_wvalid_w[i]),
.ready_in (m_axi_wready_w[i]),
.valid_in (m_axi_wvalid_w),
.ready_in (m_axi_wready_w),
.data_in ({arb_byteen_out, arb_data_out}),
.data_out ({m_axi_wstrb[i], m_axi_wdata[i]}),
.valid_out (m_axi_wvalid[i]),
@ -333,7 +329,7 @@ module VX_axi_adapter #(
) ar_buf (
.clk (clk),
.reset (reset),
.valid_in (arb_valid_out && ~arb_rw_out),
.valid_in (m_axi_arvalid_w),
.ready_in (m_axi_arready_w),
.data_in ({arb_addr_out, arb_tag_r_out}),
.data_out ({buf_addr_r_out, buf_tag_r_out}),

32
hw/rtl/libs/VX_axi_write_ack.sv
View file

@ -26,35 +26,35 @@ module VX_axi_write_ack (
output wire tx_ack,
output wire tx_rdy
);
reg awfired;
reg wfired;
reg aw_fired;
reg w_fired;
wire awfire = awvalid && awready;
wire wfire = wvalid && wready;
wire aw_fire = awvalid && awready;
wire w_fire = wvalid && wready;
always @(posedge clk) begin
if (reset) begin
awfired <= 0;
wfired <= 0;
aw_fired <= 0;
w_fired <= 0;
end else begin
if (awfire) begin
awfired <= 1;
if (aw_fire) begin
aw_fired <= 1;
end
if (wfire) begin
wfired <= 1;
if (w_fire) begin
w_fired <= 1;
end
if (tx_ack) begin
awfired <= 0;
wfired <= 0;
aw_fired <= 0;
w_fired <= 0;
end
end
end
assign aw_ack = awfired;
assign w_ack = wfired;
assign aw_ack = aw_fired;
assign w_ack = w_fired;
assign tx_ack = (awfire || awfired) && (wfire || wfired);
assign tx_rdy = (awready || awfired) && (wready || wfired);
assign tx_ack = (aw_fire || aw_fired) && (w_fire || w_fired);
assign tx_rdy = (awready || aw_fired) && (wready || w_fired);
endmodule
`TRACING_ON

112
hw/rtl/libs/VX_dp_ram.sv
View file

@ -13,10 +13,6 @@
`include "VX_platform.vh"
`ifdef VIVADO
`define ASYNC_BRAM_PATCH
`endif
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin : g_init \
if (INIT_FILE != "") begin : g_file \
@ -30,18 +26,38 @@
end \
end
`define RAM_WRITE_ALL if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
ram[waddr] <= wdata; \
end
`ifdef QUARTUS
`define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i] <= wdata[i * WSELW +: WSELW]; \
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i] <= wdata[i * WSELW +: WSELW]; \
end \
end \
end
`else
`define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
end \
end \
end
`endif
@ -92,9 +108,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [ADDRW-1:0] raddr_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
raddr_r <= raddr;
end
@ -105,9 +119,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [ADDRW-1:0] raddr_r;
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
raddr_r <= raddr;
end
@ -120,9 +132,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
rdata_r <= ram[raddr];
end
@ -133,9 +143,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
rdata_r <= ram[raddr];
end
@ -150,9 +158,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [ADDRW-1:0] raddr_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
raddr_r <= raddr;
end
@ -163,9 +169,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [ADDRW-1:0] raddr_r;
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
raddr_r <= raddr;
end
@ -178,9 +182,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
rdata_r <= ram[raddr];
end
@ -191,9 +193,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
rdata_r <= ram[raddr];
end
@ -235,18 +235,14 @@ module VX_dp_ram #(
`RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[raddr];
end else begin : g_no_wren
`RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[raddr];
end
@ -255,18 +251,14 @@ module VX_dp_ram #(
`NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[raddr];
end else begin : g_no_wren
`NO_RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[raddr];
end
@ -278,18 +270,14 @@ module VX_dp_ram #(
`RW_RAM_CHECK `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[raddr];
end else begin : g_no_wren
`RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[raddr];
end
@ -298,18 +286,14 @@ module VX_dp_ram #(
`NO_RW_RAM_CHECK `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[raddr];
end else begin : g_no_wren
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[raddr];
end
@ -322,17 +306,7 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
always @(posedge clk) begin
if (RESET_RAM && reset) begin
for (integer i = 0; i < SIZE; ++i) begin
ram[i] <= DATAW'(INIT_VALUE);
end
end else if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i]) begin
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
`RAM_WRITE_WREN
end
if (OUT_REG) begin : g_sync

132
hw/rtl/libs/VX_sp_ram.sv
View file

@ -13,10 +13,6 @@
`include "VX_platform.vh"
`ifdef VIVADO
`define ASYNC_BRAM_PATCH
`endif
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin : g_init \
if (INIT_FILE != "") begin : g_file \
@ -30,18 +26,38 @@
end \
end
`define RAM_WRITE_ALL if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
ram[addr] <= wdata; \
end
`ifdef QUARTUS
`define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[addr][i] <= wdata[i * WSELW +: WSELW]; \
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[addr][i] <= wdata[i * WSELW +: WSELW]; \
end \
end \
end
`else
`define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1];
`define RAM_WRITE_WREN for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
`define RAM_WRITE_WREN if (RESET_RAM && reset) begin \
for (integer i = 0; i < SIZE; ++i) begin \
ram[i] <= DATAW'(INIT_VALUE); \
end \
end else if (write) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
end \
end \
end
`endif
@ -91,9 +107,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [ADDRW-1:0] addr_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
addr_r <= addr;
end
@ -104,9 +118,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
if (write) begin
rdata_r <= wdata;
@ -123,9 +135,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
rdata_r <= ram[addr];
end
@ -136,9 +146,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
rdata_r <= ram[addr];
end
@ -151,9 +159,8 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end else if (read) begin
`RAM_WRITE_WREN
else if (read) begin
rdata_r <= ram[addr];
end
end
@ -163,9 +170,8 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end else if (read) begin
`RAM_WRITE_ALL
else if (read) begin
rdata_r <= ram[addr];
end
end
@ -179,9 +185,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [ADDRW-1:0] addr_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
addr_r <= addr;
end
@ -192,9 +196,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
if (write) begin
rdata_r <= wdata;
@ -211,9 +213,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
if (read) begin
rdata_r <= ram[addr];
end
@ -224,9 +224,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
if (read) begin
rdata_r <= ram[addr];
end
@ -239,9 +237,8 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end else if (read) begin
`RAM_WRITE_WREN
else if (read) begin
rdata_r <= ram[addr];
end
end
@ -251,9 +248,8 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end else if (read) begin
`RAM_WRITE_ALL
else if (read) begin
rdata_r <= ram[addr];
end
end
@ -294,18 +290,14 @@ module VX_sp_ram #(
`RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[addr];
end else begin : g_no_wren
`RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[addr];
end
@ -314,18 +306,14 @@ module VX_sp_ram #(
`NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[addr];
end else begin : g_no_wren
`NO_RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[addr];
end
@ -337,18 +325,14 @@ module VX_sp_ram #(
`RW_RAM_CHECK `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[addr];
end else begin : g_no_wren
`RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[addr];
end
@ -357,18 +341,14 @@ module VX_sp_ram #(
`NO_RW_RAM_CHECK `RAM_ARRAY_WREN
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
`RAM_WRITE_WREN
end
`RAM_WRITE_WREN
end
assign rdata = ram[addr];
end else begin : g_no_wren
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[addr] <= wdata;
end
`RAM_WRITE_ALL
end
assign rdata = ram[addr];
end
@ -381,17 +361,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
always @(posedge clk) begin
if (RESET_RAM && reset) begin
for (integer i = 0; i < SIZE; ++i) begin
ram[i] <= DATAW'(INIT_VALUE);
end
end else if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i]) begin
ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
end
`RAM_WRITE_WREN
end
if (OUT_REG) begin : g_sync

8
hw/syn/xilinx/xrt/Makefile
View file

@ -116,12 +116,12 @@ endif
# Debugging
ifdef DEBUG
VPP_FLAGS += -g --optimize 0 --debug.protocol all
ifneq ($(TARGET), hw)
VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
CFLAGS += -DDEBUG_LEVEL=$(DEBUG) $(DBG_TRACE_FLAGS)
else
ifeq ($(TARGET), hw)
VPP_FLAGS += --debug.chipscope vortex_afu_1
CFLAGS += -DNDEBUG -DCHIPSCOPE $(DBG_SCOPE_FLAGS)
else
VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
CFLAGS += -DDEBUG_LEVEL=$(DEBUG) $(DBG_TRACE_FLAGS)
endif
else
VPP_FLAGS += --optimize 3

2
runtime/xrt/vortex.cpp
View file

@ -19,7 +19,7 @@
// XRT includes
#ifdef XRTSIM
#include <xrt.h>
#include <xrt_c.h>
#else
#include "experimental/xrt_bo.h"
#include "experimental/xrt_device.h"

2
sim/xrtsim/Makefile
View file

@ -50,7 +50,7 @@ DBG_FLAGS += -DDEBUG_LEVEL=$(DEBUG) -DVCD_OUTPUT $(DBG_TRACE_FLAGS)
SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
SRCS += $(SRC_DIR)/xrt.cpp $(SRC_DIR)/xrt_sim.cpp
SRCS += $(SRC_DIR)/xrt_c.cpp $(SRC_DIR)/xrt_sim.cpp
RTL_PKGS += $(RTL_DIR)/VX_gpu_pkg.sv $(RTL_DIR)/fpu/VX_fpu_pkg.sv

2
sim/xrtsim/xrt.cpp → sim/xrtsim/xrt_c.cpp
View file

@ -19,7 +19,7 @@
#include <cstring>
#include <unistd.h>
#include <assert.h>
#include "xrt.h"
#include "xrt_c.h"
#include "xrt_sim.h"
#include <VX_config.h>
#include <util.h>

0
sim/xrtsim/xrt.h → sim/xrtsim/xrt_c.h
View file

56
sim/xrtsim/xrt_sim.cpp
View file

@ -341,7 +341,7 @@ private:
for (int b = 0; b < PLATFORM_MEMORY_BANKS; ++b) {
*m_axi_mem_[b].arready = 1;
*m_axi_mem_[b].awready = 1;
*m_axi_mem_[b].wready = 1;
*m_axi_mem_[b].wready = 0;
}
}
@ -426,10 +426,6 @@ private:
// write response
*m_axi_mem_[b].bvalid = 0;
// states
m_axi_states_[b].write_req_addr_ack = false;
m_axi_states_[b].write_req_data_ack = false;
}
}
@ -483,6 +479,7 @@ private:
// handle read requests
if (*m_axi_mem_[b].arvalid && *m_axi_mem_[b].arready) {
// create read request
auto mem_req = new mem_req_t();
mem_req->tag = *m_axi_mem_[b].arid;
mem_req->addr = uint64_t(*m_axi_mem_[b].araddr);
@ -501,32 +498,21 @@ private:
dram_queues_[b].push(mem_req);
}
// handle write address requests
if (*m_axi_mem_[b].awvalid && *m_axi_mem_[b].awready && !m_axi_states_[b].write_req_addr_ack) {
m_axi_states_[b].write_req_addr = *m_axi_mem_[b].awaddr;
m_axi_states_[b].write_req_tag = *m_axi_mem_[b].awid;
m_axi_states_[b].write_req_addr_ack = true;
}
// handle write data requests
if (*m_axi_mem_[b].wvalid && *m_axi_mem_[b].wready && !m_axi_states_[b].write_req_data_ack) {
m_axi_states_[b].write_req_byteen = *m_axi_mem_[b].wstrb;
auto data = (const uint8_t*)m_axi_mem_[b].wdata->data();
for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; ++i) {
m_axi_states_[b].write_req_data[i] = data[i];
}
m_axi_states_[b].write_req_data_ack = true;
}
if (*m_axi_mem_[b].wvalid && *m_axi_mem_[b].wready) {
// ensure write address channel is not active
assert(!*m_axi_mem_[b].awvalid);
// handle write requests
if (m_axi_states_[b].write_req_addr_ack && m_axi_states_[b].write_req_data_ack) {
auto byteen = m_axi_states_[b].write_req_byteen;
// capture write data
auto byte_addr = m_axi_states_[b].write_req_addr;
auto data = (const uint8_t*)m_axi_mem_[b].wdata->data();
auto byteen = *m_axi_mem_[b].wstrb;
for (int i = 0; i < PLATFORM_MEMORY_DATA_SIZE; ++i) {
if ((byteen >> i) & 0x1) {
(*ram_)[byte_addr + i] = m_axi_states_[b].write_req_data[i];
(*ram_)[byte_addr + i] = data[i];
}
}
// create write request
auto mem_req = new mem_req_t();
mem_req->tag = m_axi_states_[b].write_req_tag;
mem_req->addr = byte_addr;
@ -536,29 +522,35 @@ private:
/*printf("%0ld: [sim] axi-mem-write[%d]: addr=0x%lx, byteen=0x%lx, tag=0x%x, data=0x", timestamp, b, mem_req->addr, byteen, mem_req->tag);
for (int i = PLATFORM_MEMORY_DATA_SIZE-1; i >= 0; --i) {
printf("%02x", m_axi_states_[b].write_req_data[i]]);
printf("%02x", data[i]]);
}
printf("\n");*/
// send dram request
dram_queues_[b].push(mem_req);
// clear acks
m_axi_states_[b].write_req_addr_ack = false;
m_axi_states_[b].write_req_data_ack = false;
// reset write request handshake
*m_axi_mem_[b].wready = 0;
*m_axi_mem_[b].awready = 1;
}
// handle write address requests
if (*m_axi_mem_[b].awvalid && *m_axi_mem_[b].awready) {
// capture write request address
m_axi_states_[b].write_req_addr = *m_axi_mem_[b].awaddr;
m_axi_states_[b].write_req_tag = *m_axi_mem_[b].awid;
// enable write data handshake
*m_axi_mem_[b].awready = 0;
*m_axi_mem_[b].wready = 1;
}
}
}
typedef struct {
std::array<uint8_t, PLATFORM_MEMORY_DATA_SIZE> write_req_data;
uint64_t write_req_byteen;
uint64_t write_req_addr;
uint32_t write_req_tag;
bool read_rsp_ready;
bool write_rsp_ready;
bool write_req_addr_ack;
bool write_req_data_ack;
} m_axi_state_t;
typedef struct {