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gfx support update

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This commit is contained in:
Blaise Tine 2022-02-09 06:09:30 -05:00
parent 8a3b9546a9
commit 87bd74b0bb
11 changed files with 321 additions and 19 deletions
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2
hw/rtl/VX_define.vh
View file

@ -196,6 +196,8 @@
`define INST_GPU_BAR 4'h4
`define INST_GPU_PRED 4'h5
`define INST_GPU_TEX 4'h6
`define INST_GPU_RASTER 4'h7
`define INST_GPU_ROP 4'h8
`define INST_GPU_BITS 4
///////////////////////////////////////////////////////////////////////////////

149
hw/rtl/VX_gpu_unit.sv
View file

@ -105,7 +105,154 @@ module VX_gpu_unit #(
// pack warp ctl result
assign warp_ctl_data = {tmc, wspawn, split, barrier};
// texture
`ifdef EXT_RASTER_ENABLE
`IGNORE_WARNINGS_BEGIN
VX_raster_req_if raster_req_if();
VX_raster_rsp_if raster_rsp_if();
VX_raster_csr_if raster_csr_if();
VX_perf_raster_if perf_raster_if();
VX_dcache_req_if rcache_req_if();
VX_dcache_rsp_if rcache_rsp_if();
wire is_raster = (gpu_req_if.op_type == `INST_GPU_RASTER);
assign raster_req_if.valid = gpu_req_if.valid && is_tex;
assign raster_req_if.uuid = gpu_req_if.uuid;
assign raster_req_if.wid = gpu_req_if.wid;
assign raster_req_if.tmask = gpu_req_if.tmask;
assign raster_req_if.PC = gpu_req_if.PC;
assign raster_req_if.rd = gpu_req_if.rd;
assign raster_req_if.wb = gpu_req_if.wb;
`UNUSED_VAR (raster_req_if.ready) // TODO: remove
// TODO: remove
`UNUSED_VAR (raster_rsp_if.valid)
`UNUSED_VAR (raster_rsp_if.uuid)
`UNUSED_VAR (raster_rsp_if.wid)
`UNUSED_VAR (raster_rsp_if.tmask)
`UNUSED_VAR (raster_rsp_if.PC)
`UNUSED_VAR (raster_rsp_if.rd)
`UNUSED_VAR (raster_rsp_if.wb)
`UNUSED_VAR (raster_rsp_if.rem)
assign raster_rsp_if.ready = 0;
// TODO: remove
assign raster_csr_if.write_enable = 0;
assign raster_csr_if.write_addr = 0;
assign raster_csr_if.write_data = 0;
assign raster_csr_if.write_uuid = 0;
// TODO: remove
`UNUSED_VAR (perf_raster_if.mem_reads);
`UNUSED_VAR (perf_raster_if.mem_latency);
// TODO: remove
`UNUSED_VAR (rcache_req_if.valid);
`UNUSED_VAR (rcache_req_if.rw);
`UNUSED_VAR (rcache_req_if.byteen);
`UNUSED_VAR (rcache_req_if.addr);
`UNUSED_VAR (rcache_req_if.data);
`UNUSED_VAR (rcache_req_if.tag);
assign rcache_req_if.ready = 0;
// TODO: remove
assign rcache_rsp_if.valid = 0;
assign rcache_rsp_if.tmask = 0;
assign rcache_rsp_if.data = 0;
assign rcache_rsp_if.tag = 0;
`UNUSED_VAR (rcache_rsp_if.ready);
VX_raster_unit #(
.CORE_ID (CORE_ID),
.NUM_SLICES (1)
) raster_unit (
.clk (clk),
.reset (reset),
`ifdef PERF_ENABLE
.perf_raster_if(perf_raster_if),
`endif
.raster_req_if (raster_req_if),
.raster_csr_if (raster_csr_if),
.raster_rsp_if (raster_rsp_if),
.cache_req_if (rcache_req_if),
.cache_rsp_if (rcache_rsp_if)
);
`IGNORE_WARNINGS_END
`endif
`ifdef EXT_ROP_ENABLE
`IGNORE_WARNINGS_BEGIN
VX_rop_req_if rop_req_if();
VX_rop_csr_if rop_csr_if();
VX_perf_rop_if perf_rop_if();
VX_dcache_req_if ccache_req_if();
VX_dcache_rsp_if ccache_rsp_if();
wire is_rop = (gpu_req_if.op_type == `INST_GPU_ROP);
assign rop_req_if.valid = gpu_req_if.valid && is_rop;
assign rop_req_if.uuid = gpu_req_if.uuid;
assign rop_req_if.wid = gpu_req_if.wid;
assign rop_req_if.tmask = gpu_req_if.tmask;
assign rop_req_if.PC = gpu_req_if.PC;
assign rop_req_if.rd = gpu_req_if.rd;
assign rop_req_if.wb = gpu_req_if.wb;
assign rop_req_if.x = 0; // TODO: remove
assign rop_req_if.y = 0; // TODO: remove
assign rop_req_if.color = 0; // TODO: remove
`UNUSED_VAR (rop_req_if.ready) // TODO: remove
// TODO: remove
assign rop_csr_if.write_enable = 0;
assign rop_csr_if.write_addr = 0;
assign rop_csr_if.write_data = 0;
assign rop_csr_if.write_uuid = 0;
// TODO: remove
`UNUSED_VAR (perf_rop_if.mem_reads);
`UNUSED_VAR (perf_rop_if.mem_writes);
`UNUSED_VAR (perf_rop_if.mem_latency);
// TODO: remove
`UNUSED_VAR (ccache_req_if.valid);
`UNUSED_VAR (ccache_req_if.rw);
`UNUSED_VAR (ccache_req_if.byteen);
`UNUSED_VAR (ccache_req_if.addr);
`UNUSED_VAR (ccache_req_if.data);
`UNUSED_VAR (ccache_req_if.tag);
assign ccache_req_if.ready = 0;
// TODO: remove
assign ccache_rsp_if.valid = 0;
assign ccache_rsp_if.tmask = 0;
assign ccache_rsp_if.data = 0;
assign ccache_rsp_if.tag = 0;
`UNUSED_VAR (ccache_rsp_if.ready);
VX_rop_unit #(
.CORE_ID (CORE_ID),
.NUM_SLICES (`NUM_THREADS)
) rop_unit (
.clk (clk),
.reset (reset),
`ifdef PERF_ENABLE
.perf_rop_if (perf_rop_if),
`endif
.rop_req_if (rop_req_if),
.rop_csr_if (rop_csr_if),
.cache_req_if (ccache_req_if),
.cache_rsp_if (ccache_rsp_if)
);
`IGNORE_WARNINGS_END
`endif
`ifdef EXT_TEX_ENABLE

23
hw/rtl/interfaces/VX_perf_raster_if.sv Normal file
View file

@ -0,0 +1,23 @@
`ifndef VX_PERF_RASTER_IF
`define VX_PERF_RASTER_IF
`include "VX_define.vh"
interface VX_perf_raster_if ();
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output mem_reads,
output mem_latency
);
modport slave (
input mem_reads,
input mem_latency
);
endinterface
`endif

26
hw/rtl/interfaces/VX_perf_rop_if.sv Normal file
View file

@ -0,0 +1,26 @@
`ifndef VX_PERF_ROP_IF
`define VX_PERF_ROP_IF
`include "VX_define.vh"
interface VX_perf_rop_if ();
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_writes;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output mem_reads,
output mem_writes,
output mem_latency
);
modport slave (
input mem_reads,
input mem_writes,
input mem_latency
);
endinterface
`endif

14
hw/rtl/raster_unit/VX_raster_types.vh
View file

@ -6,12 +6,14 @@
package raster_types;
typedef struct packed {
logic [(`TEX_LOD_MAX+1)-1:0][`TEX_MIPOFF_BITS-1:0] mipoff;
logic [1:0][`TEX_LOD_BITS-1:0] logdims;
logic [1:0][`TEX_WRAP_BITS-1:0] wraps;
logic [`TEX_ADDR_BITS-1:0] baddr;
logic [`TEX_FORMAT_BITS-1:0] format;
logic [`TEX_FILTER_BITS-1:0] filter;
logic [31:0] pidx_addr;
logic [31:0] pidx_size;
logic [31:0] pbuf_addr;
logic [31:0] pbuf_size;
logic [15:0] tile_x;
logic [15:0] tile_y;
logic [15:0] tile_width;
logic [15:0] tile_height;
} raster_csrs_t;
endpackage

60
hw/rtl/raster_unit/VX_raster_unit.sv
View file

@ -1,7 +1,8 @@
`include "VX_raster_define.vh"
module VX_raster_unit #(
parameter CORE_ID = 0
parameter CORE_ID = 0,
parameter NUM_SLICES = 1
// TODO
) (
input wire clk,
@ -9,12 +10,12 @@ module VX_raster_unit #(
// PERF
`ifdef PERF_ENABLE
VX_perf_tex_if.master perf_raster_if,
VX_perf_raster_if.master perf_raster_if,
`endif
// Memory interface
VX_dcache_req_if.master mem_req_if,
VX_dcache_rsp_if.slave mem_rsp_if,
VX_dcache_req_if.master cache_req_if,
VX_dcache_rsp_if.slave cache_rsp_if,
// Inputs
VX_raster_csr_if.slave raster_csr_if,
@ -24,6 +25,55 @@ module VX_raster_unit #(
VX_raster_rsp_if.master raster_rsp_if
);
// TODO
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
// TODO: remove
`UNUSED_VAR (raster_req_if.valid)
`UNUSED_VAR (raster_req_if.uuid)
`UNUSED_VAR (raster_req_if.wid)
`UNUSED_VAR (raster_req_if.tmask)
`UNUSED_VAR (raster_req_if.PC)
`UNUSED_VAR (raster_req_if.rd)
`UNUSED_VAR (raster_req_if.wb)
`UNUSED_VAR (raster_req_if.tmask)
assign raster_req_if.ready = 0;
// TODO: remove
assign raster_rsp_if.valid = 0;
assign raster_rsp_if.uuid = 0;
assign raster_rsp_if.wid = 0;
assign raster_rsp_if.tmask = 0;
assign raster_rsp_if.PC = 0;
assign raster_rsp_if.rd = 0;
assign raster_rsp_if.wb = 0;
assign raster_rsp_if.rem = 0;
`UNUSED_VAR (raster_rsp_if.ready)
// TODO: remove
`UNUSED_VAR (raster_csr_if.write_enable);
`UNUSED_VAR (raster_csr_if.write_addr);
`UNUSED_VAR (raster_csr_if.write_data);
`UNUSED_VAR (raster_csr_if.write_uuid);
// TODO: remove
assign perf_raster_if.mem_reads = 0;
assign perf_raster_if.mem_latency = 0;
// TODO: remove
assign cache_req_if.valid = 0;
assign cache_req_if.rw = 0;
assign cache_req_if.byteen = 0;
assign cache_req_if.addr = 0;
assign cache_req_if.data = 0;
assign cache_req_if.tag = 0;
`UNUSED_VAR (cache_req_if.ready)
// TODO: remove
`UNUSED_VAR (cache_rsp_if.valid)
`UNUSED_VAR (cache_rsp_if.tmask)
`UNUSED_VAR (cache_rsp_if.data)
`UNUSED_VAR (cache_rsp_if.tag)
assign cache_rsp_if.ready = 0;
endmodule

2
hw/rtl/rop_unit/VX_rop_types.vh
View file

@ -11,7 +11,7 @@ typedef struct packed {
logic [`ROP_BLEND_FACTOR_BITS-1:0] blend_src_a;
logic [`ROP_BLEND_FACTOR_BITS-1:0] blend_dst_a;
logic [31:0] blend_const;
logic [`TEX_LOGIC_OP_BITS-1:0] logic_op;
logic [`ROP_LOGIC_OP_BITS-1:0] logic_op;
} rop_csrs_t;
endpackage

49
hw/rtl/rop_unit/VX_rop_unit.sv
View file

@ -1,14 +1,15 @@
`include "VX_rop_define.vh"
module VX_rop_unit #(
parameter CORE_ID = 0
parameter CORE_ID = 0,
parameter NUM_SLICES = 1
) (
input wire clk,
input wire reset,
// PERF
`ifdef PERF_ENABLE
VX_perf_tex_if.master perf_rop_if,
VX_perf_rop_if.master perf_rop_if,
`endif
// Memory interface
@ -20,6 +21,48 @@ module VX_rop_unit #(
VX_rop_req_if.slave rop_req_if
);
// TODO
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
// TODO: remove
`UNUSED_VAR (rop_req_if.valid)
`UNUSED_VAR (rop_req_if.uuid)
`UNUSED_VAR (rop_req_if.wid)
`UNUSED_VAR (rop_req_if.tmask)
`UNUSED_VAR (rop_req_if.PC)
`UNUSED_VAR (rop_req_if.rd)
`UNUSED_VAR (rop_req_if.wb)
`UNUSED_VAR (rop_req_if.tmask)
`UNUSED_VAR (rop_req_if.x)
`UNUSED_VAR (rop_req_if.y)
`UNUSED_VAR (rop_req_if.color)
assign rop_req_if.ready = 0;
// TODO: remove
`UNUSED_VAR (rop_csr_if.write_enable);
`UNUSED_VAR (rop_csr_if.write_addr);
`UNUSED_VAR (rop_csr_if.write_data);
`UNUSED_VAR (rop_csr_if.write_uuid);
// TODO: remove
assign perf_rop_if.mem_reads = 0;
assign perf_rop_if.mem_writes = 0;
assign perf_rop_if.mem_latency = 0;
// TODO: remove
assign cache_req_if.valid = 0;
assign cache_req_if.rw = 0;
assign cache_req_if.byteen = 0;
assign cache_req_if.addr = 0;
assign cache_req_if.data = 0;
assign cache_req_if.tag = 0;
`UNUSED_VAR (cache_req_if.ready)
// TODO: remove
`UNUSED_VAR (cache_rsp_if.valid)
`UNUSED_VAR (cache_rsp_if.tmask)
`UNUSED_VAR (cache_rsp_if.data)
`UNUSED_VAR (cache_rsp_if.tag)
assign cache_rsp_if.ready = 0;
endmodule

5
hw/syn/opae/Makefile
View file

@ -33,7 +33,10 @@ CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=1 -DICACHE_
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/afu $(FPU_INCLUDE) $(TEX_INCLUDE)
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/afu $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
CFLAGS += $(RTL_INCLUDE)

5
sim/rtlsim/Makefile
View file

@ -29,7 +29,10 @@ DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) $(TEX_INCLUDE)
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp
SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp

5
sim/vlsim/Makefile
View file

@ -34,7 +34,10 @@ SRCS += fpga.cpp opae_sim.cpp
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE)
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
RTL_INCLUDE += -I$(RTL_DIR)/afu -I$(RTL_DIR)/afu/ccip
TOP = vortex_afu_shim