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revert xilinx's asynchronous bram workaround

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This commit is contained in:
Blaise Tine 2024-10-24 01:44:55 -07:00
parent 22ade31fd5
commit 8b172d07ec
13 changed files with 82 additions and 62 deletions
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6
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -154,7 +154,7 @@ module VX_cache_bank #(
wire [`CS_WAY_SEL_WIDTH-1:0] way_idx_st0, way_idx_st1;
wire [`CS_LINE_ADDR_WIDTH-1:0] addr_sel, addr_st0, addr_st1;
wire [`CS_LINE_SEL_BITS-1:0] line_idx_sel, line_idx_st0, line_idx_st1;
wire [`CS_LINE_SEL_BITS-1:0] line_idx_st0, line_idx_st1;
wire [`CS_TAG_SEL_BITS-1:0] line_tag_st0, line_tag_st1;
wire [`CS_TAG_SEL_BITS-1:0] evict_tag_st0, evict_tag_st1;
wire rw_sel, rw_st0, rw_st1;
@ -332,7 +332,6 @@ module VX_cache_bank #(
wire do_read_st1 = valid_st1 && is_read_st1;
wire do_write_st1 = valid_st1 && is_write_st1;
assign line_idx_sel = addr_sel[`CS_LINE_SEL_BITS-1:0];
assign line_idx_st0 = addr_st0[`CS_LINE_SEL_BITS-1:0];
assign line_tag_st0 = `CS_LINE_ADDR_TAG(addr_st0);
@ -358,7 +357,6 @@ module VX_cache_bank #(
.hit_line (line_idx_st1),
.hit_way (way_idx_st1),
.repl_valid (do_fill_st0 && ~pipe_stall),
.repl_line_n(line_idx_sel),
.repl_line (line_idx_st0),
.repl_way (victim_way_st0)
);
@ -375,14 +373,12 @@ module VX_cache_bank #(
) cache_tags (
.clk (clk),
.reset (reset),
.stall (pipe_stall),
// inputs
.init (do_init_st0),
.flush (do_flush_st0 && ~pipe_stall),
.fill (do_fill_st0 && ~pipe_stall),
.read (do_read_st0 && ~pipe_stall),
.write (do_write_st0 && ~pipe_stall),
.line_idx_n (line_idx_sel),
.line_idx (line_idx_st0),
.line_tag (line_tag_st0),
.evict_way (evict_way_st0),

9
hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -82,7 +82,8 @@ module VX_cache_data #(
.DATAW (LINE_SIZE * NUM_WAYS),
.WRENW (LINE_SIZE * NUM_WAYS),
.SIZE (`CS_LINES_PER_BANK),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) byteen_store (
.clk (clk),
.reset (reset),
@ -129,7 +130,8 @@ module VX_cache_data #(
.DATAW (NUM_WAYS * `CS_LINE_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.WRENW (NUM_WAYS * LINE_SIZE),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) data_store (
.clk (clk),
.reset (reset),
@ -153,7 +155,8 @@ module VX_cache_data #(
VX_sp_ram #(
.DATAW (`CS_LINE_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) data_store (
.clk (clk),
.reset (reset),

4
hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -221,7 +221,7 @@ module VX_cache_mshr #(
VX_dp_ram #(
.DATAW (DATA_WIDTH),
.SIZE (MSHR_SIZE),
.OUT_REG (1)
.RDW_MODE ("R")
) mshr_store (
.clk (clk),
.reset (reset),
@ -230,7 +230,7 @@ module VX_cache_mshr #(
.wren (1'b1),
.waddr (allocate_id_r),
.wdata (allocate_data),
.raddr (dequeue_id_n),
.raddr (dequeue_id_r),
.rdata (dequeue_data)
);

30
hw/rtl/cache/VX_cache_repl.sv vendored
View file

@ -99,7 +99,6 @@ module VX_cache_repl #(
input wire [`CS_LINE_SEL_BITS-1:0] hit_line,
input wire [`CS_WAY_SEL_WIDTH-1:0] hit_way,
input wire repl_valid,
input wire [`CS_LINE_SEL_BITS-1:0] repl_line_n,
input wire [`CS_LINE_SEL_BITS-1:0] repl_line,
output wire [`CS_WAY_SEL_WIDTH-1:0] repl_way
);
@ -110,26 +109,24 @@ module VX_cache_repl #(
if (REPL_POLICY == `CS_REPL_PLRU) begin : g_plru
// Pseudo Least Recently Used replacement policy
localparam LRU_WIDTH = `UP(NUM_WAYS-1);
`UNUSED_VAR (repl_valid)
`UNUSED_VAR (repl_line)
wire [LRU_WIDTH-1:0] plru_rdata;
wire [LRU_WIDTH-1:0] plru_wdata;
wire [LRU_WIDTH-1:0] plru_wmask;
VX_dp_ram #(
.DATAW (LRU_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.WRENW (LRU_WIDTH),
.OUT_REG (1)
.DATAW (LRU_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.WRENW (LRU_WIDTH),
.RDW_MODE ("R")
) plru_store (
.clk (clk),
.reset (reset),
.read (~stall),
.read (repl_valid),
.write (hit_valid),
.wren (plru_wmask),
.waddr (hit_line),
.raddr (repl_line_n),
.raddr (repl_line),
.wdata (plru_wdata),
.rdata (plru_rdata)
);
@ -158,18 +155,17 @@ module VX_cache_repl #(
wire [WAY_SEL_WIDTH-1:0] ctr_rdata;
wire [WAY_SEL_WIDTH-1:0] ctr_wdata = ctr_rdata + 1;
VX_dp_ram #(
.DATAW (WAY_SEL_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.OUT_REG (1)
VX_sp_ram #(
.DATAW (WAY_SEL_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.RDW_MODE ("R")
) ctr_store (
.clk (clk),
.reset (reset),
.read (~stall),
.read (repl_valid),
.write (repl_valid),
.wren (1'b1),
.raddr (repl_line_n),
.waddr (repl_line),
.addr (repl_line),
.wdata (ctr_wdata),
.rdata (ctr_rdata)
);
@ -182,7 +178,6 @@ module VX_cache_repl #(
`UNUSED_VAR (hit_way)
`UNUSED_VAR (repl_valid)
`UNUSED_VAR (repl_line)
`UNUSED_VAR (repl_line_n)
reg [WAY_SEL_WIDTH-1:0] victim_idx;
always @(posedge clk) begin
if (reset) begin
@ -201,7 +196,6 @@ module VX_cache_repl #(
`UNUSED_VAR (hit_way)
`UNUSED_VAR (repl_valid)
`UNUSED_VAR (repl_line)
`UNUSED_VAR (repl_line_n)
assign repl_way = 1'b0;
end

12
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -29,7 +29,6 @@ module VX_cache_tags #(
) (
input wire clk,
input wire reset,
input wire stall,
// inputs
input wire init,
@ -37,7 +36,6 @@ module VX_cache_tags #(
input wire fill,
input wire read,
input wire write,
input wire [`CS_LINE_SEL_BITS-1:0] line_idx_n,
input wire [`CS_LINE_SEL_BITS-1:0] line_idx,
input wire [`CS_TAG_SEL_BITS-1:0] line_tag,
input wire [`CS_WAY_SEL_WIDTH-1:0] evict_way,
@ -71,7 +69,7 @@ module VX_cache_tags #(
wire do_flush = flush && (!WRITEBACK || way_en); // flush the whole line in writethrough mode
wire do_write = WRITEBACK && write && tag_matches[i]; // only write on tag hit
//wire line_read = read || write || (WRITEBACK && (fill || flush));
wire line_read = read || write || (WRITEBACK && (fill || flush));
wire line_write = do_init || do_fill || do_flush || do_write;
wire line_valid = fill || write;
@ -87,19 +85,17 @@ module VX_cache_tags #(
assign read_dirty[i] = 1'b0;
end
VX_dp_ram #(
VX_sp_ram #(
.DATAW (TAG_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.OUT_REG (1),
.RDW_MODE ("W")
) tag_store (
.clk (clk),
.reset (reset),
.read (~stall),
.read (line_read),
.write (line_write),
.wren (1'b1),
.waddr (line_idx),
.raddr (line_idx_n),
.addr (line_idx),
.wdata (line_wdata),
.rdata (line_rdata)
);

2
hw/rtl/core/VX_fetch.sv
View file

@ -53,7 +53,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
VX_dp_ram #(
.DATAW (`PC_BITS + `NUM_THREADS),
.SIZE (`NUM_WARPS),
.OUT_REG (0)
.RDW_MODE ("R")
) tag_store (
.clk (clk),
.reset (reset),

3
hw/rtl/core/VX_ipdom_stack.sv
View file

@ -75,7 +75,8 @@ module VX_ipdom_stack #(
VX_dp_ram #(
.DATAW (1 + WIDTH * 2),
.SIZE (DEPTH),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) ipdom_store (
.clk (clk),
.reset (reset),

2
hw/rtl/libs/VX_dp_ram.sv
View file

@ -20,7 +20,7 @@ module VX_dp_ram #(
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 0,
parameter `STRING RDW_MODE = "R", // R: read-first, W: write-first, U: undefined
parameter `STRING RDW_MODE = "W", // W: write-first, R: read-first, U: undefined
parameter RDW_ASSERT = 0,
parameter RESET_RAM = 0,
parameter INIT_ENABLE = 0,

11
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -77,20 +77,16 @@ module VX_fifo_queue #(
localparam ADDRW = `CLOG2(DEPTH);
wire [DATAW-1:0] data_out_w;
reg [ADDRW-1:0] rd_ptr_r, rd_ptr_n;
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r;
always @(*) begin
rd_ptr_n = rd_ptr_r + ADDRW'(pop);
end
always @(posedge clk) begin
if (reset) begin
wr_ptr_r <= '0;
rd_ptr_r <= (OUT_REG != 0) ? 1 : 0;
end else begin
wr_ptr_r <= wr_ptr_r + ADDRW'(push);
rd_ptr_r <= rd_ptr_n;
rd_ptr_r <= rd_ptr_r + ADDRW'(pop);
end
end
@ -100,7 +96,6 @@ module VX_fifo_queue #(
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (DEPTH),
.OUT_REG (1),
.LUTRAM (LUTRAM),
.RDW_MODE ("W")
) dp_ram (
@ -109,9 +104,9 @@ module VX_fifo_queue #(
.read (~bypass),
.write (push),
.wren (1'b1),
.raddr (rd_ptr_r),
.waddr (wr_ptr_r),
.wdata (data_in),
.raddr (rd_ptr_n),
.rdata (data_out_w)
);

3
hw/rtl/libs/VX_index_buffer.sv
View file

@ -50,8 +50,7 @@ module VX_index_buffer #(
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUT_REG (0),
.RDW_MODE("W")
.RDW_MODE ("R")
) data_table (
.clk (clk),
.reset (reset),

6
hw/rtl/libs/VX_scope_tap.sv
View file

@ -112,7 +112,8 @@ module VX_scope_tap #(
VX_dp_ram #(
.DATAW (IDLE_CTRW),
.SIZE (DEPTH),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) delta_store (
.clk (clk),
.reset (reset),
@ -133,7 +134,8 @@ module VX_scope_tap #(
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (DEPTH),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) data_store (
.clk (clk),
.reset (reset),

53
hw/rtl/libs/VX_sp_ram.sv
View file

@ -20,7 +20,7 @@ module VX_sp_ram #(
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 0,
parameter `STRING RDW_MODE = "R", // R: read-first, W: write-first, N: no-change
parameter `STRING RDW_MODE = "W", // W: write-first, R: read-first, N: no-change, U: undefined
parameter RDW_ASSERT = 0,
parameter RESET_RAM = 0,
parameter INIT_ENABLE = 0,
@ -75,14 +75,13 @@ module VX_sp_ram #(
end
`endif
if (OUT_REG) begin : g_sync
wire cs = read || write;
if (FORCE_BRAM) begin : g_bram
if (RDW_MODE == "R") begin : g_read_first
`USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
@ -96,7 +95,7 @@ module VX_sp_ram #(
if (WRENW > 1) begin : g_wren
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
@ -108,7 +107,7 @@ module VX_sp_ram #(
`UNUSED_VAR (wren)
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
ram[addr] <= wdata;
rdata_r <= wdata;
@ -124,7 +123,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end else begin
@ -133,6 +132,19 @@ module VX_sp_ram #(
end
end
assign rdata = rdata_r;
end else if (RDW_MODE == "U") begin : g_unknown
`USE_BLOCK_BRAM `RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE
end
if (read) begin
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end
end else begin : g_auto
if (RDW_MODE == "R") begin : g_read_first
@ -140,7 +152,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
@ -154,7 +166,7 @@ module VX_sp_ram #(
if (WRENW > 1) begin : g_wren
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end
@ -166,7 +178,7 @@ module VX_sp_ram #(
`UNUSED_VAR (wren)
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
ram[addr] <= wdata;
rdata_r <= wdata;
@ -182,7 +194,7 @@ module VX_sp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (cs) begin
if (read || write) begin
if (write) begin
`RAM_WRITE
end else begin
@ -191,6 +203,19 @@ module VX_sp_ram #(
end
end
assign rdata = rdata_r;
end else if (RDW_MODE == "U") begin : g_unknown
`RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE
end
if (read) begin
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end
end
end else begin : g_async
@ -281,6 +306,14 @@ module VX_sp_ram #(
end
end
assign rdata = rdata_r;
end else if (RDW_MODE == "U") begin : g_unknown
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (read) begin
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end
end else begin : g_async
`UNUSED_VAR (read)

3
hw/rtl/mem/VX_local_mem.sv
View file

@ -166,7 +166,8 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.DATAW (WORD_WIDTH),
.SIZE (WORDS_PER_BANK),
.WRENW (WORD_SIZE),
.OUT_REG (1)
.OUT_REG (1),
.RDW_MODE ("R")
) lmem_store (
.clk (clk),
.reset (reset),