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1 WARP 8 THREADS TESTED + FULLY WORKING

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This commit is contained in:
felsabbagh3 2019-03-31 05:21:00 -04:00
parent c83ef94d02
commit 8c2ae97510
21 changed files with 6389 additions and 998 deletions
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1
.gitignore vendored
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@ -0,0 +1 @@
./rtl/obj_dir/debug.txt

2
kernel/vortex_test.dump
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@ -7,7 +7,7 @@ Disassembly of section .text:
80000000 <_start>:
80000000: 00100513 li a0,1
80000004: 02051073 csrw 0x20,a0
80000008: 00200513 li a0,2
80000008: 00800513 li a0,8
8000000c: 02151073 csrw 0x21,a0
80000010: f1401073 csrw mhartid,zero
80000014: 30101073 csrw misa,zero

BIN
kernel/vortex_test.elf
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2
kernel/vortex_test.hex
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@ -1,5 +1,5 @@
:0200000480007A
:10000000130510007310050213052000731015026C
:10000000130510007310050213058000731015020C
:10001000731040F17310103037F1FF7FEF0080193B
:10002000EF10C06D73000000938B0600130D0700E6
:10003000130F01009303050013051000635C7500A6

2
kernel/vx_os/vx_back/vx_back.s
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@ -8,7 +8,7 @@
_start:
li a0, 1 # Num Warps
csrw 0x20, a0 # Setting the number of available warps
li a0, 2 # Num Threads
li a0, 8 # Num Threads
csrw 0x21, a0 # Setting the number of available threads
csrw mhartid,zero
csrw misa,zero

85
rtl/VX_decode.v
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@ -139,9 +139,9 @@ module VX_decode(
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
always @(*) begin
$display("DECODE PC: %h",in_curr_PC);
end
// always @(*) begin
// $display("DECODE PC: %h",in_curr_PC);
// end
// always @(posedge clk) begin
@ -164,45 +164,46 @@ module VX_decode(
);
wire to_clone_1 = (1 == rd1_register[0]) && (state_stall == 1);
// wire to_clone_1 = (1 == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_valid (in_wb_valid[1]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[1]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_clone (is_clone),
.in_to_clone (to_clone_1),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[1]),
.out_src2_data (rd2_register[1])
);
// genvar index;
// generate
// for (index=1; index < `NT; index=index+1)
// begin: gen_code_label
// VX_register_file_slave vx_register_file_slave(
// .clk (clk),
// .in_valid (in_wb_valid[index]),
// .in_valid (in_wb_valid[1]),
// .in_write_register (write_register),
// .in_rd (in_rd),
// .in_data (in_write_data[index]),
// .in_data (in_write_data[1]),
// .in_src1 (out_rs1),
// .in_src2 (out_rs2),
// .in_clone (is_clone),
// .in_to_clone (index == rd1_register[0]),
// .in_to_clone (to_clone_1),
// .in_regs (clone_regsiters),
// .out_src1_data (rd1_register[index]),
// .out_src2_data (rd2_register[index])
// .out_src1_data (rd1_register[1]),
// .out_src2_data (rd2_register[1])
// );
// end
// endgenerate
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_valid (in_wb_valid[index]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_clone (is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
assign curr_opcode = in_instruction[6:0];
@ -237,11 +238,11 @@ module VX_decode(
assign is_jalrs = is_gpgpu && (func3 == 6);
assign is_jmprt = is_gpgpu && (func3 == 4);
always @(*) begin
if (is_jalrs) begin
$display("JALRS WOHOOO: rs2 - %h", out_b_reg_data[0]);
end
end
// always @(*) begin
// if (is_jalrs) begin
// $display("JALRS WOHOOO: rs2 - %h", out_b_reg_data[0]);
// end
// end
wire jalrs_thread_mask[`NT_M1:0];
@ -272,21 +273,21 @@ module VX_decode(
// assign out_clone = is_clone;
always @(in_instruction) begin
$display("Decode inst: %h", in_instruction);
end
// always @(in_instruction) begin
// $display("Decode inst: %h", in_instruction);
// end
reg[5:0] state_stall = 0;
always @(posedge clk) begin
if ((is_clone) && state_stall == 0) begin
state_stall <= 10;
$display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end else if (state_stall == 1) begin
$display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, is_clone);
// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, is_clone);
state_stall <= 0;
end else if (state_stall > 0) begin
state_stall <= state_stall - 1;
$display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end
end

4
rtl/VX_define.h
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@ -1,7 +1,7 @@
#define NT 5
#define NT_M1 4
#define NT 8
#define NT_M1 7
#define R_INST 51
#define L_INST 3

4
rtl/VX_define.v
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@ -1,6 +1,6 @@
`define NT 5
`define NT_M1 4
`define NT 8
`define NT_M1 7
`define R_INST 7'd51

12
rtl/VX_fetch.v
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@ -68,7 +68,7 @@ module VX_fetch (
always @(*) begin : proc_
if (in_change_mask) begin
$display("CHANGING MASK: [%d %d]",in_thread_mask[0], in_thread_mask[1]);
// $display("CHANGING MASK: [%d %d]",in_thread_mask[0], in_thread_mask[1]);
assign valid = in_thread_mask;
end
end
@ -100,7 +100,7 @@ module VX_fetch (
PC_to_use = real_PC;
end
end else if (stall_reg == 1'b1) begin
$display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC);
// $display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC);
PC_to_use = old;
end else begin
PC_to_use = PC_to_use_temp;
@ -125,7 +125,7 @@ module VX_fetch (
if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin
temp_PC = in_jal_dest;
$display("in_jal_dest: %h",in_jal_dest);
// $display("in_jal_dest: %h",in_jal_dest);
end else if ((in_branch_dir == 1'b1) && (delay_reg == 1'b0)) begin
temp_PC = in_branch_dest;
end else begin
@ -136,9 +136,9 @@ module VX_fetch (
assign out_PC = temp_PC;
always @(*) begin
$display("FETCH PC: %h (%h, %h, %h)",temp_PC, PC_to_use, in_jal_dest, in_branch_dest);
end
// always @(*) begin
// $display("FETCH PC: %h (%h, %h, %h)",temp_PC, PC_to_use, in_jal_dest, in_branch_dest);
// end
always @(*) begin

2
rtl/VX_register_file.v
View file

@ -38,7 +38,7 @@ module VX_register_file (
always @(posedge clk) begin
if(write_enable) begin
$display("RF: Writing %h to %d",write_data, write_register);
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end
end

4
rtl/VX_register_file_slave.v
View file

@ -43,10 +43,10 @@ module VX_register_file_slave (
always @(posedge clk) begin
if(write_enable && !in_clone) begin
$display("RF: Writing %h to %d",write_data, write_register);
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end else if (in_clone && in_to_clone) begin
$display("CLONING IN SLAVE");
// $display("CLONING IN SLAVE");
registers <= in_regs;
end
end

14
rtl/VX_writeback.v
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@ -3,13 +3,17 @@
module VX_writeback (
/* verilator lint_off UNUSED */
input wire clk,
/* verilator lint_off UNUSED */
input wire[31:0] in_alu_result[`NT_M1:0],
input wire[31:0] in_mem_result[`NT_M1:0],
input wire[4:0] in_rd,
input wire[1:0] in_wb,
input wire[31:0] in_PC_next,
/* verilator lint_off UNUSED */
input wire in_valid[`NT_M1:0],
/* verilator lint_on UNUSED */
output wire[31:0] out_write_data[`NT_M1:0],
output wire[4:0] out_rd,
@ -40,11 +44,11 @@ module VX_writeback (
in_mem_result;
always @(negedge clk) begin
if (in_wb != 0) begin
$display("[%h] WB Data: %h {%h}, to register: %d [%d %d]",in_PC_next - 4, out_write_data[0], in_mem_result[0], in_rd, in_valid[0], in_valid[1]);
end
end
// always @(negedge clk) begin
// if (in_wb != 0) begin
// $display("[%h] WB Data: %h {%h}, to register: %d [%d %d]",in_PC_next - 4, out_write_data[0], in_mem_result[0], in_rd, in_valid[0], in_valid[1]);
// end
// end
assign out_rd = in_rd;
assign out_wb = in_wb;

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rtl/obj_dir/VVortex
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6929
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load diff

268
rtl/obj_dir/VVortex.h
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@ -27,10 +27,10 @@ VL_MODULE(VVortex) {
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_IN(fe_instruction,31,0);
VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[5],31,0);
VL_OUT(out_cache_driver_in_address[5],31,0);
VL_OUT8(out_cache_driver_in_valid[5],0,0);
VL_OUT(out_cache_driver_in_data[5],31,0);
VL_IN(in_cache_driver_out_data[8],31,0);
VL_OUT(out_cache_driver_in_address[8],31,0);
VL_OUT8(out_cache_driver_in_valid[8],0,0);
VL_OUT(out_cache_driver_in_data[8],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
@ -58,7 +58,6 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__to_clone_1,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
@ -101,9 +100,9 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_fetch__DOT__BR_reg,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__PC_to_use,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
@ -116,6 +115,9 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__5__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__6__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__7__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
@ -127,59 +129,68 @@ VL_MODULE(VVortex) {
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__4__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__5__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__6__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__7__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__fetch_valid[5],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[5],0,0);
VL_SIG(Vortex__DOT__decode_a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__decode_b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__decode_valid[5],0,0);
VL_SIG8(Vortex__DOT__decode_thread_mask[5],0,0);
VL_SIG(Vortex__DOT__d_e_a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__d_e_b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[5],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[5],31,0);
VL_SIG(Vortex__DOT__execute_b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__execute_valid[5],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[5],31,0);
VL_SIG(Vortex__DOT__e_m_b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[5],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[5],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[5],31,0);
VL_SIG8(Vortex__DOT__memory_valid[5],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[5],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[5],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[5],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[5],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[5],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[5],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid[5],0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[5],31,0);
VL_SIG8(Vortex__DOT__fetch_valid[8],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[8],0,0);
VL_SIG(Vortex__DOT__decode_a_reg_data[8],31,0);
VL_SIG(Vortex__DOT__decode_b_reg_data[8],31,0);
VL_SIG8(Vortex__DOT__decode_valid[8],0,0);
VL_SIG8(Vortex__DOT__decode_thread_mask[8],0,0);
VL_SIG(Vortex__DOT__d_e_a_reg_data[8],31,0);
VL_SIG(Vortex__DOT__d_e_b_reg_data[8],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[8],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[8],31,0);
VL_SIG(Vortex__DOT__execute_b_reg_data[8],31,0);
VL_SIG8(Vortex__DOT__execute_valid[8],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[8],31,0);
VL_SIG(Vortex__DOT__e_m_b_reg_data[8],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[8],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[8],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[8],31,0);
VL_SIG8(Vortex__DOT__memory_valid[8],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[8],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[8],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[8],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[8],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[8],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[8],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid[8],0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[8],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[8],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[8],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__clone_regsiters[32],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[8],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[8],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[5],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[5],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[5],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[5],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[5],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__5__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__6__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__7__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[8],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[8],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[8],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[8],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[8],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[8],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[8],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[8],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[8],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[8],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[8],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[8],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[8],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[8],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[8],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[8],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
@ -190,81 +201,101 @@ VL_MODULE(VVortex) {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5,0,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v6,0,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v8,0,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v9,0,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__5__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__5__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__6__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__6__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__7__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__7__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[5],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[5],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[5],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[5],0,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[8],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[8],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[8],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[8],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[8],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[8],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[8],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[8],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[8],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[8],31,0);
};
struct {
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[5],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[8],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[8],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[8],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[8],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[8],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__5__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__6__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__gen_code_label__BRA__7__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
@ -300,8 +331,8 @@ VL_MODULE(VVortex) {
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
@ -314,13 +345,12 @@ VL_MODULE(VVortex) {
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _multiclk__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__9(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

BIN
rtl/obj_dir/VVortex__ALL.a
View file

Binary file not shown.

BIN
rtl/obj_dir/VVortex__ALLcls.o
View file

Binary file not shown.

48
rtl/obj_dir/VVortex__verFiles.dat
View file

@ -1,27 +1,27 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2862 12889318286 1553966962 0 1553966962 0 "VX_alu.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 5105 12889318287 1554013046 0 1554013046 0 "VX_d_e_reg.v"
S 15001 12889419225 1554022101 0 1554022101 0 "VX_decode.v"
S 1557 12889419227 1554008503 0 1554008503 0 "VX_define.v"
S 4077 12889318289 1553997299 0 1553997299 0 "VX_e_m_reg.v"
S 3288 12889318290 1554000824 0 1554000824 0 "VX_execute.v"
S 1540 12889050060 1554018831 0 1554018831 0 "VX_f_d_reg.v"
S 4588 12889419228 1554021543 0 1554021543 0 "VX_fetch.v"
S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 3002 12889084513 1553997670 0 1553997670 0 "VX_memory.v"
S 1075 12889419229 1554007548 0 1554007548 0 "VX_register_file.v"
S 1381 12889437241 1554016243 0 1554016243 0 "VX_register_file_slave.v"
S 1173 12889419230 1553930874 0 1553930874 0 "VX_writeback.v"
S 16910 12889419231 1554021042 0 1554021042 0 "Vortex.v"
T 416263 12889432530 1554022103 0 1554022103 0 "obj_dir/VVortex.cpp"
T 17158 12889432529 1554022103 0 1554022103 0 "obj_dir/VVortex.h"
T 1800 12889432532 1554022103 0 1554022103 0 "obj_dir/VVortex.mk"
T 530 12889432528 1554022103 0 1554022103 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889432527 1554022103 0 1554022103 0 "obj_dir/VVortex__Syms.h"
T 489 12889432533 1554022103 0 1554022103 0 "obj_dir/VVortex__ver.d"
T 0 0 1554022103 0 1554022103 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889432531 1554022103 0 1554022103 0 "obj_dir/VVortex_classes.mk"
S 2862 12889457986 1554023089 0 1554023089 0 "VX_alu.v"
S 1495 12889457987 1554023089 0 1554023089 0 "VX_csr_handler.v"
S 5105 12889457988 1554023089 0 1554023089 0 "VX_d_e_reg.v"
S 15102 12889457989 1554023916 0 1554023916 0 "VX_decode.v"
S 1557 12889457991 1554023528 0 1554023528 0 "VX_define.v"
S 4077 12889457992 1554023089 0 1554023089 0 "VX_e_m_reg.v"
S 3288 12889457993 1554023938 0 1554023938 0 "VX_execute.v"
S 1540 12889457994 1554023089 0 1554023089 0 "VX_f_d_reg.v"
S 4606 12889457995 1554023897 0 1554023897 0 "VX_fetch.v"
S 5632 12889457996 1554023089 0 1554023089 0 "VX_forwarding.v"
S 1677 12889457997 1554023089 0 1554023089 0 "VX_m_w_reg.v"
S 3002 12889457998 1554023089 0 1554023089 0 "VX_memory.v"
S 1078 12889457999 1554023928 0 1554023928 0 "VX_register_file.v"
S 1387 12889458000 1554023933 0 1554023933 0 "VX_register_file_slave.v"
S 1323 12889458001 1554023982 0 1554023982 0 "VX_writeback.v"
S 16910 12889458002 1554023089 0 1554023089 0 "Vortex.v"
T 797432 12889458029 1554023984 0 1554023984 0 "obj_dir/VVortex.cpp"
T 21112 12889458030 1554023984 0 1554023984 0 "obj_dir/VVortex.h"
T 1800 12889458031 1554023984 0 1554023984 0 "obj_dir/VVortex.mk"
T 530 12889458039 1554023984 0 1554023984 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889458040 1554023984 0 1554023984 0 "obj_dir/VVortex__Syms.h"
T 489 12889458041 1554023984 0 1554023984 0 "obj_dir/VVortex__ver.d"
T 0 0 1554023984 0 1554023984 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889458043 1554023984 0 1554023984 0 "obj_dir/VVortex_classes.mk"

BIN
rtl/obj_dir/test_bench.o
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Binary file not shown.

6
rtl/results.txt
View file

@ -1,9 +1,9 @@
**************** ../../kernel/vortex_test.hex ****************
# Dynamic Instructions: 482804
# of total cycles: 482816
# Dynamic Instructions: 365972
# of total cycles: 365984
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00002
# CPI: 1.00003
# time to simulate: 6.95312e-310 milliseconds
# GRADE: Failed on test: 0

4
rtl/test_bench.h
View file

@ -198,7 +198,7 @@ bool Vortex::dbus_driver()
ram.writeHalf( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
{
printf("STORING %x in %x \n", data_write, addr);
// printf("STORING %x in %x \n", data_write, addr);
data_write = data_write;
ram.writeWord( addr, &data_write);
}
@ -232,7 +232,7 @@ bool Vortex::dbus_driver()
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
{
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
// std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
std::cout << std::dec;
vortex->in_cache_driver_out_data[curr_th] = data_read;