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1 WARP 2 THREADS WORKING

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felsabbagh3 2019-03-31 05:02:55 -04:00
parent 4aac33b298
commit c83ef94d02
50 changed files with 8125 additions and 117160 deletions
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4
kernel/vortex_test.dump
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@ -5,9 +5,9 @@ vortex_test.elf: file format elf32-littleriscv
Disassembly of section .text:
80000000 <_start>:
80000000: 00400513 li a0,4
80000000: 00100513 li a0,1
80000004: 02051073 csrw 0x20,a0
80000008: 00800513 li a0,8
80000008: 00200513 li a0,2
8000000c: 02151073 csrw 0x21,a0
80000010: f1401073 csrw mhartid,zero
80000014: 30101073 csrw misa,zero

BIN
kernel/vortex_test.elf
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Binary file not shown.

2
kernel/vortex_test.hex
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@ -1,5 +1,5 @@
:0200000480007A
:1000000013054000731005021305800073101502DC
:10000000130510007310050213052000731015026C
:10001000731040F17310103037F1FF7FEF0080193B
:10002000EF10C06D73000000938B0600130D0700E6
:10003000130F01009303050013051000635C7500A6

4
kernel/vx_os/vx_back/vx_back.s
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@ -6,9 +6,9 @@
.type _start, @function
.global _start
_start:
li a0, 4 # Num Warps
li a0, 1 # Num Warps
csrw 0x20, a0 # Setting the number of available warps
li a0, 8 # Num Threads
li a0, 2 # Num Threads
csrw 0x21, a0 # Setting the number of available threads
csrw mhartid,zero
csrw misa,zero

0
results.txt
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2
rtl/Makefile
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@ -5,7 +5,7 @@ all: RUNFILE
VERILATOR:
verilator -Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp
verilator -Wall -cc Vortex.v --exe test_bench.cpp
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVortex.mk)

3
rtl/VX_d_e_reg.v
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@ -27,6 +27,7 @@ module VX_d_e_reg (
input wire in_jal,
input wire[31:0] in_jal_offset,
input wire in_freeze,
input wire in_clone_stall,
input wire in_valid[`NT_M1:0],
output wire[11:0] out_csr_address, // done
@ -110,7 +111,7 @@ module VX_d_e_reg (
wire stalling;
assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL);
assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
assign out_rd = rd;
assign out_rs1 = rs1;

173
rtl/VX_decode.v
View file

@ -41,6 +41,9 @@ module VX_decode(
output reg[31:0] out_jal_offset,
output reg[19:0] out_upper_immed,
output wire[31:0] out_PC_next,
output reg out_clone_stall,
output wire out_change_mask,
output wire out_thread_mask[`NT_M1:0],
output wire out_valid[`NT_M1:0]
);
@ -63,6 +66,11 @@ module VX_decode(
wire is_csr_immed;
wire is_e_inst;
wire is_gpgpu;
wire is_clone;
wire is_jalrs;
wire is_jmprt;
wire write_register;
wire[2:0] func3;
@ -131,30 +139,70 @@ module VX_decode(
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
always @(*) begin
$display("DECODE PC: %h",in_curr_PC);
end
// always @(posedge clk) begin
// $display("Decode: curr_pc: %h", in_curr_PC);
// end
genvar index;
wire[31:0] clone_regsiters[31:0];
generate
for (index=0; index < `NT; index=index+1)
begin: gen_code_label
VX_register_file vx_register_file(
.clk(clk),
.in_valid(in_wb_valid[index]),
.in_write_register(write_register),
.in_rd(in_rd),
.in_data(in_write_data[index]),
.in_src1(out_rs1),
.in_src2(out_rs2),
.out_src1_data(rd1_register[index]),
.out_src2_data(rd2_register[index])
VX_register_file vx_register_file_master(
.clk (clk),
.in_valid (in_wb_valid[0]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
wire to_clone_1 = (1 == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_valid (in_wb_valid[1]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[1]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_clone (is_clone),
.in_to_clone (to_clone_1),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[1]),
.out_src2_data (rd2_register[1])
);
end
endgenerate
// genvar index;
// generate
// for (index=1; index < `NT; index=index+1)
// begin: gen_code_label
// VX_register_file_slave vx_register_file_slave(
// .clk (clk),
// .in_valid (in_wb_valid[index]),
// .in_write_register (write_register),
// .in_rd (in_rd),
// .in_data (in_write_data[index]),
// .in_src1 (out_rs1),
// .in_src2 (out_rs2),
// .in_clone (is_clone),
// .in_to_clone (index == rd1_register[0]),
// .in_regs (clone_regsiters),
// .out_src1_data (rd1_register[index]),
// .out_src2_data (rd2_register[index])
// );
// end
// endgenerate
assign curr_opcode = in_instruction[6:0];
@ -184,6 +232,65 @@ module VX_decode(
assign is_csr_immed = (is_csr) && (func3[2] == 1);
assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0);
assign is_gpgpu = (curr_opcode == `GPGPU_INST);
assign is_clone = is_gpgpu && (func3 == 5);
assign is_jalrs = is_gpgpu && (func3 == 6);
assign is_jmprt = is_gpgpu && (func3 == 4);
always @(*) begin
if (is_jalrs) begin
$display("JALRS WOHOOO: rs2 - %h", out_b_reg_data[0]);
end
end
wire jalrs_thread_mask[`NT_M1:0];
wire jmprt_thread_mask[`NT_M1:0];
genvar tm_i;
generate
for (tm_i = 0; tm_i < `NT; tm_i = tm_i + 1) begin
assign jalrs_thread_mask[tm_i] = tm_i <= $signed(out_b_reg_data[0]);
end
endgenerate
genvar tm_ji;
generate
assign jmprt_thread_mask[0] = 1;
for (tm_ji = 1; tm_ji < `NT; tm_ji = tm_ji + 1) begin
assign jmprt_thread_mask[tm_ji] = 0;
end
endgenerate
assign out_thread_mask = is_jalrs ? jalrs_thread_mask : jmprt_thread_mask;
assign out_change_mask = is_jalrs || is_jmprt;
// assign out_clone = is_clone;
always @(in_instruction) begin
$display("Decode inst: %h", in_instruction);
end
reg[5:0] state_stall = 0;
always @(posedge clk) begin
if ((is_clone) && state_stall == 0) begin
state_stall <= 10;
$display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end else if (state_stall == 1) begin
$display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, is_clone);
state_stall <= 0;
end else if (state_stall > 0) begin
state_stall <= state_stall - 1;
$display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end
end
assign out_clone_stall = ((state_stall == 0) && is_clone) || ((state_stall != 1) && is_clone);
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
@ -221,7 +328,7 @@ module VX_decode(
assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_a_reg_data[0];
assign out_wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL :
assign out_wb = (is_jal || is_jalr || is_jalrs || is_e_inst) ? `WB_JAL :
is_linst ? `WB_MEM :
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
`NO_WB;
@ -267,22 +374,30 @@ module VX_decode(
case(curr_opcode)
`JAL_INST:
begin
out_jal = 1'b1;
out_jal = 1'b1 && in_valid[0];
out_jal_offset = jal_1_offset;
end
`JALR_INST:
begin
out_jal = 1'b1;
out_jal = 1'b1 && in_valid[0];
out_jal_offset = jal_2_offset;
end
`GPGPU_INST:
begin
if (is_jalrs || is_jmprt)
begin
out_jal = 1'b1 && in_valid[0];
out_jal_offset = 32'h0;
end
end
`SYS_INST:
begin
out_jal = jal_sys_jal;
out_jal = jal_sys_jal && in_valid[0];
out_jal_offset = jal_sys_off;
end
default:
begin
out_jal = 1'b0;
out_jal = 1'b0 && in_valid[0];
out_jal_offset = 32'hdeadbeef;
end
endcase
@ -318,7 +433,7 @@ module VX_decode(
case(curr_opcode)
`B_INST:
begin
out_branch_stall = 1'b1;
out_branch_stall = 1'b1 && in_valid[0];
case(func3)
3'h0: out_branch_type = `BEQ;
3'h1: out_branch_type = `BNE;
@ -333,17 +448,25 @@ module VX_decode(
`JAL_INST:
begin
out_branch_type = `NO_BRANCH;
out_branch_stall = 1'b1;
out_branch_stall = 1'b1 && in_valid[0];
end
`JALR_INST:
begin
out_branch_type = `NO_BRANCH;
out_branch_stall = 1'b1;
out_branch_stall = 1'b1 && in_valid[0];
end
`GPGPU_INST:
begin
if (is_jalrs || is_jmprt)
begin
out_branch_type = `NO_BRANCH;
out_branch_stall = 1'b1 && in_valid[0];
end
end
default:
begin
out_branch_type = `NO_BRANCH;
out_branch_stall = 1'b0;
out_branch_stall = 1'b0 && in_valid[0];
end
endcase
end

1
rtl/VX_define.v
View file

@ -13,6 +13,7 @@
`define JAL_INST 7'd111
`define JALR_INST 7'd103
`define SYS_INST 7'd115
`define GPGPU_INST 7'h6b
`define WB_ALU 2'h1

10
rtl/VX_f_d_reg.v
View file

@ -9,6 +9,7 @@ module VX_f_d_reg (
input wire[31:0] in_curr_PC,
input wire in_fwd_stall,
input wire in_freeze,
input wire in_clone_stall,
output wire[31:0] out_instruction,
output wire[31:0] out_curr_PC,
@ -25,6 +26,9 @@ module VX_f_d_reg (
integer reset_cur_thread = 0;
always @(in_instruction) begin
$display("in_instruction: %h",in_instruction);
end
always @(posedge clk or posedge reset) begin
if(reset) begin
@ -33,8 +37,10 @@ module VX_f_d_reg (
for (reset_cur_thread = 0; reset_cur_thread < `NT; reset_cur_thread = reset_cur_thread + 1)
valid[reset_cur_thread] <= 1'b0;
end else if (in_fwd_stall == 1'b1 || in_freeze == 1'b1) begin
// $display("Because of FWD stall keeping pc: %h", curr_PC);
end else if (in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall) begin
if (in_clone_stall) begin
$display("STALL BECAUSE OF CLONE");
end
end else begin
instruction <= in_instruction;
valid <= in_valid;

25
rtl/VX_fetch.v
View file

@ -10,11 +10,14 @@ module VX_fetch (
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_interrupt,
input wire in_debug,
input wire[31:0] in_instruction,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
output wire[31:0] out_instruction,
output wire out_delay,
@ -42,7 +45,7 @@ module VX_fetch (
reg[4:0] temp_state;
reg[4:0] tempp_state;
reg[`NT_M1:0] valid;
reg valid[`NT_M1:0];
integer ini_cur_th = 0;
@ -62,6 +65,14 @@ module VX_fetch (
prev_debug = 0;
end
always @(*) begin : proc_
if (in_change_mask) begin
$display("CHANGING MASK: [%d %d]",in_thread_mask[0], in_thread_mask[1]);
assign valid = in_thread_mask;
end
end
always @(*) begin
case(state)
5'h00: PC_to_use_temp = real_PC;
@ -89,20 +100,21 @@ module VX_fetch (
PC_to_use = real_PC;
end
end else if (stall_reg == 1'b1) begin
// $display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC);
$display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC);
PC_to_use = old;
end else begin
PC_to_use = PC_to_use_temp;
end
end
assign stall = in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze;
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze;
assign out_instruction = stall ? 32'b0 : in_instruction;
// assign out_instruction = in_instruction;
generate
for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1)
assign out_valid[out_cur_th] = stall ? 1'b0 : valid[out_cur_th];
assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th];
endgenerate
@ -113,6 +125,7 @@ module VX_fetch (
if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin
temp_PC = in_jal_dest;
$display("in_jal_dest: %h",in_jal_dest);
end else if ((in_branch_dir == 1'b1) && (delay_reg == 1'b0)) begin
temp_PC = in_branch_dest;
end else begin
@ -123,6 +136,10 @@ module VX_fetch (
assign out_PC = temp_PC;
always @(*) begin
$display("FETCH PC: %h (%h, %h, %h)",temp_PC, PC_to_use, in_jal_dest, in_branch_dest);
end
always @(*) begin
if (in_jal == 1'b1) begin

7
rtl/VX_register_file.v
View file

@ -9,8 +9,9 @@ module VX_register_file (
input wire[4:0] in_src1,
input wire[4:0] in_src2,
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data
output wire[31:0] out_regs[31:0],
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data
);
reg[31:0] registers[31:0];
@ -28,6 +29,8 @@ module VX_register_file (
// end
// end
assign out_regs = registers;
assign write_data = in_data;
assign write_register = in_rd;

66
rtl/VX_register_file_slave.v Normal file
View file

@ -0,0 +1,66 @@
module VX_register_file_slave (
input wire clk,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire in_clone,
input wire in_to_clone,
input wire[31:0] in_regs[31:0],
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data
);
reg[31:0] registers[31:0];
wire[31:0] write_data;
wire[4:0] write_register;
wire write_enable;
// reg[5:0] i;
// always @(posedge clk) begin
// for (i = 0; i < 32; i++) begin
// $display("%d: %h",i, registers[i[4:0]]);
// end
// end
// integer i;
assign write_data = in_data;
assign write_register = in_rd;
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid;
always @(posedge clk) begin
if(write_enable && !in_clone) begin
$display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end else if (in_clone && in_to_clone) begin
$display("CLONING IN SLAVE");
registers <= in_regs;
end
end
// always @(posedge clk) begin
// for (i = 0; i < 32; i = i + 1)
// $display("(%d): %x", i, registers[i]);
// end
always @(negedge clk) begin
out_src1_data <= registers[in_src1];
out_src2_data <= registers[in_src2];
end
endmodule

15
rtl/Vortex.v
View file

@ -56,7 +56,10 @@ reg decode_jal;
reg[31:0] decode_jal_offset;
reg[19:0] decode_upper_immed;
wire[31:0] decode_PC_next;
wire decode_valid[`NT_M1:0];
wire decode_valid[`NT_M1:0];
wire decode_clone_stall;
wire decode_change_mask;
wire decode_thread_mask[`NT_M1:0];
// From d_e_register
wire[11:0] d_e_csr_address;
@ -192,11 +195,14 @@ VX_fetch vx_fetch(
.in_branch_stall (decode_branch_stall),
.in_fwd_stall (forwarding_fwd_stall),
.in_branch_stall_exe(execute_branch_stall),
.in_clone_stall (decode_clone_stall),
.in_jal (e_m_jal),
.in_jal_dest (e_m_jal_dest),
.in_interrupt (interrupt),
.in_debug (debug),
.in_instruction (fe_instruction),
.in_thread_mask (decode_thread_mask),
.in_change_mask (decode_change_mask),
.out_instruction (fetch_instruction),
.out_delay (fetch_delay),
@ -213,6 +219,7 @@ VX_f_d_reg vx_f_d_reg(
.in_curr_PC (fetch_curr_PC),
.in_fwd_stall (forwarding_fwd_stall),
.in_freeze (total_freeze),
.in_clone_stall (decode_clone_stall),
.out_instruction(f_d_instruction),
.out_curr_PC (f_d_curr_PC),
.out_valid (f_d_valid)
@ -254,7 +261,10 @@ VX_decode vx_decode(
.out_jal_offset (decode_jal_offset),
.out_upper_immed (decode_upper_immed),
.out_PC_next (decode_PC_next),
.out_valid (decode_valid)
.out_valid (decode_valid),
.out_clone_stall (decode_clone_stall),
.out_change_mask (decode_change_mask),
.out_thread_mask (decode_thread_mask)
);
@ -284,6 +294,7 @@ VX_d_e_reg vx_d_e_reg(
.in_jal_offset (decode_jal_offset),
.in_freeze (total_freeze),
.in_valid (decode_valid),
.in_clone_stall (decode_clone_stall),
.out_csr_address(d_e_csr_address),
.out_is_csr (d_e_is_csr),

3068
rtl/obj_dir/VVX_decode.cpp Normal file
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File diff suppressed because it is too large Load diff

152
rtl/obj_dir/VVX_decode.h Normal file
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@ -0,0 +1,152 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_decode_H_
#define _VVX_decode_H_
#include "verilated_heavy.h"
class VVX_decode__Syms;
//----------
VL_MODULE(VVX_decode) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(in_rd,4,0);
VL_IN8(in_wb,1,0);
VL_IN8(in_src1_fwd,0,0);
VL_IN8(in_src2_fwd,0,0);
VL_OUT8(out_is_csr,0,0);
VL_OUT8(out_rd,4,0);
VL_OUT8(out_rs1,4,0);
VL_OUT8(out_rs2,4,0);
VL_OUT8(out_wb,1,0);
VL_OUT8(out_alu_op,4,0);
VL_OUT8(out_rs2_src,0,0);
VL_OUT8(out_mem_read,2,0);
VL_OUT8(out_mem_write,2,0);
VL_OUT8(out_branch_type,2,0);
VL_OUT8(out_branch_stall,0,0);
VL_OUT8(out_jal,0,0);
VL_OUT8(out_clone_stall,0,0);
VL_OUT16(out_csr_address,11,0);
VL_IN(in_instruction,31,0);
VL_IN(in_curr_PC,31,0);
VL_OUT(out_csr_mask,31,0);
VL_OUT(out_itype_immed,31,0);
VL_OUT(out_jal_offset,31,0);
VL_OUT(out_upper_immed,19,0);
VL_OUT(out_PC_next,31,0);
VL_IN8(in_valid[5],0,0);
VL_IN(in_write_data[5],31,0);
VL_IN8(in_wb_valid[5],0,0);
VL_IN(in_src1_fwd_data[5],31,0);
VL_IN(in_src2_fwd_data[5],31,0);
VL_OUT(out_a_reg_data[5],31,0);
VL_OUT(out_b_reg_data[5],31,0);
VL_OUT8(out_valid[5],0,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(VX_decode__DOT__is_itype,0,0);
VL_SIG8(VX_decode__DOT__is_csr,0,0);
VL_SIG8(VX_decode__DOT__is_clone,0,0);
VL_SIG8(VX_decode__DOT__mul_alu,4,0);
VL_SIG8(VX_decode__DOT__state_stall,2,0);
VL_SIG8(VX_decode__DOT__temp_final_alu,4,0);
VL_SIG16(VX_decode__DOT__jalr_immed,11,0);
VL_SIG16(VX_decode__DOT__alu_tempp,11,0);
VL_SIG(VX_decode__DOT__rd1_register[5],31,0);
VL_SIG(VX_decode__DOT__rd2_register[5],31,0);
VL_SIG(VX_decode__DOT__clone_regsiters[32],31,0);
VL_SIG(VX_decode__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(VX_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(VX_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(VX_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(VX_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG(VX_decode__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(VX_decode__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(VX_decode__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(VX_decode__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(VX_decode__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(VX_decode__DOT____Vcellinp__gen_code_label__BRA__4__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
static VL_ST_SIG8(__Vtable1_VX_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_decode__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_decode); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_decode(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_decode();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_decode__Syms* symsp, bool first);
private:
static QData _change_request(VVX_decode__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp);
static void _combo__TOP__6(VVX_decode__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
static void _eval(VVX_decode__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_decode__Syms* __restrict vlSymsp);
static void _eval_settle(VVX_decode__Syms* __restrict vlSymsp);
static void _initial__TOP__5(VVX_decode__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVX_decode__Syms* __restrict vlSymsp);
static void _settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

53
rtl/obj_dir/VVX_decode.mk Normal file
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@ -0,0 +1,53 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_decode.mk
default: VVX_decode__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_decode
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_decode
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include VVX_decode_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
rtl/obj_dir/VVX_decode__Syms.cpp Normal file
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@ -0,0 +1,19 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_decode__Syms.h"
#include "VVX_decode.h"
// FUNCTIONS
VVX_decode__Syms::VVX_decode__Syms(VVX_decode* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

34
rtl/obj_dir/VVX_decode__Syms.h Normal file
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@ -0,0 +1,34 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _VVX_decode__Syms_H_
#define _VVX_decode__Syms_H_
#include "verilated_heavy.h"
// INCLUDE MODULE CLASSES
#include "VVX_decode.h"
// SYMS CLASS
class VVX_decode__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVX_decode* TOPp;
// CREATORS
VVX_decode__Syms(VVX_decode* topp, const char* namep);
~VVX_decode__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVX_decode__ver.d Normal file
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@ -0,0 +1 @@
obj_dir/VVX_decode.cpp obj_dir/VVX_decode.h obj_dir/VVX_decode.mk obj_dir/VVX_decode__Syms.cpp obj_dir/VVX_decode__Syms.h obj_dir/VVX_decode__ver.d obj_dir/VVX_decode_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_decode.v VX_define.v VX_register_file.v VX_register_file_slave.v

15
rtl/obj_dir/VVX_decode__verFiles.dat Normal file
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@ -0,0 +1,15 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "VX_decode.v -cc"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 12482 12889419225 1554012698 0 1554012698 0 "VX_decode.v"
S 1557 12889419227 1554008503 0 1554008503 0 "VX_define.v"
S 1075 12889419229 1554007548 0 1554007548 0 "VX_register_file.v"
S 1209 12889437241 1554012117 0 1554012117 0 "VX_register_file_slave.v"
T 191649 12889446512 1554012701 0 1554012701 0 "obj_dir/VVX_decode.cpp"
T 6700 12889446511 1554012701 0 1554012701 0 "obj_dir/VVX_decode.h"
T 1476 12889446514 1554012701 0 1554012701 0 "obj_dir/VVX_decode.mk"
T 545 12889446510 1554012701 0 1554012701 0 "obj_dir/VVX_decode__Syms.cpp"
T 738 12889446509 1554012701 0 1554012701 0 "obj_dir/VVX_decode__Syms.h"
T 356 12889446515 1554012701 0 1554012701 0 "obj_dir/VVX_decode__ver.d"
T 0 0 1554012701 0 1554012701 0 "obj_dir/VVX_decode__verFiles.dat"
T 1168 12889446513 1554012701 0 1554012701 0 "obj_dir/VVX_decode_classes.mk"

38
rtl/obj_dir/VVX_decode_classes.mk Normal file
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@ -0,0 +1,38 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_decode.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_decode \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_decode__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

348
rtl/obj_dir/VVX_register_file.cpp Normal file
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@ -0,0 +1,348 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVX_register_file.h for the primary calling header
#include "VVX_register_file.h"
#include "VVX_register_file__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVX_register_file) {
VVX_register_file__Syms* __restrict vlSymsp = __VlSymsp = new VVX_register_file__Syms(this, name());
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVX_register_file::__Vconfigure(VVX_register_file__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVX_register_file::~VVX_register_file() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void VVX_register_file::eval() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_register_file::eval\n"); );
VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void VVX_register_file::_eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
//--------------------
// Internal Methods
VL_INLINE_OPT void VVX_register_file::_sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_sequent__TOP__1\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// ALWAYS at VX_register_file.v:46
vlTOPp->out_src1_data = vlTOPp->VX_register_file__DOT__registers
[vlTOPp->in_src1];
// ALWAYS at VX_register_file.v:46
vlTOPp->out_src2_data = vlTOPp->VX_register_file__DOT__registers
[vlTOPp->in_src2];
}
VL_INLINE_OPT void VVX_register_file::_sequent__TOP__2(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_sequent__TOP__2\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Variables
// Begin mtask footprint all:
VL_SIG8(__Vdlyvdim0__VX_register_file__DOT__registers__v0,4,0);
VL_SIG8(__Vdlyvset__VX_register_file__DOT__registers__v0,0,0);
VL_SIG(__Vdlyvval__VX_register_file__DOT__registers__v0,31,0);
// Body
__Vdlyvset__VX_register_file__DOT__registers__v0 = 0U;
// ALWAYS at VX_register_file.v:39
if (VL_UNLIKELY((((IData)(vlTOPp->in_write_register)
& (0U != (IData)(vlTOPp->in_rd)))
& (IData)(vlTOPp->in_valid)))) {
VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->in_data,
5,(IData)(vlTOPp->in_rd));
__Vdlyvval__VX_register_file__DOT__registers__v0
= vlTOPp->in_data;
__Vdlyvset__VX_register_file__DOT__registers__v0 = 1U;
__Vdlyvdim0__VX_register_file__DOT__registers__v0
= vlTOPp->in_rd;
}
// ALWAYSPOST at VX_register_file.v:42
if (__Vdlyvset__VX_register_file__DOT__registers__v0) {
vlTOPp->VX_register_file__DOT__registers[__Vdlyvdim0__VX_register_file__DOT__registers__v0]
= __Vdlyvval__VX_register_file__DOT__registers__v0;
}
vlTOPp->out_regs[0x1fU] = vlTOPp->VX_register_file__DOT__registers
[0x1fU];
vlTOPp->out_regs[0x1eU] = vlTOPp->VX_register_file__DOT__registers
[0x1eU];
vlTOPp->out_regs[0x1dU] = vlTOPp->VX_register_file__DOT__registers
[0x1dU];
vlTOPp->out_regs[0x1cU] = vlTOPp->VX_register_file__DOT__registers
[0x1cU];
vlTOPp->out_regs[0x1bU] = vlTOPp->VX_register_file__DOT__registers
[0x1bU];
vlTOPp->out_regs[0x1aU] = vlTOPp->VX_register_file__DOT__registers
[0x1aU];
vlTOPp->out_regs[0x19U] = vlTOPp->VX_register_file__DOT__registers
[0x19U];
vlTOPp->out_regs[0x18U] = vlTOPp->VX_register_file__DOT__registers
[0x18U];
vlTOPp->out_regs[0x17U] = vlTOPp->VX_register_file__DOT__registers
[0x17U];
vlTOPp->out_regs[0x16U] = vlTOPp->VX_register_file__DOT__registers
[0x16U];
vlTOPp->out_regs[0x15U] = vlTOPp->VX_register_file__DOT__registers
[0x15U];
vlTOPp->out_regs[0x14U] = vlTOPp->VX_register_file__DOT__registers
[0x14U];
vlTOPp->out_regs[0x13U] = vlTOPp->VX_register_file__DOT__registers
[0x13U];
vlTOPp->out_regs[0x12U] = vlTOPp->VX_register_file__DOT__registers
[0x12U];
vlTOPp->out_regs[0x11U] = vlTOPp->VX_register_file__DOT__registers
[0x11U];
vlTOPp->out_regs[0x10U] = vlTOPp->VX_register_file__DOT__registers
[0x10U];
vlTOPp->out_regs[0xfU] = vlTOPp->VX_register_file__DOT__registers
[0xfU];
vlTOPp->out_regs[0xeU] = vlTOPp->VX_register_file__DOT__registers
[0xeU];
vlTOPp->out_regs[0xdU] = vlTOPp->VX_register_file__DOT__registers
[0xdU];
vlTOPp->out_regs[0xcU] = vlTOPp->VX_register_file__DOT__registers
[0xcU];
vlTOPp->out_regs[0xbU] = vlTOPp->VX_register_file__DOT__registers
[0xbU];
vlTOPp->out_regs[0xaU] = vlTOPp->VX_register_file__DOT__registers
[0xaU];
vlTOPp->out_regs[9U] = vlTOPp->VX_register_file__DOT__registers
[9U];
vlTOPp->out_regs[8U] = vlTOPp->VX_register_file__DOT__registers
[8U];
vlTOPp->out_regs[7U] = vlTOPp->VX_register_file__DOT__registers
[7U];
vlTOPp->out_regs[6U] = vlTOPp->VX_register_file__DOT__registers
[6U];
vlTOPp->out_regs[5U] = vlTOPp->VX_register_file__DOT__registers
[5U];
vlTOPp->out_regs[4U] = vlTOPp->VX_register_file__DOT__registers
[4U];
vlTOPp->out_regs[3U] = vlTOPp->VX_register_file__DOT__registers
[3U];
vlTOPp->out_regs[2U] = vlTOPp->VX_register_file__DOT__registers
[2U];
vlTOPp->out_regs[1U] = vlTOPp->VX_register_file__DOT__registers
[1U];
vlTOPp->out_regs[0U] = vlTOPp->VX_register_file__DOT__registers
[0U];
}
void VVX_register_file::_settle__TOP__3(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_settle__TOP__3\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_regs[0x1fU] = vlTOPp->VX_register_file__DOT__registers
[0x1fU];
vlTOPp->out_regs[0x1eU] = vlTOPp->VX_register_file__DOT__registers
[0x1eU];
vlTOPp->out_regs[0x1dU] = vlTOPp->VX_register_file__DOT__registers
[0x1dU];
vlTOPp->out_regs[0x1cU] = vlTOPp->VX_register_file__DOT__registers
[0x1cU];
vlTOPp->out_regs[0x1bU] = vlTOPp->VX_register_file__DOT__registers
[0x1bU];
vlTOPp->out_regs[0x1aU] = vlTOPp->VX_register_file__DOT__registers
[0x1aU];
vlTOPp->out_regs[0x19U] = vlTOPp->VX_register_file__DOT__registers
[0x19U];
vlTOPp->out_regs[0x18U] = vlTOPp->VX_register_file__DOT__registers
[0x18U];
vlTOPp->out_regs[0x17U] = vlTOPp->VX_register_file__DOT__registers
[0x17U];
vlTOPp->out_regs[0x16U] = vlTOPp->VX_register_file__DOT__registers
[0x16U];
vlTOPp->out_regs[0x15U] = vlTOPp->VX_register_file__DOT__registers
[0x15U];
vlTOPp->out_regs[0x14U] = vlTOPp->VX_register_file__DOT__registers
[0x14U];
vlTOPp->out_regs[0x13U] = vlTOPp->VX_register_file__DOT__registers
[0x13U];
vlTOPp->out_regs[0x12U] = vlTOPp->VX_register_file__DOT__registers
[0x12U];
vlTOPp->out_regs[0x11U] = vlTOPp->VX_register_file__DOT__registers
[0x11U];
vlTOPp->out_regs[0x10U] = vlTOPp->VX_register_file__DOT__registers
[0x10U];
vlTOPp->out_regs[0xfU] = vlTOPp->VX_register_file__DOT__registers
[0xfU];
vlTOPp->out_regs[0xeU] = vlTOPp->VX_register_file__DOT__registers
[0xeU];
vlTOPp->out_regs[0xdU] = vlTOPp->VX_register_file__DOT__registers
[0xdU];
vlTOPp->out_regs[0xcU] = vlTOPp->VX_register_file__DOT__registers
[0xcU];
vlTOPp->out_regs[0xbU] = vlTOPp->VX_register_file__DOT__registers
[0xbU];
vlTOPp->out_regs[0xaU] = vlTOPp->VX_register_file__DOT__registers
[0xaU];
vlTOPp->out_regs[9U] = vlTOPp->VX_register_file__DOT__registers
[9U];
vlTOPp->out_regs[8U] = vlTOPp->VX_register_file__DOT__registers
[8U];
vlTOPp->out_regs[7U] = vlTOPp->VX_register_file__DOT__registers
[7U];
vlTOPp->out_regs[6U] = vlTOPp->VX_register_file__DOT__registers
[6U];
vlTOPp->out_regs[5U] = vlTOPp->VX_register_file__DOT__registers
[5U];
vlTOPp->out_regs[4U] = vlTOPp->VX_register_file__DOT__registers
[4U];
vlTOPp->out_regs[3U] = vlTOPp->VX_register_file__DOT__registers
[3U];
vlTOPp->out_regs[2U] = vlTOPp->VX_register_file__DOT__registers
[2U];
vlTOPp->out_regs[1U] = vlTOPp->VX_register_file__DOT__registers
[1U];
vlTOPp->out_regs[0U] = vlTOPp->VX_register_file__DOT__registers
[0U];
}
void VVX_register_file::_eval(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) {
vlTOPp->_sequent__TOP__1(vlSymsp);
}
if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
vlTOPp->_sequent__TOP__2(vlSymsp);
}
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_register_file::_eval_initial(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_initial\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_register_file::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::final\n"); );
// Variables
VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp;
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void VVX_register_file::_eval_settle(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_settle\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_settle__TOP__3(vlSymsp);
}
VL_INLINE_OPT QData VVX_register_file::_change_request(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_change_request\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void VVX_register_file::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((clk & 0xfeU))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY((in_valid & 0xfeU))) {
Verilated::overWidthError("in_valid");}
if (VL_UNLIKELY((in_write_register & 0xfeU))) {
Verilated::overWidthError("in_write_register");}
if (VL_UNLIKELY((in_rd & 0xe0U))) {
Verilated::overWidthError("in_rd");}
if (VL_UNLIKELY((in_src1 & 0xe0U))) {
Verilated::overWidthError("in_src1");}
if (VL_UNLIKELY((in_src2 & 0xe0U))) {
Verilated::overWidthError("in_src2");}
}
#endif // VL_DEBUG
void VVX_register_file::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_ctor_var_reset\n"); );
// Body
clk = VL_RAND_RESET_I(1);
in_valid = VL_RAND_RESET_I(1);
in_write_register = VL_RAND_RESET_I(1);
in_rd = VL_RAND_RESET_I(5);
in_data = VL_RAND_RESET_I(32);
in_src1 = VL_RAND_RESET_I(5);
in_src2 = VL_RAND_RESET_I(5);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
out_regs[__Vi0] = VL_RAND_RESET_I(32);
}}
out_src1_data = VL_RAND_RESET_I(32);
out_src2_data = VL_RAND_RESET_I(32);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
VX_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
}}
}

91
rtl/obj_dir/VVX_register_file.h Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_register_file_H_
#define _VVX_register_file_H_
#include "verilated_heavy.h"
class VVX_register_file__Syms;
//----------
VL_MODULE(VVX_register_file) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(in_valid,0,0);
VL_IN8(in_write_register,0,0);
VL_IN8(in_rd,4,0);
VL_IN8(in_src1,4,0);
VL_IN8(in_src2,4,0);
VL_IN(in_data,31,0);
VL_OUT(out_src1_data,31,0);
VL_OUT(out_src2_data,31,0);
VL_OUT(out_regs[32],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG(VX_register_file__DOT__registers[32],31,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vclklast__TOP__clk,0,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_register_file__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_register_file); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_register_file(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_register_file();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_register_file__Syms* symsp, bool first);
private:
static QData _change_request(VVX_register_file__Syms* __restrict vlSymsp);
void _ctor_var_reset();
public:
static void _eval(VVX_register_file__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_register_file__Syms* __restrict vlSymsp);
static void _eval_settle(VVX_register_file__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVX_register_file__Syms* __restrict vlSymsp);
static void _settle__TOP__3(VVX_register_file__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

53
rtl/obj_dir/VVX_register_file.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_register_file.mk
default: VVX_register_file__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_register_file
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_register_file
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include VVX_register_file_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
rtl/obj_dir/VVX_register_file__Syms.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_register_file__Syms.h"
#include "VVX_register_file.h"
// FUNCTIONS
VVX_register_file__Syms::VVX_register_file__Syms(VVX_register_file* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

34
rtl/obj_dir/VVX_register_file__Syms.h Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _VVX_register_file__Syms_H_
#define _VVX_register_file__Syms_H_
#include "verilated_heavy.h"
// INCLUDE MODULE CLASSES
#include "VVX_register_file.h"
// SYMS CLASS
class VVX_register_file__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVX_register_file* TOPp;
// CREATORS
VVX_register_file__Syms(VVX_register_file* topp, const char* namep);
~VVX_register_file__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVX_register_file__ver.d Normal file
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@ -0,0 +1 @@
obj_dir/VVX_register_file.cpp obj_dir/VVX_register_file.h obj_dir/VVX_register_file.mk obj_dir/VVX_register_file__Syms.cpp obj_dir/VVX_register_file__Syms.h obj_dir/VVX_register_file__ver.d obj_dir/VVX_register_file_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_register_file.v

12
rtl/obj_dir/VVX_register_file__verFiles.dat Normal file
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@ -0,0 +1,12 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "VX_register_file.v -cc"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 1075 12889419229 1554007548 0 1554007548 0 "VX_register_file.v"
T 13053 12889437111 1554007562 0 1554007562 0 "obj_dir/VVX_register_file.cpp"
T 3056 12889437110 1554007562 0 1554007562 0 "obj_dir/VVX_register_file.h"
T 1511 12889437113 1554007562 0 1554007562 0 "obj_dir/VVX_register_file.mk"
T 580 12889437109 1554007562 0 1554007562 0 "obj_dir/VVX_register_file__Syms.cpp"
T 787 12889437108 1554007562 0 1554007562 0 "obj_dir/VVX_register_file__Syms.h"
T 356 12889437114 1554007562 0 1554007562 0 "obj_dir/VVX_register_file__ver.d"
T 0 0 1554007562 0 1554007562 0 "obj_dir/VVX_register_file__verFiles.dat"
T 1189 12889437112 1554007562 0 1554007562 0 "obj_dir/VVX_register_file_classes.mk"

38
rtl/obj_dir/VVX_register_file_classes.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_register_file.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_register_file \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_register_file__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

384
rtl/obj_dir/VVX_register_file_slave.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVX_register_file_slave.h for the primary calling header
#include "VVX_register_file_slave.h"
#include "VVX_register_file_slave__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVX_register_file_slave) {
VVX_register_file_slave__Syms* __restrict vlSymsp = __VlSymsp = new VVX_register_file_slave__Syms(this, name());
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVX_register_file_slave::__Vconfigure(VVX_register_file_slave__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVX_register_file_slave::~VVX_register_file_slave() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void VVX_register_file_slave::eval() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_register_file_slave::eval\n"); );
VVX_register_file_slave__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void VVX_register_file_slave::_eval_initial_loop(VVX_register_file_slave__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
//--------------------
// Internal Methods
VL_INLINE_OPT void VVX_register_file_slave::_sequent__TOP__1(VVX_register_file_slave__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_sequent__TOP__1\n"); );
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// ALWAYS at VX_register_file_slave.v:51
vlTOPp->out_src1_data = vlTOPp->VX_register_file_slave__DOT__registers
[vlTOPp->in_src1];
// ALWAYS at VX_register_file_slave.v:51
vlTOPp->out_src2_data = vlTOPp->VX_register_file_slave__DOT__registers
[vlTOPp->in_src2];
}
VL_INLINE_OPT void VVX_register_file_slave::_sequent__TOP__2(VVX_register_file_slave__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_sequent__TOP__2\n"); );
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Variables
// Begin mtask footprint all:
VL_SIG8(__Vdlyvdim0__VX_register_file_slave__DOT__registers__v0,4,0);
VL_SIG8(__Vdlyvset__VX_register_file_slave__DOT__registers__v0,0,0);
VL_SIG8(__Vdlyvset__VX_register_file_slave__DOT__registers__v1,0,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v0,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v1,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v2,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v3,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v4,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v5,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v6,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v7,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v8,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v9,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v10,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v11,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v12,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v13,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v14,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v15,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v16,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v17,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v18,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v19,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v20,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v21,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v22,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v23,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v24,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v25,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v26,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v27,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v28,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v29,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v30,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v31,31,0);
VL_SIG(__Vdlyvval__VX_register_file_slave__DOT__registers__v32,31,0);
// Body
__Vdlyvset__VX_register_file_slave__DOT__registers__v0 = 0U;
__Vdlyvset__VX_register_file_slave__DOT__registers__v1 = 0U;
// ALWAYS at VX_register_file_slave.v:42
if (VL_UNLIKELY(((((IData)(vlTOPp->in_write_register)
& (0U != (IData)(vlTOPp->in_rd)))
& (IData)(vlTOPp->in_valid))
& (~ (IData)(vlTOPp->in_clone))))) {
VL_WRITEF("RF: Writing %x to %2#\n",32,vlTOPp->in_data,
5,(IData)(vlTOPp->in_rd));
__Vdlyvval__VX_register_file_slave__DOT__registers__v0
= vlTOPp->in_data;
__Vdlyvset__VX_register_file_slave__DOT__registers__v0 = 1U;
__Vdlyvdim0__VX_register_file_slave__DOT__registers__v0
= vlTOPp->in_rd;
} else {
if (vlTOPp->in_clone) {
__Vdlyvval__VX_register_file_slave__DOT__registers__v1
= vlTOPp->in_regs[0x1fU];
__Vdlyvset__VX_register_file_slave__DOT__registers__v1 = 1U;
__Vdlyvval__VX_register_file_slave__DOT__registers__v2
= vlTOPp->in_regs[0x1eU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v3
= vlTOPp->in_regs[0x1dU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v4
= vlTOPp->in_regs[0x1cU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v5
= vlTOPp->in_regs[0x1bU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v6
= vlTOPp->in_regs[0x1aU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v7
= vlTOPp->in_regs[0x19U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v8
= vlTOPp->in_regs[0x18U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v9
= vlTOPp->in_regs[0x17U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v10
= vlTOPp->in_regs[0x16U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v11
= vlTOPp->in_regs[0x15U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v12
= vlTOPp->in_regs[0x14U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v13
= vlTOPp->in_regs[0x13U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v14
= vlTOPp->in_regs[0x12U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v15
= vlTOPp->in_regs[0x11U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v16
= vlTOPp->in_regs[0x10U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v17
= vlTOPp->in_regs[0xfU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v18
= vlTOPp->in_regs[0xeU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v19
= vlTOPp->in_regs[0xdU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v20
= vlTOPp->in_regs[0xcU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v21
= vlTOPp->in_regs[0xbU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v22
= vlTOPp->in_regs[0xaU];
__Vdlyvval__VX_register_file_slave__DOT__registers__v23
= vlTOPp->in_regs[9U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v24
= vlTOPp->in_regs[8U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v25
= vlTOPp->in_regs[7U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v26
= vlTOPp->in_regs[6U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v27
= vlTOPp->in_regs[5U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v28
= vlTOPp->in_regs[4U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v29
= vlTOPp->in_regs[3U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v30
= vlTOPp->in_regs[2U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v31
= vlTOPp->in_regs[1U];
__Vdlyvval__VX_register_file_slave__DOT__registers__v32
= vlTOPp->in_regs[0U];
}
}
// ALWAYSPOST at VX_register_file_slave.v:45
if (__Vdlyvset__VX_register_file_slave__DOT__registers__v0) {
vlTOPp->VX_register_file_slave__DOT__registers[__Vdlyvdim0__VX_register_file_slave__DOT__registers__v0]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v0;
}
if (__Vdlyvset__VX_register_file_slave__DOT__registers__v1) {
vlTOPp->VX_register_file_slave__DOT__registers[0x1fU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v1;
vlTOPp->VX_register_file_slave__DOT__registers[0x1eU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v2;
vlTOPp->VX_register_file_slave__DOT__registers[0x1dU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v3;
vlTOPp->VX_register_file_slave__DOT__registers[0x1cU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v4;
vlTOPp->VX_register_file_slave__DOT__registers[0x1bU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v5;
vlTOPp->VX_register_file_slave__DOT__registers[0x1aU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v6;
vlTOPp->VX_register_file_slave__DOT__registers[0x19U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v7;
vlTOPp->VX_register_file_slave__DOT__registers[0x18U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v8;
vlTOPp->VX_register_file_slave__DOT__registers[0x17U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v9;
vlTOPp->VX_register_file_slave__DOT__registers[0x16U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v10;
vlTOPp->VX_register_file_slave__DOT__registers[0x15U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v11;
vlTOPp->VX_register_file_slave__DOT__registers[0x14U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v12;
vlTOPp->VX_register_file_slave__DOT__registers[0x13U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v13;
vlTOPp->VX_register_file_slave__DOT__registers[0x12U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v14;
vlTOPp->VX_register_file_slave__DOT__registers[0x11U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v15;
vlTOPp->VX_register_file_slave__DOT__registers[0x10U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v16;
vlTOPp->VX_register_file_slave__DOT__registers[0xfU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v17;
vlTOPp->VX_register_file_slave__DOT__registers[0xeU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v18;
vlTOPp->VX_register_file_slave__DOT__registers[0xdU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v19;
vlTOPp->VX_register_file_slave__DOT__registers[0xcU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v20;
vlTOPp->VX_register_file_slave__DOT__registers[0xbU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v21;
vlTOPp->VX_register_file_slave__DOT__registers[0xaU]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v22;
vlTOPp->VX_register_file_slave__DOT__registers[9U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v23;
vlTOPp->VX_register_file_slave__DOT__registers[8U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v24;
vlTOPp->VX_register_file_slave__DOT__registers[7U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v25;
vlTOPp->VX_register_file_slave__DOT__registers[6U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v26;
vlTOPp->VX_register_file_slave__DOT__registers[5U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v27;
vlTOPp->VX_register_file_slave__DOT__registers[4U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v28;
vlTOPp->VX_register_file_slave__DOT__registers[3U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v29;
vlTOPp->VX_register_file_slave__DOT__registers[2U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v30;
vlTOPp->VX_register_file_slave__DOT__registers[1U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v31;
vlTOPp->VX_register_file_slave__DOT__registers[0U]
= __Vdlyvval__VX_register_file_slave__DOT__registers__v32;
}
}
void VVX_register_file_slave::_eval(VVX_register_file_slave__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_eval\n"); );
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) {
vlTOPp->_sequent__TOP__1(vlSymsp);
}
if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
vlTOPp->_sequent__TOP__2(vlSymsp);
}
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_register_file_slave::_eval_initial(VVX_register_file_slave__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_eval_initial\n"); );
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_register_file_slave::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::final\n"); );
// Variables
VVX_register_file_slave__Syms* __restrict vlSymsp = this->__VlSymsp;
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void VVX_register_file_slave::_eval_settle(VVX_register_file_slave__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_eval_settle\n"); );
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
VL_INLINE_OPT QData VVX_register_file_slave::_change_request(VVX_register_file_slave__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_change_request\n"); );
VVX_register_file_slave* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void VVX_register_file_slave::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((clk & 0xfeU))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY((in_valid & 0xfeU))) {
Verilated::overWidthError("in_valid");}
if (VL_UNLIKELY((in_write_register & 0xfeU))) {
Verilated::overWidthError("in_write_register");}
if (VL_UNLIKELY((in_rd & 0xe0U))) {
Verilated::overWidthError("in_rd");}
if (VL_UNLIKELY((in_src1 & 0xe0U))) {
Verilated::overWidthError("in_src1");}
if (VL_UNLIKELY((in_src2 & 0xe0U))) {
Verilated::overWidthError("in_src2");}
if (VL_UNLIKELY((in_clone & 0xfeU))) {
Verilated::overWidthError("in_clone");}
}
#endif // VL_DEBUG
void VVX_register_file_slave::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file_slave::_ctor_var_reset\n"); );
// Body
clk = VL_RAND_RESET_I(1);
in_valid = VL_RAND_RESET_I(1);
in_write_register = VL_RAND_RESET_I(1);
in_rd = VL_RAND_RESET_I(5);
in_data = VL_RAND_RESET_I(32);
in_src1 = VL_RAND_RESET_I(5);
in_src2 = VL_RAND_RESET_I(5);
in_clone = VL_RAND_RESET_I(1);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
in_regs[__Vi0] = VL_RAND_RESET_I(32);
}}
out_src1_data = VL_RAND_RESET_I(32);
out_src2_data = VL_RAND_RESET_I(32);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
VX_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
}}
}

91
rtl/obj_dir/VVX_register_file_slave.h Normal file
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@ -0,0 +1,91 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_register_file_slave_H_
#define _VVX_register_file_slave_H_
#include "verilated_heavy.h"
class VVX_register_file_slave__Syms;
//----------
VL_MODULE(VVX_register_file_slave) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(in_valid,0,0);
VL_IN8(in_write_register,0,0);
VL_IN8(in_rd,4,0);
VL_IN8(in_src1,4,0);
VL_IN8(in_src2,4,0);
VL_IN8(in_clone,0,0);
VL_IN(in_data,31,0);
VL_OUT(out_src1_data,31,0);
VL_OUT(out_src2_data,31,0);
VL_IN(in_regs[32],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG(VX_register_file_slave__DOT__registers[32],31,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vclklast__TOP__clk,0,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_register_file_slave__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_register_file_slave); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_register_file_slave(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_register_file_slave();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_register_file_slave__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_register_file_slave__Syms* symsp, bool first);
private:
static QData _change_request(VVX_register_file_slave__Syms* __restrict vlSymsp);
void _ctor_var_reset();
public:
static void _eval(VVX_register_file_slave__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_register_file_slave__Syms* __restrict vlSymsp);
static void _eval_settle(VVX_register_file_slave__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVX_register_file_slave__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVX_register_file_slave__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

53
rtl/obj_dir/VVX_register_file_slave.mk Normal file
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@ -0,0 +1,53 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_register_file_slave.mk
default: VVX_register_file_slave__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_register_file_slave
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_register_file_slave
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include VVX_register_file_slave_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
rtl/obj_dir/VVX_register_file_slave__Syms.cpp Normal file
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@ -0,0 +1,19 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_register_file_slave__Syms.h"
#include "VVX_register_file_slave.h"
// FUNCTIONS
VVX_register_file_slave__Syms::VVX_register_file_slave__Syms(VVX_register_file_slave* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

34
rtl/obj_dir/VVX_register_file_slave__Syms.h Normal file
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@ -0,0 +1,34 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _VVX_register_file_slave__Syms_H_
#define _VVX_register_file_slave__Syms_H_
#include "verilated_heavy.h"
// INCLUDE MODULE CLASSES
#include "VVX_register_file_slave.h"
// SYMS CLASS
class VVX_register_file_slave__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVX_register_file_slave* TOPp;
// CREATORS
VVX_register_file_slave__Syms(VVX_register_file_slave* topp, const char* namep);
~VVX_register_file_slave__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVX_register_file_slave__ver.d Normal file
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@ -0,0 +1 @@
obj_dir/VVX_register_file_slave.cpp obj_dir/VVX_register_file_slave.h obj_dir/VVX_register_file_slave.mk obj_dir/VVX_register_file_slave__Syms.cpp obj_dir/VVX_register_file_slave__Syms.h obj_dir/VVX_register_file_slave__ver.d obj_dir/VVX_register_file_slave_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_register_file_slave.v

12
rtl/obj_dir/VVX_register_file_slave__verFiles.dat Normal file
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@ -0,0 +1,12 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "VX_register_file_slave.v -cc"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 1160 12889437241 1554007811 0 1554007811 0 "VX_register_file_slave.v"
T 17581 12889437306 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave.cpp"
T 3104 12889437305 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave.h"
T 1541 12889437308 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave.mk"
T 610 12889437304 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave__Syms.cpp"
T 829 12889437303 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave__Syms.h"
T 404 12889437310 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave__ver.d"
T 0 0 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave__verFiles.dat"
T 1207 12889437307 1554007815 0 1554007815 0 "obj_dir/VVX_register_file_slave_classes.mk"

38
rtl/obj_dir/VVX_register_file_slave_classes.mk Normal file
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@ -0,0 +1,38 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_register_file_slave.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_register_file_slave \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_register_file_slave__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

BIN
rtl/obj_dir/VVortex
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4831
rtl/obj_dir/VVortex.cpp
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65
rtl/obj_dir/VVortex.h
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@ -37,7 +37,11 @@ VL_MODULE(VVortex) {
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(Vortex__DOT__decode_branch_stall,0,0);
VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
VL_SIG8(Vortex__DOT__decode_jal,0,0);
VL_SIG8(Vortex__DOT__decode_clone_stall,0,0);
VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
@ -48,10 +52,14 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__to_clone_1,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
@ -84,6 +92,7 @@ VL_MODULE(VVortex) {
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
VL_SIG(Vortex__DOT__decode_jal_offset,31,0);
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__old,31,0);
@ -92,6 +101,8 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_fetch__DOT__BR_reg,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__PC_to_use,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__temp_PC,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
@ -101,8 +112,6 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
@ -125,6 +134,7 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__decode_a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__decode_b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__decode_valid[5],0,0);
VL_SIG8(Vortex__DOT__decode_thread_mask[5],0,0);
VL_SIG(Vortex__DOT__d_e_a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__d_e_b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[5],0,0);
@ -143,19 +153,22 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__writeback_write_data[5],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[5],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[5],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid[5],0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__4__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__clone_regsiters[32],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[5],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[5],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[5],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[5],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[5],0,0);
};
struct {
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[5],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[5],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[5],31,0);
@ -167,8 +180,6 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[5],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[5],31,0);
};
struct {
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
@ -178,26 +189,25 @@ VL_MODULE(VVortex) {
struct {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5,0,0);
VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v6,0,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__4__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[5],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[5],31,0);
@ -241,9 +251,9 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[5],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[5],0,0);
};
struct {
VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[5],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[5],31,0);
@ -253,6 +263,8 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[5],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[5],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__vx_register_file_slave__in_regs[32],31,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
@ -288,8 +300,8 @@ VL_MODULE(VVortex) {
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__5(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
@ -302,12 +314,13 @@ VL_MODULE(VVortex) {
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _multiclk__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__9(VVortex__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

BIN
rtl/obj_dir/VVortex__ALL.a
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BIN
rtl/obj_dir/VVortex__ALLcls.o
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2
rtl/obj_dir/VVortex__ver.d
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@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_writeback.v Vortex.v

33
rtl/obj_dir/VVortex__verFiles.dat
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@ -1,26 +1,27 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
C "-Wall -cc Vortex.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2862 12889318286 1553966962 0 1553966962 0 "VX_alu.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 5040 12889318287 1553995422 0 1553995422 0 "VX_d_e_reg.v"
S 11230 12889419225 1554000860 0 1554000860 0 "VX_decode.v"
S 1532 12889419227 1553998396 0 1553998396 0 "VX_define.v"
S 5105 12889318287 1554013046 0 1554013046 0 "VX_d_e_reg.v"
S 15001 12889419225 1554022101 0 1554022101 0 "VX_decode.v"
S 1557 12889419227 1554008503 0 1554008503 0 "VX_define.v"
S 4077 12889318289 1553997299 0 1553997299 0 "VX_e_m_reg.v"
S 3288 12889318290 1554000824 0 1554000824 0 "VX_execute.v"
S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v"
S 4020 12889419228 1554000776 0 1554000776 0 "VX_fetch.v"
S 1540 12889050060 1554018831 0 1554018831 0 "VX_f_d_reg.v"
S 4588 12889419228 1554021543 0 1554021543 0 "VX_fetch.v"
S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 3002 12889084513 1553997670 0 1553997670 0 "VX_memory.v"
S 1003 12889419229 1553930745 0 1553930745 0 "VX_register_file.v"
S 1075 12889419229 1554007548 0 1554007548 0 "VX_register_file.v"
S 1381 12889437241 1554016243 0 1554016243 0 "VX_register_file_slave.v"
S 1173 12889419230 1553930874 0 1553930874 0 "VX_writeback.v"
S 16452 12889419231 1553997933 0 1553997933 0 "Vortex.v"
T 347293 12889432530 1554000904 0 1554000904 0 "obj_dir/VVortex.cpp"
T 17090 12889432529 1554000904 0 1554000904 0 "obj_dir/VVortex.h"
T 1800 12889432532 1554000904 0 1554000904 0 "obj_dir/VVortex.mk"
T 530 12889432528 1554000904 0 1554000904 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889432527 1554000904 0 1554000904 0 "obj_dir/VVortex__Syms.h"
T 464 12889432533 1554000904 0 1554000904 0 "obj_dir/VVortex__ver.d"
T 0 0 1554000904 0 1554000904 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889432531 1554000904 0 1554000904 0 "obj_dir/VVortex_classes.mk"
S 16910 12889419231 1554021042 0 1554021042 0 "Vortex.v"
T 416263 12889432530 1554022103 0 1554022103 0 "obj_dir/VVortex.cpp"
T 17158 12889432529 1554022103 0 1554022103 0 "obj_dir/VVortex.h"
T 1800 12889432532 1554022103 0 1554022103 0 "obj_dir/VVortex.mk"
T 530 12889432528 1554022103 0 1554022103 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889432527 1554022103 0 1554022103 0 "obj_dir/VVortex__Syms.h"
T 489 12889432533 1554022103 0 1554022103 0 "obj_dir/VVortex__ver.d"
T 0 0 1554022103 0 1554022103 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889432531 1554022103 0 1554022103 0 "obj_dir/VVortex_classes.mk"

114881
rtl/obj_dir/debug.txt
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rtl/obj_dir/test_bench.o
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415
rtl/results.txt
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@ -1,414 +1,9 @@
**************** ../../emulator/riscv_tests/rv32ui-p-add.hex ****************
# Dynamic Instructions: 597
# of total cycles: 608
**************** ../../kernel/vortex_test.hex ****************
# Dynamic Instructions: 482804
# of total cycles: 482816
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01843
# CPI: 1.00002
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-addi.hex ****************
# Dynamic Instructions: 312
# of total cycles: 323
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03526
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-and.hex ****************
# Dynamic Instructions: 595
# of total cycles: 606
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01849
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-andi.hex ****************
# Dynamic Instructions: 246
# of total cycles: 257
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04472
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-auipc.hex ****************
# Dynamic Instructions: 65
# of total cycles: 76
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.16923
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-beq.hex ****************
# Dynamic Instructions: 431
# of total cycles: 442
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bge.hex ****************
# Dynamic Instructions: 467
# of total cycles: 478
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02355
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bgeu.hex ****************
# Dynamic Instructions: 492
# of total cycles: 503
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02236
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-blt.hex ****************
# Dynamic Instructions: 431
# of total cycles: 442
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bltu.hex ****************
# Dynamic Instructions: 456
# of total cycles: 467
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02412
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-bne.hex ****************
# Dynamic Instructions: 431
# of total cycles: 442
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.02552
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-jal.hex ****************
# Dynamic Instructions: 61
# of total cycles: 72
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.18033
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-jalr.hex ****************
# Dynamic Instructions: 138
# of total cycles: 149
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.07971
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lb.hex ****************
# Dynamic Instructions: 331
# of total cycles: 342
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03323
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lbu.hex ****************
# Dynamic Instructions: 331
# of total cycles: 342
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03323
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lh.hex ****************
# Dynamic Instructions: 339
# of total cycles: 350
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03245
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lhu.hex ****************
# Dynamic Instructions: 343
# of total cycles: 354
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03207
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lui.hex ****************
# Dynamic Instructions: 73
# of total cycles: 84
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.15068
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-lw.hex ****************
# Dynamic Instructions: 346
# of total cycles: 357
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03179
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-or.hex ****************
# Dynamic Instructions: 598
# of total cycles: 609
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01839
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-ori.hex ****************
# Dynamic Instructions: 253
# of total cycles: 264
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04348
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sb.hex ****************
# Dynamic Instructions: 571
# of total cycles: 582
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01926
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sh.hex ****************
# Dynamic Instructions: 603
# of total cycles: 614
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01824
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-simple.hex ****************
# Dynamic Instructions: 37
# of total cycles: 48
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.2973
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sll.hex ****************
# Dynamic Instructions: 633
# of total cycles: 644
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01738
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slli.hex ****************
# Dynamic Instructions: 311
# of total cycles: 322
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03537
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slt.hex ****************
# Dynamic Instructions: 591
# of total cycles: 602
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01861
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-slti.hex ****************
# Dynamic Instructions: 307
# of total cycles: 318
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03583
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sltiu.hex ****************
# Dynamic Instructions: 307
# of total cycles: 318
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03583
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sltu.hex ****************
# Dynamic Instructions: 591
# of total cycles: 602
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01861
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sra.hex ****************
# Dynamic Instructions: 654
# of total cycles: 665
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01682
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srai.hex ****************
# Dynamic Instructions: 326
# of total cycles: 337
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03374
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srl.hex ****************
# Dynamic Instructions: 648
# of total cycles: 659
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01698
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-srli.hex ****************
# Dynamic Instructions: 320
# of total cycles: 331
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.03438
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex ****************
# Dynamic Instructions: 587
# of total cycles: 598
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01874
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-sw.hex ****************
# Dynamic Instructions: 612
# of total cycles: 623
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01797
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-xor.hex ****************
# Dynamic Instructions: 597
# of total cycles: 608
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01843
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32ui-p-xori.hex ****************
# Dynamic Instructions: 255
# of total cycles: 266
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.04314
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-div.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-divu.hex ****************
# Dynamic Instructions: 113
# of total cycles: 124
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09735
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mul.hex ****************
# Dynamic Instructions: 589
# of total cycles: 600
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01868
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulh.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulhsu.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-mulhu.hex ****************
# Dynamic Instructions: 585
# of total cycles: 596
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0188
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-rem.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
**************** ../../emulator/riscv_tests/rv32um-p-remu.hex ****************
# Dynamic Instructions: 112
# of total cycles: 123
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.09821
# time to simulate: 6.95312e-310 milliseconds
# GRADE: PASSING
# GRADE: Failed on test: 0

127
rtl/test_bench.cpp
View file

@ -12,77 +12,78 @@ int main(int argc, char **argv)
Vortex v;
bool passed = true;
std::string tests[NUM_TESTS] = {
"../../emulator/riscv_tests/rv32ui-p-add.hex",
"../../emulator/riscv_tests/rv32ui-p-addi.hex",
"../../emulator/riscv_tests/rv32ui-p-and.hex",
"../../emulator/riscv_tests/rv32ui-p-andi.hex",
"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
"../../emulator/riscv_tests/rv32ui-p-beq.hex",
"../../emulator/riscv_tests/rv32ui-p-bge.hex",
"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
"../../emulator/riscv_tests/rv32ui-p-blt.hex",
"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
"../../emulator/riscv_tests/rv32ui-p-bne.hex",
"../../emulator/riscv_tests/rv32ui-p-jal.hex",
"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
"../../emulator/riscv_tests/rv32ui-p-lb.hex",
"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
"../../emulator/riscv_tests/rv32ui-p-lh.hex",
"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
"../../emulator/riscv_tests/rv32ui-p-lui.hex",
"../../emulator/riscv_tests/rv32ui-p-lw.hex",
"../../emulator/riscv_tests/rv32ui-p-or.hex",
"../../emulator/riscv_tests/rv32ui-p-ori.hex",
"../../emulator/riscv_tests/rv32ui-p-sb.hex",
"../../emulator/riscv_tests/rv32ui-p-sh.hex",
"../../emulator/riscv_tests/rv32ui-p-simple.hex",
"../../emulator/riscv_tests/rv32ui-p-sll.hex",
"../../emulator/riscv_tests/rv32ui-p-slli.hex",
"../../emulator/riscv_tests/rv32ui-p-slt.hex",
"../../emulator/riscv_tests/rv32ui-p-slti.hex",
"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
"../../emulator/riscv_tests/rv32ui-p-sra.hex",
"../../emulator/riscv_tests/rv32ui-p-srai.hex",
"../../emulator/riscv_tests/rv32ui-p-srl.hex",
"../../emulator/riscv_tests/rv32ui-p-srli.hex",
"../../emulator/riscv_tests/rv32ui-p-sub.hex",
"../../emulator/riscv_tests/rv32ui-p-sw.hex",
"../../emulator/riscv_tests/rv32ui-p-xor.hex",
"../../emulator/riscv_tests/rv32ui-p-xori.hex",
"../../emulator/riscv_tests/rv32um-p-div.hex",
"../../emulator/riscv_tests/rv32um-p-divu.hex",
"../../emulator/riscv_tests/rv32um-p-mul.hex",
"../../emulator/riscv_tests/rv32um-p-mulh.hex",
"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
"../../emulator/riscv_tests/rv32um-p-rem.hex",
"../../emulator/riscv_tests/rv32um-p-remu.hex"
};
// bool passed = true;
// std::string tests[NUM_TESTS] = {
// "../../emulator/riscv_tests/rv32ui-p-add.hex",
// "../../emulator/riscv_tests/rv32ui-p-addi.hex",
// "../../emulator/riscv_tests/rv32ui-p-and.hex",
// "../../emulator/riscv_tests/rv32ui-p-andi.hex",
// "../../emulator/riscv_tests/rv32ui-p-auipc.hex",
// "../../emulator/riscv_tests/rv32ui-p-beq.hex",
// "../../emulator/riscv_tests/rv32ui-p-bge.hex",
// "../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
// "../../emulator/riscv_tests/rv32ui-p-blt.hex",
// "../../emulator/riscv_tests/rv32ui-p-bltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-bne.hex",
// "../../emulator/riscv_tests/rv32ui-p-jal.hex",
// "../../emulator/riscv_tests/rv32ui-p-jalr.hex",
// "../../emulator/riscv_tests/rv32ui-p-lb.hex",
// "../../emulator/riscv_tests/rv32ui-p-lbu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lh.hex",
// "../../emulator/riscv_tests/rv32ui-p-lhu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lui.hex",
// "../../emulator/riscv_tests/rv32ui-p-lw.hex",
// "../../emulator/riscv_tests/rv32ui-p-or.hex",
// "../../emulator/riscv_tests/rv32ui-p-ori.hex",
// "../../emulator/riscv_tests/rv32ui-p-sb.hex",
// "../../emulator/riscv_tests/rv32ui-p-sh.hex",
// "../../emulator/riscv_tests/rv32ui-p-simple.hex",
// "../../emulator/riscv_tests/rv32ui-p-sll.hex",
// "../../emulator/riscv_tests/rv32ui-p-slli.hex",
// "../../emulator/riscv_tests/rv32ui-p-slt.hex",
// "../../emulator/riscv_tests/rv32ui-p-slti.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sra.hex",
// "../../emulator/riscv_tests/rv32ui-p-srai.hex",
// "../../emulator/riscv_tests/rv32ui-p-srl.hex",
// "../../emulator/riscv_tests/rv32ui-p-srli.hex",
// "../../emulator/riscv_tests/rv32ui-p-sub.hex",
// "../../emulator/riscv_tests/rv32ui-p-sw.hex",
// "../../emulator/riscv_tests/rv32ui-p-xor.hex",
// "../../emulator/riscv_tests/rv32ui-p-xori.hex",
// "../../emulator/riscv_tests/rv32um-p-div.hex",
// "../../emulator/riscv_tests/rv32um-p-divu.hex",
// "../../emulator/riscv_tests/rv32um-p-mul.hex",
// "../../emulator/riscv_tests/rv32um-p-mulh.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhu.hex",
// "../../emulator/riscv_tests/rv32um-p-rem.hex",
// "../../emulator/riscv_tests/rv32um-p-remu.hex"
// };
for (int ii = 0; ii < NUM_TESTS; ii++)
// for (int ii = 0; ii < NUM_TESTS - 1; ii++)
{
bool curr = v.simulate(tests[ii]);
// for (int ii = 0; ii < NUM_TESTS; ii++)
// // for (int ii = 0; ii < NUM_TESTS - 1; ii++)
// {
// bool curr = v.simulate(tests[ii]);
if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
passed = passed && curr;
// if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
// passed = passed && curr;
std::cerr << DEFAULT;
}
// std::cerr << DEFAULT;
// }
if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
// if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
char testing[] = "../../kernel/vortex_test.hex";
// bool curr = v.simulate(testing);
// if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return 0;

11
rtl/test_bench.h
View file

@ -142,7 +142,7 @@ bool Vortex::ibus_driver()
ram.getWord(new_PC, &curr_inst);
vortex->fe_instruction = curr_inst;
// printf("\n\n(%x) Inst: %x\n", new_PC, curr_inst);
printf("\n\n---------------------------------------------\n(%x) Inst: %x\n", new_PC, curr_inst);
printf("\n");
////////////////////// IBUS //////////////////////
@ -182,6 +182,11 @@ bool Vortex::dbus_driver()
data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
if (addr == 0x00010000)
{
std::cerr << (char) data_write;
}
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
{
data_write = ( data_write) & 0xFF;
@ -206,7 +211,7 @@ bool Vortex::dbus_driver()
printf("----\n");
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
{
@ -328,7 +333,7 @@ bool Vortex::simulate(std::string file_to_simulate)
// std::cout << "************* Cycle: " << cycle << "\n";
istop = ibus_driver();
dstop = !dbus_driver();
// dstop = !dbus_driver();
vortex->clk = 1;
vortex->eval();