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minor update

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This commit is contained in:
Blaise Tine 2021-09-29 09:32:21 -07:00
parent bbcb50ba81
commit 8e82ee00a0
7 changed files with 15 additions and 8 deletions
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2
hw/rtl/VX_lsu_unit.sv
View file

@ -303,7 +303,7 @@ module VX_lsu_unit #(
`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
`ifndef __SYNTHESIS__
`ifndef SYNTHESIS
reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs;
wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));

8
hw/rtl/VX_platform.vh
View file

@ -1,7 +1,7 @@
`ifndef VX_PLATFORM
`define VX_PLATFORM
`ifndef __SYNTHESIS__
`ifndef SYNTHESIS
`include "util_dpi.vh"
`endif
@ -9,7 +9,7 @@
///////////////////////////////////////////////////////////////////////////////
`ifndef __SYNTHESIS__
`ifndef SYNTHESIS
`ifndef NDEBUG
`define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
@ -70,7 +70,7 @@
`define TRACING_ON /* verilator tracing_on */
`define TRACING_OFF /* verilator tracing_off */
`else // __SYNTHESIS__
`else // SYNTHESIS
`define DEBUG_BLOCK(x)
`define IGNORE_UNUSED_BEGIN
@ -87,7 +87,7 @@
`define TRACING_ON
`define TRACING_OFF
`endif // __SYNTHESIS__
`endif // SYNTHESIS
///////////////////////////////////////////////////////////////////////////////

2
hw/rtl/libs/VX_dp_ram.sv
View file

@ -34,7 +34,7 @@ module VX_dp_ram #(
end \
end
`ifdef __SYNTHESIS__
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;

2
hw/rtl/libs/VX_sp_ram.sv
View file

@ -33,7 +33,7 @@ module VX_sp_ram #(
end \
end
`ifdef __SYNTHESIS__
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;

1
hw/syn/opae/vortex_afu.qsf
View file

@ -5,6 +5,7 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON

7
hw/syn/quartus/Makefile
View file

@ -1,6 +1,11 @@
BUILD_DIR ?= build
.PHONY: unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64
.PHONY: dogfood unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64
dogfood:
mkdir -p dogfood/$(BUILD_DIR)
cp dogfood/Makefile dogfood/$(BUILD_DIR)
$(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 &
unittest:
mkdir -p unittest/$(BUILD_DIR)

1
hw/syn/quartus/project.tcl
View file

@ -36,6 +36,7 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON