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fixed synthesis warning

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Blaise Tine 2024-08-12 05:24:46 -07:00
parent ed66ee2806
commit 9053919e92
1 changed files with 1 additions and 1 deletions
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hw/rtl/libs/VX_rr_arbiter.sv
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@ -451,7 +451,7 @@ module VX_rr_arbiter #(
end else if (MODEL == 2) begin
reg [LOG_NUM_REQS-1:0] grant_table [NUM_REQS-1:0];
reg [NUM_REQS-1:0][LOG_NUM_REQS-1:0] grant_table;
reg [LOG_NUM_REQS-1:0] state;
for (genvar i = 0; i < NUM_REQS; ++i) begin