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issue pipeline synthesis test

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Blaise Tine 2024-07-17 20:34:44 -07:00
parent 068ec6c5ef
commit 9a018014ff
2 changed files with 15 additions and 0 deletions
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5
hw/syn/altera/quartus/Makefile
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@ -50,6 +50,11 @@ core:
cp core/Makefile core/$(BUILD_DIR)
$(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 &
issue:
mkdir -p issue/$(BUILD_DIR)
cp issue/Makefile issue/$(BUILD_DIR)
$(MAKE) -C issue/$(BUILD_DIR) clean && $(MAKE) -C issue/$(BUILD_DIR) > issue/$(BUILD_DIR)/build.log 2>&1 &
vortex: ip-gen
mkdir -p vortex/$(BUILD_DIR)
cp vortex/Makefile vortex/$(BUILD_DIR)

10
hw/syn/altera/quartus/issue/Makefile Normal file
View file

@ -0,0 +1,10 @@
PROJECT = VX_issue_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
#CONFIGS += -DNUM_WARPS=32
#CONFIGS += -DNUM_THREADS=32
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem $(FPU_INCLUDE)