riscv-tests update

miscs/patches/riscv-test-env.patch

@@ -1,40 +1,23 @@
 diff --git a/encoding.h b/encoding.h
-index 01889d1..672f753 100644
+index 01889d1..362ebd8 100644
 --- a/encoding.h
 +++ b/encoding.h
-@@ -231,6 +231,30 @@
+@@ -231,6 +231,13 @@
  #define MSECCFG_USEED  0x00000100
  #define MSECCFG_SSEED  0x00000200
  
++// Vortex defines
 +#define RISCV_CUSTOM0 0x0B
-+
-+#if __riscv_xlen == 64
-+#define VX_IO_BASE_ADDR (0x1fff00000)
-+#else
-+#define VX_IO_BASE_ADDR (0xfff00000)
-+#endif
-+
-+#define VX_IO_COUT_ADDR VX_IO_BASE_ADDR
++#define VX_IO_COUT_ADDR 0x40
 +#define VX_IO_COUT_SIZE 64
 +#define VX_IO_MPM_ADDR (VX_IO_COUT_ADDR + VX_IO_COUT_SIZE)
 +#define VX_IO_MPM_EXITCODE (VX_IO_MPM_ADDR + 8)
-+
-+#if __riscv_xlen == 64
-+  #define LOAD_IMMEDIATE(rd, imm) \
-+    li   t0, (imm >> 32); \
-+    slli t0, t0, 32; \
-+    li   rd, (imm & 0xffffffff); \
-+    or   rd, rd, t0
-+#else
-+  #define LOAD_IMMEDIATE(rd, imm) \
-+    li rd, imm
-+#endif
 +
  /* jvt fields */
  #define JVT_MODE   0x3F
  #define JVT_BASE   (~0x3F)
 diff --git a/p/riscv_test.h b/p/riscv_test.h
-index 7bf35cf..d370887 100644
+index 7bf35cf..6dc759f 100644
 --- a/p/riscv_test.h
 +++ b/p/riscv_test.h
 @@ -174,6 +174,13 @@
@@ -44,8 +27,8 @@ index 7bf35cf..d370887 100644
 +        .globl exit;                                                    \
 +        .align 2;                                                       \
 +exit:                                                                   \
-+        LOAD_IMMEDIATE(t1, VX_IO_MPM_EXITCODE);                         \
-+        sw a0, 0(t1);                                                   \
++        li t0, VX_IO_MPM_EXITCODE;                                      \
++        sw a0, 0(t0);                                                   \
 +        fence;                                                          \
 +        .insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0;                        \
          .align 2;                                                       \
@@ -77,7 +60,7 @@ index 7bf35cf..d370887 100644
  //-----------------------------------------------------------------------
  // Data Section Macro
 diff --git a/v/entry.S b/v/entry.S
-index 13d46a3..f8975a9 100644
+index 13d46a3..39a6c34 100644
 --- a/v/entry.S
 +++ b/v/entry.S
 @@ -17,8 +17,14 @@
@@ -89,8 +72,8 @@ index 13d46a3..f8975a9 100644
 +  .globl exit
 +  .align 2
 +exit:
-+  LOAD_IMMEDIATE(t1, VX_IO_MPM_EXITCODE)
-+  sw a0, 0(t1)
++  li t0, VX_IO_MPM_EXITCODE
++  sw a0, 0(t0)
 +  fence
 +  .insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0
 +/* NMI vector */

miscs/patches/riscv-tests.patch

@@ -95,7 +95,7 @@ index fde4f23..317fd77 100644
  install-link:
  	rm -rf $(instbasedir)/$(instname)
 diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
-index 3f5bb2c..4223544 100644
+index 3f5bb2c..811412c 100644
 --- a/benchmarks/common/crt.S
 +++ b/benchmarks/common/crt.S
 @@ -134,7 +134,22 @@ _start:
@@ -106,14 +106,14 @@ index 3f5bb2c..4223544 100644
 +  .align 2
 +  .globl exit
 +exit:
-+  LOAD_IMMEDIATE(t1, VX_IO_MPM_EXITCODE)
-+  sw a0, 0(t1)
++  li t0, VX_IO_MPM_EXITCODE
++  sw a0, 0(t0)
 +  fence
 +  .insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0
 +  .align 2
 +  .globl putchar
 +putchar:
-+  LOAD_IMMEDIATE(t1, VX_IO_COUT_ADDR)
++  li t1, VX_IO_COUT_ADDR
 +  csrr t0, CSR_MHARTID
 +  andi t0, t0, %lo(VX_IO_COUT_SIZE-1)
 +  add t0, t0, t1