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code refactoring for Vivado compatibility

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This commit is contained in:
Blaise Tine 2021-09-29 03:24:17 -04:00
parent 18c1dc2f0e
commit a45261b530
31 changed files with 133 additions and 110 deletions
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22
hw/rtl/VX_cluster.v
View file

@ -12,16 +12,16 @@ module VX_cluster #(
// Memory request
output wire mem_req_valid,
output wire mem_req_rw,
output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag,
output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// Memory response
input wire mem_rsp_valid,
input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
// Status
@ -34,12 +34,12 @@ module VX_cluster #(
wire [`NUM_CORES-1:0][`DCACHE_MEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen;
wire [`NUM_CORES-1:0][`DCACHE_MEM_ADDR_WIDTH-1:0] per_core_mem_req_addr;
wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_req_data;
wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_req_tag;
wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_req_tag;
wire [`NUM_CORES-1:0] per_core_mem_req_ready;
wire [`NUM_CORES-1:0] per_core_mem_rsp_valid;
wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_rsp_data;
wire [`NUM_CORES-1:0][`XMEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag;
wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag;
wire [`NUM_CORES-1:0] per_core_mem_rsp_ready;
wire [`NUM_CORES-1:0] per_core_busy;
@ -69,7 +69,7 @@ module VX_cluster #(
.mem_rsp_tag (per_core_mem_rsp_tag [i]),
.mem_rsp_ready (per_core_mem_rsp_ready[i]),
.busy (per_core_busy [i])
.busy (per_core_busy [i])
);
end
@ -96,7 +96,7 @@ module VX_cluster #(
.MRSQ_SIZE (`L2_MRSQ_SIZE),
.MREQ_SIZE (`L2_MREQ_SIZE),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`XMEM_TAG_WIDTH),
.CORE_TAG_WIDTH (`L1_MEM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.MEM_TAG_WIDTH (`L2_MEM_TAG_WIDTH),
.NC_ENABLE (1)
@ -150,7 +150,7 @@ module VX_cluster #(
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH),
.ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`XMEM_TAG_WIDTH),
.TAG_IN_WIDTH (`L1_MEM_TAG_WIDTH),
.TYPE ("R"),
.TAG_SEL_IDX (1), // Skip 0 for NC flag
.BUFFERED_REQ (1),

16
hw/rtl/VX_core.v
View file

@ -12,16 +12,16 @@ module VX_core #(
// Memory request
output wire mem_req_valid,
output wire mem_req_rw,
output wire [`DCACHE_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`DCACHE_MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`XMEM_TAG_WIDTH-1:0] mem_req_tag,
output wire [`DCACHE_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
output wire [`DCACHE_MEM_ADDR_WIDTH-1:0] mem_req_addr,
output wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_req_data,
output wire [`L1_MEM_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_ready,
// Memory reponse
input wire mem_rsp_valid,
input wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`XMEM_TAG_WIDTH-1:0] mem_rsp_tag,
input wire [`DCACHE_MEM_DATA_WIDTH-1:0] mem_rsp_data,
input wire [`L1_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_rsp_ready,
// Status
@ -34,12 +34,12 @@ module VX_core #(
VX_mem_req_if #(
.DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH),
.ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH),
.TAG_WIDTH (`XMEM_TAG_WIDTH)
.TAG_WIDTH (`L1_MEM_TAG_WIDTH)
) mem_req_if();
VX_mem_rsp_if #(
.DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH),
.TAG_WIDTH (`XMEM_TAG_WIDTH)
.TAG_WIDTH (`L1_MEM_TAG_WIDTH)
) mem_rsp_if();
assign mem_req_valid = mem_req_if.valid;

2
hw/rtl/VX_csr_data.v
View file

@ -30,6 +30,8 @@ module VX_csr_data #(
input wire busy
);
import fpu_types::*;
reg [`CSR_WIDTH-1:0] csr_satp;
reg [`CSR_WIDTH-1:0] csr_mstatus;
reg [`CSR_WIDTH-1:0] csr_medeleg;

2
hw/rtl/VX_decode.v
View file

@ -1,5 +1,7 @@
`include "VX_define.vh"
`ifdef DBG_PRINT_PIPELINE
`include "VX_print_instr.vh"
`endif
`ifdef EXT_F_ENABLE
`define USED_IREG(r) \

13
hw/rtl/VX_define.vh
View file

@ -301,6 +301,9 @@
`define _DNC_MEM_TAG_WIDTH ($clog2(`DCACHE_NUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCACHE_CORE_TAG_WIDTH)
`define DCACHE_MEM_TAG_WIDTH `MAX((`CLOG2(`DCACHE_NUM_BANKS) + `CLOG2(`DCACHE_MSHR_SIZE) + `NC_FLAG_BITS), `_DNC_MEM_TAG_WIDTH)
// Merged D-cache/I-cache memory tag
`define L1_MEM_TAG_WIDTH (`MAX(`ICACHE_MEM_TAG_WIDTH, `DCACHE_MEM_TAG_WIDTH) + `CLOG2(2))
////////////////////////// SM Configurable Knobs //////////////////////////////
// Cache ID
@ -343,9 +346,9 @@
// Memory request tag bits
`define _L2_MEM_ADDR_RATIO_W $clog2(`L2_CACHE_LINE_SIZE / `L2_WORD_SIZE)
`define _L2_NC_MEM_TAG_WIDTH ($clog2(`L2_NUM_REQS) + `_L2_MEM_ADDR_RATIO_W + `XMEM_TAG_WIDTH)
`define _L2_NC_MEM_TAG_WIDTH ($clog2(`L2_NUM_REQS) + `_L2_MEM_ADDR_RATIO_W + `L1_MEM_TAG_WIDTH)
`define _L2_MEM_TAG_WIDTH `MAX((`CLOG2(`L2_NUM_BANKS) + `CLOG2(`L2_MSHR_SIZE) + `NC_FLAG_BITS), `_L2_NC_MEM_TAG_WIDTH)
`define L2_MEM_TAG_WIDTH ((`L2_ENABLE) ? `_L2_MEM_TAG_WIDTH : (`XMEM_TAG_WIDTH + `CLOG2(`L2_NUM_REQS)))
`define L2_MEM_TAG_WIDTH ((`L2_ENABLE) ? `_L2_MEM_TAG_WIDTH : (`L1_MEM_TAG_WIDTH + `CLOG2(`L2_NUM_REQS)))
////////////////////////// L3cache Configurable Knobs /////////////////////////
@ -390,9 +393,9 @@
`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
// Merged D-cache/I-cache memory tag
`define XMEM_TAG_WIDTH (`DCACHE_MEM_TAG_WIDTH + `CLOG2(2))
///////////////////////////////////////////////////////////////////////////////
`include "VX_types.vh"
`include "VX_fpu_types.vh"
`include "VX_gpu_types.vh"
`endif

3
hw/rtl/VX_fpu_unit.v
View file

@ -13,7 +13,8 @@ module VX_fpu_unit #(
input wire[`NUM_WARPS-1:0] csr_pending,
output wire[`NUM_WARPS-1:0] pending
);
import fpu_types::*;
`UNUSED_PARAM (CORE_ID)
localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE);

34
hw/rtl/VX_types.vh → hw/rtl/VX_gpu_types.vh
View file

@ -1,34 +1,16 @@
`ifndef VX_TYPES
`define VX_TYPES
`ifndef VX_GPU_TYPES
`define VX_GPU_TYPES
`include "VX_define.vh"
typedef struct packed {
logic is_normal;
logic is_zero;
logic is_subnormal;
logic is_inf;
logic is_nan;
logic is_quiet;
logic is_signaling;
} fp_class_t;
typedef struct packed {
logic NV; // 4-Invalid
logic DZ; // 3-Divide by zero
logic OF; // 2-Overflow
logic UF; // 1-Underflow
logic NX; // 0-Inexact
} fflags_t;
`define FFLAGS_BITS $bits(fflags_t)
package gpu_types;
typedef struct packed {
logic valid;
logic [`NUM_THREADS-1:0] tmask;
} gpu_tmc_t;
`define GPU_TMC_BITS (1+`NUM_THREADS)
`define GPU_TMC_BITS $bits(gpu_tmc_t)
typedef struct packed {
logic valid;
@ -36,7 +18,7 @@ typedef struct packed {
logic [31:0] pc;
} gpu_wspawn_t;
`define GPU_WSPAWN_BITS (1+`NUM_WARPS+32)
`define GPU_WSPAWN_BITS $bits(gpu_wspawn_t)
typedef struct packed {
logic valid;
@ -46,7 +28,7 @@ typedef struct packed {
logic [31:0] pc;
} gpu_split_t;
`define GPU_SPLIT_BITS (1+1+`NUM_THREADS+`NUM_THREADS+32)
`define GPU_SPLIT_BITS $bits(gpu_split_t)
typedef struct packed {
logic valid;
@ -54,6 +36,8 @@ typedef struct packed {
logic [`NW_BITS-1:0] size_m1;
} gpu_barrier_t;
`define GPU_BARRIER_BITS (1+`NB_BITS+`NW_BITS)
`define GPU_BARRIER_BITS $bits(gpu_barrier_t)
endpackage
`endif

1
hw/rtl/VX_gpu_unit.v
View file

@ -15,6 +15,7 @@ module VX_gpu_unit #(
VX_warp_ctl_if.master warp_ctl_if,
VX_commit_if.master gpu_commit_if
);
import gpu_types::*;
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (clk)

2
hw/rtl/VX_lsu_unit.v
View file

@ -303,7 +303,7 @@ module VX_lsu_unit #(
`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
`ifndef SYNTHESIS
`ifndef __SYNTHESIS__
reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs;
wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));

28
hw/rtl/VX_platform.vh
View file

@ -1,7 +1,7 @@
`ifndef VX_PLATFORM
`define VX_PLATFORM
`ifndef SYNTHESIS
`ifndef __SYNTHESIS__
`include "util_dpi.vh"
`endif
@ -9,7 +9,7 @@
///////////////////////////////////////////////////////////////////////////////
`ifndef SYNTHESIS
`ifndef __SYNTHESIS__
`ifndef NDEBUG
`define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \
@ -29,7 +29,8 @@
/* verilator lint_off UNOPTFLAT */ \
/* verilator lint_off UNDRIVEN */ \
/* verilator lint_off DECLFILENAME */ \
/* verilator lint_off IMPLICIT */
/* verilator lint_off IMPLICIT */ \
/* verilator lint_off IMPORTSTAR */
`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \
/* verilator lint_on PINCONNECTEMPTY */ \
@ -37,7 +38,8 @@
/* verilator lint_on UNOPTFLAT */ \
/* verilator lint_on UNDRIVEN */ \
/* verilator lint_on DECLFILENAME */ \
/* verilator lint_on IMPLICIT */
/* verilator lint_on IMPLICIT */ \
/* verilator lint_on IMPORTSTAR */
`define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \
localparam __``x = x; \
@ -49,6 +51,9 @@
. x () \
/* verilator lint_on PINCONNECTEMPTY */
`define ERROR(msg) \
$error msg
`define ASSERT(cond, msg) \
assert(cond) else $error msg
@ -65,7 +70,7 @@
`define TRACING_ON /* verilator tracing_on */
`define TRACING_OFF /* verilator tracing_off */
`else // SYNTHESIS
`else // __SYNTHESIS__
`define DEBUG_BLOCK(x)
`define IGNORE_UNUSED_BEGIN
@ -75,13 +80,14 @@
`define UNUSED_PARAM(x)
`define UNUSED_VAR(x)
`define UNUSED_PIN(x) . x ()
`define ERROR(msg)
`define ASSERT(cond, msg) if (cond);
`define STATIC_ASSERT(cond, msg)
`define RUNTIME_ASSERT(cond, msg)
`define TRACING_ON
`define TRACING_OFF
`endif // SYNTHESIS
`endif // __SYNTHESIS__
///////////////////////////////////////////////////////////////////////////////
@ -106,14 +112,12 @@
`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1)
`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1))))
`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : x);
`define ABS(x) (($signed(x) < 0) ? (-$signed(x)) : (x));
`define MIN(x, y) ((x < y) ? (x) : (y))
`define MAX(x, y) ((x > y) ? (x) : (y))
`define MIN(x, y) (((x) < (y)) ? (x) : (y))
`define MAX(x, y) (((x) > (y)) ? (x) : (y))
`define UP(x) (((x) > 0) ? x : 1)
`define SAFE_RNG(h,l) `MAX(h,l) : l
`define UP(x) (((x) > 0) ? (x) : 1)
`define RTRIM(x,s) x[$bits(x)-1:($bits(x)-s)]

10
hw/rtl/Vortex.v
View file

@ -30,14 +30,14 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag;
wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;

2
hw/rtl/fp_cores/VX_fp_class.v
View file

@ -1,5 +1,5 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
module VX_fp_class # (
parameter MAN_BITS = 23,

2
hw/rtl/fp_cores/VX_fp_cvt.v
View file

@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
/// Modified port of cast module from fpnew Libray
/// reference: https://github.com/pulp-platform/fpnew

6
hw/rtl/fp_cores/VX_fp_div.v
View file

@ -1,8 +1,4 @@
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`include "VX_fpu_define.vh"
module VX_fp_div #(
parameter TAGW = 1,

6
hw/rtl/fp_cores/VX_fp_fma.v
View file

@ -1,8 +1,4 @@
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`include "VX_fpu_define.vh"
module VX_fp_fma #(
parameter TAGW = 1,

2
hw/rtl/fp_cores/VX_fp_ncomp.v
View file

@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
/// Modified port of noncomp module from fpnew Libray
/// reference: https://github.com/pulp-platform/fpnew

3
hw/rtl/fp_cores/VX_fp_rounding.v
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
/// Modified port of rouding module from fpnew Libray
/// reference: https://github.com/pulp-platform/fpnew

6
hw/rtl/fp_cores/VX_fp_sqrt.v
View file

@ -1,8 +1,4 @@
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`include "VX_fpu_define.vh"
module VX_fp_sqrt #(
parameter TAGW = 1,

14
hw/rtl/fp_cores/VX_fpu_define.vh Normal file
View file

@ -0,0 +1,14 @@
`ifndef VX_FPU_DEFINE
`define VX_FPU_DEFINE
`include "VX_define.vh"
`ifndef SYNTHESIS
`include "float_dpi.vh"
`endif
`IGNORE_WARNINGS_BEGIN
import fpu_types::*;
`IGNORE_WARNINGS_END
`endif

9
hw/rtl/fp_cores/VX_fpu_dpi.v
View file

@ -1,7 +1,4 @@
`ifndef SYNTHESIS
`include "VX_define.vh"
`include "float_dpi.vh"
`include "VX_fpu_define.vh"
module VX_fpu_dpi #(
parameter TAGW = 1
@ -410,6 +407,4 @@ module VX_fpu_dpi #(
assign ready_in = per_core_ready_in[core_select];
endmodule
`endif
endmodule

2
hw/rtl/fp_cores/VX_fpu_fpga.v
View file

@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
module VX_fpu_fpga #(
parameter TAGW = 4

2
hw/rtl/fp_cores/VX_fpu_fpnew.v
View file

@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_fpu_define.vh"
`include "fpnew_pkg.sv"
`include "defs_div_sqrt_mvp.sv"

32
hw/rtl/fp_cores/VX_fpu_types.vh Normal file
View file

@ -0,0 +1,32 @@
`ifndef VX_FPU_TYPES
`define VX_FPU_TYPES
`include "VX_define.vh"
package fpu_types;
typedef struct packed {
logic is_normal;
logic is_zero;
logic is_subnormal;
logic is_inf;
logic is_nan;
logic is_quiet;
logic is_signaling;
} fp_class_t;
`define FP_CLASS_BITS $bits(fp_class_t)
typedef struct packed {
logic NV; // 4-Invalid
logic DZ; // 3-Divide by zero
logic OF; // 2-Overflow
logic UF; // 1-Underflow
logic NX; // 0-Inexact
} fflags_t;
`define FFLAGS_BITS $bits(fflags_t)
endpackage
`endif

2
hw/rtl/interfaces/VX_fpu_to_csr_if.v
View file

@ -7,7 +7,7 @@ interface VX_fpu_to_csr_if ();
wire write_enable;
wire [`NW_BITS-1:0] write_wid;
fflags_t write_fflags;
fpu_types::fflags_t write_fflags;
wire [`NW_BITS-1:0] read_wid;
wire [`INST_FRM_BITS-1:0] read_frm;

12
hw/rtl/interfaces/VX_warp_ctl_if.v
View file

@ -5,12 +5,12 @@
interface VX_warp_ctl_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
gpu_tmc_t tmc;
gpu_wspawn_t wspawn;
gpu_barrier_t barrier;
gpu_split_t split;
wire valid;
wire [`NW_BITS-1:0] wid;
gpu_types::gpu_tmc_t tmc;
gpu_types::gpu_wspawn_t wspawn;
gpu_types::gpu_barrier_t barrier;
gpu_types::gpu_split_t split;
modport master (
output valid,

2
hw/rtl/libs/VX_bypass_buffer.v
View file

@ -31,7 +31,7 @@ module VX_bypass_buffer #(
buffer_valid <= 0;
end
if (valid_in && ~ready_out) begin
`ASSERT(!buffer_valid, "runtime error");
`ASSERT(!buffer_valid, ("runtime error"));
buffer_valid <= 1;
end
end

2
hw/rtl/libs/VX_dp_ram.v
View file

@ -34,7 +34,7 @@ module VX_dp_ram #(
end \
end
`ifdef SYNTHESIS
`ifdef __SYNTHESIS__
if (LUTRAM) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;

2
hw/rtl/libs/VX_sp_ram.v
View file

@ -33,7 +33,7 @@ module VX_sp_ram #(
end \
end
`ifdef SYNTHESIS
`ifdef __SYNTHESIS__
if (LUTRAM) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;

2
hw/rtl/libs/VX_stream_arbiter.v
View file

@ -95,7 +95,7 @@ module VX_stream_arbiter #(
.grant_onehot (sel_onehot)
);
end else begin
$error ("invalid parameter");
`ERROR(("invalid parameter"));
end
wire [LANES-1:0] valid_in_sel;

1
hw/syn/opae/vortex_afu.qsf
View file

@ -5,7 +5,6 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON

1
hw/syn/quartus/project.tcl
View file

@ -36,7 +36,6 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON