github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

DCR bus interface refcatoring

Browse source
This commit is contained in:
Blaise Tine 2023-06-22 16:02:39 -04:00
parent d5e73b3478
commit a4c8ea0d8d
14 changed files with 172 additions and 172 deletions
Download patch file Download diff file Expand all files Collapse all files

50
hw/rtl/VX_cluster.sv
View file

@ -31,7 +31,7 @@ module VX_cluster #(
VX_mem_perf_if.slave perf_memsys_total_if,
`endif
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
@ -115,12 +115,12 @@ module VX_cluster #(
.NUM_LANES (`NUM_THREADS)
) raster_bus_if[`NUM_RASTER_UNITS]();
VX_dcr_write_if raster_dcr_write_tmp_if();
assign raster_dcr_write_tmp_if.valid = dcr_write_if.valid && (dcr_write_if.addr >= `DCR_RASTER_STATE_BEGIN && dcr_write_if.addr < `DCR_RASTER_STATE_END);
assign raster_dcr_write_tmp_if.addr = dcr_write_if.addr;
assign raster_dcr_write_tmp_if.data = dcr_write_if.data;
VX_dcr_bus_if raster_dcr_bus_tmp_if();
assign raster_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `DCR_RASTER_STATE_BEGIN && dcr_bus_if.write_addr < `DCR_RASTER_STATE_END);
assign raster_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
assign raster_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
`BUFFER_DCR_WRITE_IF (raster_dcr_write_if, raster_dcr_write_tmp_if, 1);
`BUFFER_DCR_BUS_IF (raster_dcr_bus_if, raster_dcr_bus_tmp_if, 1);
// Generate all raster units
for (genvar i = 0; i < `NUM_RASTER_UNITS; ++i) begin
@ -144,7 +144,7 @@ module VX_cluster #(
`ifdef PERF_ENABLE
.perf_raster_if(perf_raster_unit_if[i]),
`endif
.dcr_write_if (raster_dcr_write_if),
.dcr_bus_if (raster_dcr_bus_if),
.raster_bus_if (raster_bus_if[i]),
.cache_bus_if (rcache_bus_if[i])
);
@ -206,12 +206,12 @@ module VX_cluster #(
.bus_out_if (rop_bus_if)
);
VX_dcr_write_if rop_dcr_write_tmp_if();
assign rop_dcr_write_tmp_if.valid = dcr_write_if.valid && (dcr_write_if.addr >= `DCR_ROP_STATE_BEGIN && dcr_write_if.addr < `DCR_ROP_STATE_END);
assign rop_dcr_write_tmp_if.addr = dcr_write_if.addr;
assign rop_dcr_write_tmp_if.data = dcr_write_if.data;
VX_dcr_bus_if rop_dcr_bus_tmp_if();
assign rop_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `DCR_ROP_STATE_BEGIN && dcr_bus_if.write_addr < `DCR_ROP_STATE_END);
assign rop_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
assign rop_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
`BUFFER_DCR_WRITE_IF (rop_dcr_write_if, rop_dcr_write_tmp_if, 1);
`BUFFER_DCR_BUS_IF (rop_dcr_bus_if, rop_dcr_bus_tmp_if, 1);
// Generate all rop units
for (genvar i = 0; i < `NUM_ROP_UNITS; ++i) begin
@ -227,7 +227,7 @@ module VX_cluster #(
`ifdef PERF_ENABLE
.perf_rop_if (perf_rop_unit_if[i]),
`endif
.dcr_write_if (rop_dcr_write_if),
.dcr_bus_if (rop_dcr_bus_if),
.rop_bus_if (rop_bus_if[i]),
.cache_bus_if (ocache_bus_if[i])
);
@ -274,12 +274,12 @@ module VX_cluster #(
.bus_out_if (tex_bus_if)
);
VX_dcr_write_if tex_dcr_write_tmp_if();
assign tex_dcr_write_tmp_if.valid = dcr_write_if.valid && (dcr_write_if.addr >= `DCR_TEX_STATE_BEGIN && dcr_write_if.addr < `DCR_TEX_STATE_END);
assign tex_dcr_write_tmp_if.addr = dcr_write_if.addr;
assign tex_dcr_write_tmp_if.data = dcr_write_if.data;
VX_dcr_bus_if tex_dcr_bus_tmp_if();
assign tex_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `DCR_TEX_STATE_BEGIN && dcr_bus_if.write_addr < `DCR_TEX_STATE_END);
assign tex_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
assign tex_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
`BUFFER_DCR_WRITE_IF (tex_dcr_write_if, tex_dcr_write_tmp_if, 1);
`BUFFER_DCR_BUS_IF (tex_dcr_bus_if, tex_dcr_bus_tmp_if, 1);
// Generate all texture units
for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
@ -296,7 +296,7 @@ module VX_cluster #(
`ifdef PERF_ENABLE
.perf_tex_if (perf_tex_unit_if[i]),
`endif
.dcr_write_if (tex_dcr_write_if),
.dcr_bus_if (tex_dcr_bus_if),
.tex_bus_if (tex_bus_if[i]),
.cache_bus_if (tcache_bus_if[i])
);
@ -411,14 +411,14 @@ module VX_cluster #(
`UNUSED_VAR (per_socket_sim_ebreak)
`UNUSED_VAR (per_socket_sim_wb_value)
VX_dcr_write_if socket_dcr_write_tmp_if();
assign socket_dcr_write_tmp_if.valid = dcr_write_if.valid && (dcr_write_if.addr >= `DCR_BASE_STATE_BEGIN && dcr_write_if.addr < `DCR_BASE_STATE_END);
assign socket_dcr_write_tmp_if.addr = dcr_write_if.addr;
assign socket_dcr_write_tmp_if.data = dcr_write_if.data;
VX_dcr_bus_if socket_dcr_bus_tmp_if();
assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `DCR_BASE_STATE_END);
assign socket_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
assign socket_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
wire [`NUM_SOCKETS-1:0] per_socket_busy;
`BUFFER_DCR_WRITE_IF (socket_dcr_write_if, socket_dcr_write_tmp_if, (`NUM_SOCKETS > 1));
`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1));
// Generate all sockets
for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
@ -437,7 +437,7 @@ module VX_cluster #(
.mem_perf_if (perf_memsys_total_if),
`endif
.dcr_write_if (socket_dcr_write_if),
.dcr_bus_if (socket_dcr_bus_if),
.dcache_bus_if (per_socket_dcache_bus_if[i]),

10
hw/rtl/VX_define.vh
View file

@ -445,17 +445,17 @@
end \
assign ``dst.``field = __reduce_add_r_``dst``field
`define BUFFER_DCR_WRITE_IF(dst, src, enable) \
`define BUFFER_DCR_BUS_IF(dst, src, enable) \
logic [(1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH)-1:0] __``dst; \
if (enable) begin \
always @(posedge clk) begin \
__``dst <= {src.valid, src.addr, src.data}; \
__``dst <= {src.write_valid, src.write_addr, src.write_data}; \
end \
end else begin \
assign __``dst = {src.valid, src.addr, src.data}; \
assign __``dst = {src.write_valid, src.write_addr, src.write_data}; \
end \
VX_dcr_write_if dst(); \
assign {dst.valid, dst.addr, dst.data} = __``dst
VX_dcr_bus_if dst(); \
assign {dst.write_valid, dst.write_addr, dst.write_data} = __``dst
`define BUFFER_BUSY(src, enable) \
logic __busy; \

6
hw/rtl/VX_socket.sv
View file

@ -18,7 +18,7 @@ module VX_socket #(
VX_mem_perf_if.slave mem_perf_if,
`endif
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
VX_cache_bus_if.master dcache_bus_if,
@ -271,7 +271,7 @@ module VX_socket #(
wire [`SOCKET_SIZE-1:0] per_core_busy;
`BUFFER_DCR_WRITE_IF (core_dcr_write_if, dcr_write_if, (`SOCKET_SIZE > 1));
`BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, (`SOCKET_SIZE > 1));
`SCOPE_IO_SWITCH (`SOCKET_SIZE)
@ -292,7 +292,7 @@ module VX_socket #(
.mem_perf_if (mem_perf_if),
`endif
.dcr_write_if (core_dcr_write_if),
.dcr_bus_if (core_dcr_bus_if),
.dcache_bus_if (per_core_dcache_bus_if[i]),

12
hw/rtl/Vortex.sv
View file

@ -124,10 +124,10 @@ module Vortex (
.TAG_WIDTH (L2_MEM_TAG_WIDTH)
) per_cluster_mem_bus_if[`NUM_CLUSTERS]();
VX_dcr_write_if dcr_write_if();
assign dcr_write_if.valid = dcr_wr_valid;
assign dcr_write_if.addr = dcr_wr_addr;
assign dcr_write_if.data = dcr_wr_data;
VX_dcr_bus_if dcr_bus_if();
assign dcr_bus_if.write_valid = dcr_wr_valid;
assign dcr_bus_if.write_addr = dcr_wr_addr;
assign dcr_bus_if.write_data = dcr_wr_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
@ -138,7 +138,7 @@ module Vortex (
`RESET_RELAY (cluster_reset, reset);
`BUFFER_DCR_WRITE_IF (cluster_dcr_write_if, dcr_write_if, (`NUM_CLUSTERS > 1));
`BUFFER_DCR_BUS_IF (cluster_dcr_bus_if, dcr_bus_if, (`NUM_CLUSTERS > 1));
VX_cluster #(
.CLUSTER_ID (i)
@ -153,7 +153,7 @@ module Vortex (
.perf_memsys_total_if (perf_memsys_total_if),
`endif
.dcr_write_if (cluster_dcr_write_if),
.dcr_bus_if (cluster_dcr_bus_if),
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE

14
hw/rtl/core/VX_core.sv
View file

@ -37,7 +37,7 @@ module VX_core #(
VX_mem_perf_if.slave mem_perf_if,
`endif
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
VX_cache_bus_if.master dcache_bus_if,
@ -123,7 +123,7 @@ module VX_core #(
VX_dcr_data dcr_data (
.clk (clk),
.reset (dcr_data_reset),
.dcr_write_if(dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.base_dcrs (base_dcrs)
);
@ -477,11 +477,11 @@ module VX_core_top #(
assign gbar_bus_if.rsp_valid = gbar_rsp_valid;
assign gbar_bus_if.rsp_id = gbar_rsp_id;
VX_dcr_write_if dcr_write_if();
VX_dcr_bus_if dcr_bus_if();
assign dcr_write_if.valid = dcr_write_valid;
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
assign dcr_bus_if.write_valid = dcr_write_valid;
assign dcr_bus_if.write_addr = dcr_write_addr;
assign dcr_bus_if.write_data = dcr_write_data;
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
@ -606,7 +606,7 @@ module VX_core_top #(
.clk (clk),
.reset (reset),
.dcr_write_if (dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.dcache_bus_if (dcache_bus_if),

18
hw/rtl/core/VX_dcr_data.sv
View file

@ -13,7 +13,7 @@ module VX_dcr_data (
input wire reset,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
// Outputs
output base_dcrs_t base_dcrs
@ -24,13 +24,13 @@ module VX_dcr_data (
base_dcrs_t dcrs;
always @(posedge clk) begin
if (dcr_write_if.valid) begin
case (dcr_write_if.addr)
`DCR_BASE_STARTUP_ADDR0 : dcrs.startup_addr[31:0] <= dcr_write_if.data;
if (dcr_bus_if.write_valid) begin
case (dcr_bus_if.write_addr)
`DCR_BASE_STARTUP_ADDR0 : dcrs.startup_addr[31:0] <= dcr_bus_if.write_data;
`ifdef XLEN_64
`DCR_BASE_STARTUP_ADDR1 : dcrs.startup_addr[63:32] <= dcr_write_if.data;
`DCR_BASE_STARTUP_ADDR1 : dcrs.startup_addr[63:32] <= dcr_bus_if.write_data;
`endif
`DCR_BASE_MPM_CLASS : dcrs.mpm_class <= dcr_write_if.data[7:0];
`DCR_BASE_MPM_CLASS : dcrs.mpm_class <= dcr_bus_if.write_data[7:0];
default:;
endcase
end
@ -40,10 +40,10 @@ module VX_dcr_data (
`ifdef DBG_TRACE_CORE_PIPELINE
always @(posedge clk) begin
if (dcr_write_if.valid) begin
if (dcr_bus_if.write_valid) begin
`TRACE(1, ("%d: base-dcr: state=", $time));
trace_base_dcr(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
trace_base_dcr(1, dcr_bus_if.write_addr);
`TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data));
end
end
`endif

21
hw/rtl/interfaces/VX_dcr_bus_if.sv Normal file
View file

@ -0,0 +1,21 @@
`include "VX_define.vh"
interface VX_dcr_bus_if ();
wire write_valid;
wire [`VX_DCR_ADDR_WIDTH-1:0] write_addr;
wire [`VX_DCR_DATA_WIDTH-1:0] write_data;
modport master (
output write_valid,
output write_addr,
output write_data
);
modport slave (
input write_valid,
input write_addr,
input write_data
);
endinterface

21
hw/rtl/interfaces/VX_dcr_write_if.sv
View file

@ -1,21 +0,0 @@
`include "VX_define.vh"
interface VX_dcr_write_if ();
wire valid;
wire [`VX_DCR_ADDR_WIDTH-1:0] addr;
wire [`VX_DCR_DATA_WIDTH-1:0] data;
modport master (
output valid,
output addr,
output data
);
modport slave (
input valid,
input addr,
input data
);
endinterface

28
hw/rtl/raster/VX_raster_dcr.sv
View file

@ -7,7 +7,7 @@ module VX_raster_dcr #(
input wire reset,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
// Output
output raster_dcrs_t raster_dcrs
@ -21,27 +21,27 @@ module VX_raster_dcr #(
// DCRs write
always @(posedge clk) begin
if (dcr_write_if.valid) begin
case (dcr_write_if.addr)
if (dcr_bus_if.write_valid) begin
case (dcr_bus_if.write_addr)
`DCR_RASTER_TBUF_ADDR: begin
dcrs.tbuf_addr <= dcr_write_if.data[`RASTER_DCR_DATA_BITS-1:0];
dcrs.tbuf_addr <= dcr_bus_if.write_data[`RASTER_DCR_DATA_BITS-1:0];
end
`DCR_RASTER_TILE_COUNT: begin
dcrs.tile_count <= dcr_write_if.data[`RASTER_TILE_BITS-1:0];
dcrs.tile_count <= dcr_bus_if.write_data[`RASTER_TILE_BITS-1:0];
end
`DCR_RASTER_PBUF_ADDR: begin
dcrs.pbuf_addr <= dcr_write_if.data[`RASTER_DCR_DATA_BITS-1:0];
dcrs.pbuf_addr <= dcr_bus_if.write_data[`RASTER_DCR_DATA_BITS-1:0];
end
`DCR_RASTER_PBUF_STRIDE: begin
dcrs.pbuf_stride <= dcr_write_if.data[`RASTER_STRIDE_BITS-1:0];
dcrs.pbuf_stride <= dcr_bus_if.write_data[`RASTER_STRIDE_BITS-1:0];
end
`DCR_RASTER_SCISSOR_X: begin
dcrs.dst_xmin <= dcr_write_if.data[0 +: `RASTER_DIM_BITS];
dcrs.dst_xmax <= dcr_write_if.data[16 +: `RASTER_DIM_BITS];
dcrs.dst_xmin <= dcr_bus_if.write_data[0 +: `RASTER_DIM_BITS];
dcrs.dst_xmax <= dcr_bus_if.write_data[16 +: `RASTER_DIM_BITS];
end
`DCR_RASTER_SCISSOR_Y: begin
dcrs.dst_ymin <= dcr_write_if.data[0 +: `RASTER_DIM_BITS];
dcrs.dst_ymax <= dcr_write_if.data[16 +: `RASTER_DIM_BITS];
dcrs.dst_ymin <= dcr_bus_if.write_data[0 +: `RASTER_DIM_BITS];
dcrs.dst_ymax <= dcr_bus_if.write_data[16 +: `RASTER_DIM_BITS];
end
endcase
end
@ -52,10 +52,10 @@ module VX_raster_dcr #(
`ifdef DBG_TRACE_RASTER
always @(posedge clk) begin
if (dcr_write_if.valid) begin
if (dcr_bus_if.write_valid) begin
`TRACE(1, ("%d: %s-raster-dcr: state=", $time, INSTANCE_ID));
`TRACE_RASTER_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
`TRACE_RASTER_DCR(1, dcr_bus_if.write_addr);
`TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data));
end
end
`endif

14
hw/rtl/raster/VX_raster_unit.sv
View file

@ -26,7 +26,7 @@ module VX_raster_unit #(
VX_cache_bus_if.master cache_bus_if,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
// Outputs
VX_raster_bus_if.master raster_bus_if
@ -48,7 +48,7 @@ module VX_raster_unit #(
) raster_dcr (
.clk (clk),
.reset (reset),
.dcr_write_if(dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.raster_dcrs(raster_dcrs)
);
@ -434,11 +434,11 @@ module VX_raster_unit_top #(
VX_raster_perf_if perf_raster_if();
VX_dcr_write_if dcr_write_if();
VX_dcr_bus_if dcr_bus_if();
assign dcr_write_if.valid = dcr_write_valid;
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
assign dcr_bus_if.write_valid = dcr_write_valid;
assign dcr_bus_if.write_addr = dcr_write_addr;
assign dcr_bus_if.write_data = dcr_write_data;
VX_raster_bus_if #(
.NUM_LANES (OUTPUT_QUADS)
@ -492,7 +492,7 @@ module VX_raster_unit_top #(
`ifdef PERF_ENABLE
.perf_raster_if(perf_raster_if),
`endif
.dcr_write_if (dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.raster_bus_if (raster_bus_if),
.cache_bus_if (cache_bus_if)
);

90
hw/rtl/rop/VX_rop_dcr.sv
View file

@ -7,7 +7,7 @@ module VX_rop_dcr #(
input wire reset,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
// Output
output rop_dcrs_t rop_dcrs
@ -37,82 +37,82 @@ module VX_rop_dcr #(
// DCRs write
always @(posedge clk) begin
if (dcr_write_if.valid) begin
case (dcr_write_if.addr)
if (dcr_bus_if.write_valid) begin
case (dcr_bus_if.write_addr)
`DCR_ROP_CBUF_ADDR: begin
dcrs.cbuf_addr <= dcr_write_if.data[31:0];
dcrs.cbuf_addr <= dcr_bus_if.write_data[31:0];
end
`DCR_ROP_CBUF_PITCH: begin
dcrs.cbuf_pitch <= dcr_write_if.data[`ROP_PITCH_BITS-1:0];
dcrs.cbuf_pitch <= dcr_bus_if.write_data[`ROP_PITCH_BITS-1:0];
end
`DCR_ROP_CBUF_WRITEMASK: begin
dcrs.cbuf_writemask <= dcr_write_if.data[3:0];
dcrs.cbuf_writemask <= dcr_bus_if.write_data[3:0];
end
`DCR_ROP_ZBUF_ADDR: begin
dcrs.zbuf_addr <= dcr_write_if.data[31:0];
dcrs.zbuf_addr <= dcr_bus_if.write_data[31:0];
end
`DCR_ROP_ZBUF_PITCH: begin
dcrs.zbuf_pitch <= dcr_write_if.data[`ROP_PITCH_BITS-1:0];
dcrs.zbuf_pitch <= dcr_bus_if.write_data[`ROP_PITCH_BITS-1:0];
end
`DCR_ROP_DEPTH_FUNC: begin
dcrs.depth_func <= dcr_write_if.data[0 +: `ROP_DEPTH_FUNC_BITS];
dcrs.depth_enable <= `DEPTH_TEST_ENABLE(dcr_write_if.data[0 +: `ROP_DEPTH_FUNC_BITS], dcrs.depth_writemask);
dcrs.depth_func <= dcr_bus_if.write_data[0 +: `ROP_DEPTH_FUNC_BITS];
dcrs.depth_enable <= `DEPTH_TEST_ENABLE(dcr_bus_if.write_data[0 +: `ROP_DEPTH_FUNC_BITS], dcrs.depth_writemask);
end
`DCR_ROP_DEPTH_WRITEMASK: begin
dcrs.depth_writemask <= dcr_write_if.data[0];
dcrs.depth_enable <= `DEPTH_TEST_ENABLE(dcrs.depth_func, dcr_write_if.data[0]);
dcrs.depth_writemask <= dcr_bus_if.write_data[0];
dcrs.depth_enable <= `DEPTH_TEST_ENABLE(dcrs.depth_func, dcr_bus_if.write_data[0]);
end
`DCR_ROP_STENCIL_FUNC: begin
dcrs.stencil_func[0] <= dcr_write_if.data[0 +: `ROP_DEPTH_FUNC_BITS];
dcrs.stencil_func[1] <= dcr_write_if.data[16 +: `ROP_DEPTH_FUNC_BITS];
dcrs.stencil_enable[0] <= `STENCIL_TEST_ENABLE(dcr_write_if.data[0 +: `ROP_DEPTH_FUNC_BITS], dcrs.stencil_zpass[0], dcrs.stencil_zfail[0]);
dcrs.stencil_enable[1] <= `STENCIL_TEST_ENABLE(dcr_write_if.data[16 +: `ROP_DEPTH_FUNC_BITS], dcrs.stencil_zpass[1], dcrs.stencil_zfail[1]);
dcrs.stencil_func[0] <= dcr_bus_if.write_data[0 +: `ROP_DEPTH_FUNC_BITS];
dcrs.stencil_func[1] <= dcr_bus_if.write_data[16 +: `ROP_DEPTH_FUNC_BITS];
dcrs.stencil_enable[0] <= `STENCIL_TEST_ENABLE(dcr_bus_if.write_data[0 +: `ROP_DEPTH_FUNC_BITS], dcrs.stencil_zpass[0], dcrs.stencil_zfail[0]);
dcrs.stencil_enable[1] <= `STENCIL_TEST_ENABLE(dcr_bus_if.write_data[16 +: `ROP_DEPTH_FUNC_BITS], dcrs.stencil_zpass[1], dcrs.stencil_zfail[1]);
end
`DCR_ROP_STENCIL_ZPASS: begin
dcrs.stencil_zpass[0] <= dcr_write_if.data[0 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_zpass[1] <= dcr_write_if.data[16 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_enable[0] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[0], dcr_write_if.data[0 +: `ROP_STENCIL_OP_BITS], dcrs.stencil_zfail[0]);
dcrs.stencil_enable[1] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[1], dcr_write_if.data[16 +: `ROP_STENCIL_OP_BITS], dcrs.stencil_zfail[1]);
dcrs.stencil_zpass[0] <= dcr_bus_if.write_data[0 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_zpass[1] <= dcr_bus_if.write_data[16 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_enable[0] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[0], dcr_bus_if.write_data[0 +: `ROP_STENCIL_OP_BITS], dcrs.stencil_zfail[0]);
dcrs.stencil_enable[1] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[1], dcr_bus_if.write_data[16 +: `ROP_STENCIL_OP_BITS], dcrs.stencil_zfail[1]);
end
`DCR_ROP_STENCIL_ZFAIL: begin
dcrs.stencil_zfail[0] <= dcr_write_if.data[0 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_zfail[1] <= dcr_write_if.data[16 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_enable[0] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[0], dcrs.stencil_zpass[0], dcr_write_if.data[0 +: `ROP_STENCIL_OP_BITS]);
dcrs.stencil_enable[1] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[1], dcrs.stencil_zpass[1], dcr_write_if.data[16 +: `ROP_STENCIL_OP_BITS]);
dcrs.stencil_zfail[0] <= dcr_bus_if.write_data[0 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_zfail[1] <= dcr_bus_if.write_data[16 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_enable[0] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[0], dcrs.stencil_zpass[0], dcr_bus_if.write_data[0 +: `ROP_STENCIL_OP_BITS]);
dcrs.stencil_enable[1] <= `STENCIL_TEST_ENABLE(dcrs.stencil_func[1], dcrs.stencil_zpass[1], dcr_bus_if.write_data[16 +: `ROP_STENCIL_OP_BITS]);
end
`DCR_ROP_STENCIL_FAIL: begin
dcrs.stencil_fail[0] <= dcr_write_if.data[0 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_fail[1] <= dcr_write_if.data[16 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_fail[0] <= dcr_bus_if.write_data[0 +: `ROP_STENCIL_OP_BITS];
dcrs.stencil_fail[1] <= dcr_bus_if.write_data[16 +: `ROP_STENCIL_OP_BITS];
end
`DCR_ROP_STENCIL_REF: begin
dcrs.stencil_ref[0] <= dcr_write_if.data[0 +: `ROP_STENCIL_BITS];
dcrs.stencil_ref[1] <= dcr_write_if.data[16 +: `ROP_STENCIL_BITS];
dcrs.stencil_ref[0] <= dcr_bus_if.write_data[0 +: `ROP_STENCIL_BITS];
dcrs.stencil_ref[1] <= dcr_bus_if.write_data[16 +: `ROP_STENCIL_BITS];
end
`DCR_ROP_STENCIL_MASK: begin
dcrs.stencil_mask[0] <= dcr_write_if.data[0 +: `ROP_STENCIL_BITS];
dcrs.stencil_mask[1] <= dcr_write_if.data[16 +: `ROP_STENCIL_BITS];
dcrs.stencil_mask[0] <= dcr_bus_if.write_data[0 +: `ROP_STENCIL_BITS];
dcrs.stencil_mask[1] <= dcr_bus_if.write_data[16 +: `ROP_STENCIL_BITS];
end
`DCR_ROP_STENCIL_WRITEMASK: begin
dcrs.stencil_writemask[0] <= dcr_write_if.data[0 +: `ROP_STENCIL_BITS];
dcrs.stencil_writemask[1] <= dcr_write_if.data[16 +: `ROP_STENCIL_BITS];
dcrs.stencil_writemask[0] <= dcr_bus_if.write_data[0 +: `ROP_STENCIL_BITS];
dcrs.stencil_writemask[1] <= dcr_bus_if.write_data[16 +: `ROP_STENCIL_BITS];
end
`DCR_ROP_BLEND_MODE: begin
dcrs.blend_mode_rgb <= dcr_write_if.data[0 +: `ROP_BLEND_MODE_BITS];
dcrs.blend_mode_a <= dcr_write_if.data[16 +: `ROP_BLEND_MODE_BITS];
dcrs.blend_enable <= `BLEND_ENABLE(dcr_write_if.data[0 +: `ROP_BLEND_MODE_BITS], dcr_write_if.data[16 +: `ROP_BLEND_MODE_BITS], dcrs.blend_src_rgb, dcrs.blend_src_a, dcrs.blend_dst_rgb, dcrs.blend_dst_a);
dcrs.blend_mode_rgb <= dcr_bus_if.write_data[0 +: `ROP_BLEND_MODE_BITS];
dcrs.blend_mode_a <= dcr_bus_if.write_data[16 +: `ROP_BLEND_MODE_BITS];
dcrs.blend_enable <= `BLEND_ENABLE(dcr_bus_if.write_data[0 +: `ROP_BLEND_MODE_BITS], dcr_bus_if.write_data[16 +: `ROP_BLEND_MODE_BITS], dcrs.blend_src_rgb, dcrs.blend_src_a, dcrs.blend_dst_rgb, dcrs.blend_dst_a);
end
`DCR_ROP_BLEND_FUNC: begin
dcrs.blend_src_rgb <= dcr_write_if.data[0 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_src_a <= dcr_write_if.data[8 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_dst_rgb <= dcr_write_if.data[16 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_dst_a <= dcr_write_if.data[24 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_enable <= `BLEND_ENABLE(dcrs.blend_mode_rgb, dcrs.blend_mode_a, dcr_write_if.data[0 +: `ROP_BLEND_FUNC_BITS], dcr_write_if.data[8 +: `ROP_BLEND_FUNC_BITS], dcr_write_if.data[16 +: `ROP_BLEND_FUNC_BITS], dcr_write_if.data[24 +: `ROP_BLEND_FUNC_BITS]);
dcrs.blend_src_rgb <= dcr_bus_if.write_data[0 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_src_a <= dcr_bus_if.write_data[8 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_dst_rgb <= dcr_bus_if.write_data[16 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_dst_a <= dcr_bus_if.write_data[24 +: `ROP_BLEND_FUNC_BITS];
dcrs.blend_enable <= `BLEND_ENABLE(dcrs.blend_mode_rgb, dcrs.blend_mode_a, dcr_bus_if.write_data[0 +: `ROP_BLEND_FUNC_BITS], dcr_bus_if.write_data[8 +: `ROP_BLEND_FUNC_BITS], dcr_bus_if.write_data[16 +: `ROP_BLEND_FUNC_BITS], dcr_bus_if.write_data[24 +: `ROP_BLEND_FUNC_BITS]);
end
`DCR_ROP_BLEND_CONST: begin
dcrs.blend_const <= dcr_write_if.data[0 +: 32];
dcrs.blend_const <= dcr_bus_if.write_data[0 +: 32];
end
`DCR_ROP_LOGIC_OP: begin
dcrs.logic_op <= dcr_write_if.data[0 +: `ROP_LOGIC_OP_BITS];
dcrs.logic_op <= dcr_bus_if.write_data[0 +: `ROP_LOGIC_OP_BITS];
end
endcase
end
@ -123,10 +123,10 @@ module VX_rop_dcr #(
`ifdef DBG_TRACE_ROP
always @(posedge clk) begin
if (dcr_write_if.valid) begin
if (dcr_bus_if.write_valid) begin
`TRACE(1, ("%d: %s-rop-dcr: state=", $time, INSTANCE_ID));
`TRACE_ROP_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
`TRACE_ROP_DCR(1, dcr_bus_if.write_addr);
`TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data));
end
end
`endif

14
hw/rtl/rop/VX_rop_unit.sv
View file

@ -16,7 +16,7 @@ module VX_rop_unit #(
VX_cache_bus_if.master cache_bus_if,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
VX_rop_bus_if.slave rop_bus_if
);
localparam UUID_WIDTH = `UP(`UUID_BITS);
@ -33,7 +33,7 @@ module VX_rop_unit #(
) rop_dcr (
.clk (clk),
.reset (reset),
.dcr_write_if(dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.rop_dcrs (rop_dcrs)
);
@ -415,11 +415,11 @@ module VX_rop_unit_top #(
VX_rop_perf_if perf_rop_if();
VX_dcr_write_if dcr_write_if();
VX_dcr_bus_if dcr_bus_if();
assign dcr_write_if.valid = dcr_write_valid;
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
assign dcr_bus_if.write_valid = dcr_write_valid;
assign dcr_bus_if.write_addr = dcr_write_addr;
assign dcr_bus_if.write_data = dcr_write_data;
VX_rop_bus_if #(
.NUM_LANES (NUM_LANES)
@ -463,7 +463,7 @@ module VX_rop_unit_top #(
`ifdef PERF_ENABLE
.perf_rop_if (perf_rop_if),
`endif
.dcr_write_if (dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.rop_bus_if (rop_bus_if),
.cache_bus_if (cache_bus_if)
);

32
hw/rtl/tex/VX_tex_dcr.sv
View file

@ -8,7 +8,7 @@ module VX_tex_dcr #(
input wire reset,
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
// Output
input wire [`TEX_STAGE_BITS-1:0] stage,
@ -26,34 +26,34 @@ module VX_tex_dcr #(
// DCRs write
always @(posedge clk) begin
if (dcr_write_if.valid) begin
case (dcr_write_if.addr)
if (dcr_bus_if.write_valid) begin
case (dcr_bus_if.write_addr)
`DCR_TEX_STAGE: begin
dcr_stage <= dcr_write_if.data[$clog2(NUM_STAGES)-1:0];
dcr_stage <= dcr_bus_if.write_data[$clog2(NUM_STAGES)-1:0];
end
`DCR_TEX_ADDR: begin
dcrs[dcr_stage].baseaddr <= dcr_write_if.data[`TEX_ADDR_BITS-1:0];
dcrs[dcr_stage].baseaddr <= dcr_bus_if.write_data[`TEX_ADDR_BITS-1:0];
end
`DCR_TEX_FORMAT: begin
dcrs[dcr_stage].format <= dcr_write_if.data[`TEX_FORMAT_BITS-1:0];
dcrs[dcr_stage].format <= dcr_bus_if.write_data[`TEX_FORMAT_BITS-1:0];
end
`DCR_TEX_FILTER: begin
dcrs[dcr_stage].filter <= dcr_write_if.data[`TEX_FILTER_BITS-1:0];
dcrs[dcr_stage].filter <= dcr_bus_if.write_data[`TEX_FILTER_BITS-1:0];
end
`DCR_TEX_WRAP: begin
dcrs[dcr_stage].wraps[0] <= dcr_write_if.data[0 +: `TEX_WRAP_BITS];
dcrs[dcr_stage].wraps[1] <= dcr_write_if.data[16 +: `TEX_WRAP_BITS];
dcrs[dcr_stage].wraps[0] <= dcr_bus_if.write_data[0 +: `TEX_WRAP_BITS];
dcrs[dcr_stage].wraps[1] <= dcr_bus_if.write_data[16 +: `TEX_WRAP_BITS];
end
`DCR_TEX_LOGDIM: begin
dcrs[dcr_stage].logdims[0] <= dcr_write_if.data[0 +: `TEX_LOD_BITS];
dcrs[dcr_stage].logdims[1] <= dcr_write_if.data[16 +: `TEX_LOD_BITS];
dcrs[dcr_stage].logdims[0] <= dcr_bus_if.write_data[0 +: `TEX_LOD_BITS];
dcrs[dcr_stage].logdims[1] <= dcr_bus_if.write_data[16 +: `TEX_LOD_BITS];
end
default: begin
for (integer j = 0; j <= `TEX_LOD_MAX; ++j) begin
`IGNORE_WARNINGS_BEGIN
if (dcr_write_if.addr == `DCR_TEX_MIPOFF(j)) begin
if (dcr_bus_if.write_addr == `DCR_TEX_MIPOFF(j)) begin
`IGNORE_WARNINGS_END
dcrs[dcr_stage].mipoff[j] <= dcr_write_if.data[`TEX_MIPOFF_BITS-1:0];
dcrs[dcr_stage].mipoff[j] <= dcr_bus_if.write_data[`TEX_MIPOFF_BITS-1:0];
end
end
end
@ -66,10 +66,10 @@ module VX_tex_dcr #(
`ifdef DBG_TRACE_TEX
always @(posedge clk) begin
if (dcr_write_if.valid) begin
if (dcr_bus_if.write_valid) begin
`TRACE(1, ("%d: %s-tex-dcr: stage=%0d, state=", $time, INSTANCE_ID, dcr_stage));
`TRACE_TEX_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
`TRACE_TEX_DCR(1, dcr_bus_if.write_addr);
`TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data));
end
end
`endif

14
hw/rtl/tex/VX_tex_unit.sv
View file

@ -15,7 +15,7 @@ module VX_tex_unit #(
VX_cache_bus_if.master cache_bus_if,
VX_dcr_write_if.slave dcr_write_if,
VX_dcr_bus_if.slave dcr_bus_if,
VX_tex_bus_if.slave tex_bus_if
);
@ -33,7 +33,7 @@ module VX_tex_unit #(
) tex_dcr (
.clk (clk),
.reset (reset),
.dcr_write_if(dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.stage (tex_bus_if.req_stage),
.tex_dcrs (tex_dcrs)
);
@ -311,11 +311,11 @@ module VX_tex_unit_top #(
VX_tex_perf_if perf_tex_if();
VX_dcr_write_if dcr_write_if();
VX_dcr_bus_if dcr_bus_if();
assign dcr_write_if.valid = dcr_write_valid;
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
assign dcr_bus_if.write_valid = dcr_write_valid;
assign dcr_bus_if.write_addr = dcr_write_addr;
assign dcr_bus_if.write_data = dcr_write_data;
VX_tex_bus_if #(
.NUM_LANES (NUM_LANES),
@ -364,7 +364,7 @@ module VX_tex_unit_top #(
`ifdef PERF_ENABLE
.perf_tex_if (perf_tex_if),
`endif
.dcr_write_if (dcr_write_if),
.dcr_bus_if (dcr_bus_if),
.tex_bus_if (tex_bus_if),
.cache_bus_if (cache_bus_if)
);