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https://github.com/vortexgpgpu/vortex.git
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code refactoring
This commit is contained in:
Blaise Tine
parent
4626389ee2
commit
a7eb9a0c38
4 changed files with 84 additions and 104 deletions
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@ -127,7 +127,7 @@
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`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
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//`define SINGLE_CORE_BENCH
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`define SINGLE_CORE_BENCH
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`define GLOBAL_BLOCK_SIZE_BYTES 16
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@ -12,7 +12,6 @@
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// L2 Cache size
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`define LLCACHE_SIZE_BYTES 8192
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// `define QUEUE_FORCE_MLAB 1
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// Use l3 cache (required for cluster behavior)
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170
rtl/Vortex.v
170
rtl/Vortex.v
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@ -2,110 +2,92 @@
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`include "VX_cache_config.v"
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module Vortex
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#(
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#(
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parameter CORE_ID = 0
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)
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(
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`ifdef SINGLE_CORE_BENCH
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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) (
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`ifdef SINGLE_CORE_BENCH
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] dram_expected_lat,
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// Clock
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input wire clk,
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input wire reset,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [31:0] dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] dram_expected_lat,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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// LLC Snooping
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input wire snp_req,
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input wire [31:0] snp_req_addr,
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output wire snp_req_delay,
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output wire out_ebreak
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`else
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
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output wire [31:0] dram_expected_lat,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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// DRAM Icache Req
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output wire I_dram_req,
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output wire I_dram_req_write,
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output wire I_dram_req_read,
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output wire [31:0] I_dram_req_addr,
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output wire [31:0] I_dram_req_size,
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output wire [31:0] I_dram_req_data[`IBANK_LINE_SIZE_RNG],
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output wire [31:0] I_dram_expected_lat,
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// DRAM Icache Req
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output wire I_dram_req,
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output wire I_dram_req_write,
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output wire I_dram_req_read,
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output wire [31:0] I_dram_req_addr,
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output wire [31:0] I_dram_req_size,
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output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
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output wire [31:0] I_dram_expected_lat,
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// DRAM Icache Res
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output wire I_dram_fill_accept,
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input wire I_dram_fill_rsp,
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input wire [31:0] I_dram_fill_rsp_addr,
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input wire [31:0] I_dram_fill_rsp_data[`IBANK_LINE_SIZE_RNG],
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input wire snp_req,
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input wire [31:0] snp_req_addr,
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output wire snp_req_delay,
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input wire I_snp_req,
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input wire [31:0] I_snp_req_addr,
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output wire I_snp_req_delay,
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output wire out_ebreak
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`else
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// DRAM Dcache Req
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`DBANK_LINE_SIZE_RNG][31:0] dram_req_data,
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output wire [31:0] dram_expected_lat,
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// DRAM Dcache Res
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output wire dram_fill_accept,
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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// DRAM Icache Res
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output wire I_dram_fill_accept,
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input wire I_dram_fill_rsp,
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input wire [31:0] I_dram_fill_rsp_addr,
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input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
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// DRAM Icache Req
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output wire I_dram_req,
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output wire I_dram_req_write,
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output wire I_dram_req_read,
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output wire [31:0] I_dram_req_addr,
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output wire [31:0] I_dram_req_size,
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output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
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output wire [31:0] I_dram_expected_lat,
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input wire snp_req,
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input wire [31:0] snp_req_addr,
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output wire snp_req_delay,
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// DRAM Icache Res
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output wire I_dram_fill_accept,
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input wire I_dram_fill_rsp,
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input wire [31:0] I_dram_fill_rsp_addr,
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input wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
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input wire I_snp_req,
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input wire [31:0] I_snp_req_addr,
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output wire I_snp_req_delay,
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input wire snp_req,
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input wire [31:0] snp_req_addr,
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output wire snp_req_delay,
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input wire I_snp_req,
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input wire [31:0] I_snp_req_addr,
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output wire I_snp_req_delay,
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output wire out_ebreak
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`endif
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);
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output wire out_ebreak
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`endif
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);
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wire scheduler_empty;
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wire out_ebreak_unqual;
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@ -3,9 +3,9 @@
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module Vortex_SOC (
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// System Clock
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input wire clk,
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input wire reset,
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid[`NUMBER_CORES-1:0],
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@ -13,7 +13,7 @@ module Vortex_SOC (
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output wire[31:0] number_cores,
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// DRAM Dcache Req
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// DRAM Req
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output wire out_dram_req,
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output wire out_dram_req_write,
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output wire out_dram_req_read,
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@ -22,12 +22,13 @@ module Vortex_SOC (
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output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] out_dram_expected_lat,
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// DRAM Dcache Res
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// DRAM Res
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output wire out_dram_fill_accept,
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input wire out_dram_fill_rsp,
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input wire [31:0] out_dram_fill_rsp_addr,
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input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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// LLC Snooping
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input wire llc_snp_req,
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input wire llc_snp_req_addr,
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output wire llc_snp_req_delay,
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@ -529,7 +530,7 @@ module Vortex_SOC (
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assign io_valid[curr_core] = per_core_io_valid[curr_core];
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assign io_data [curr_core] = per_core_io_data [curr_core];
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Vortex #(.CORE_ID(curr_core)) vortex_core(
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.clk (clk),
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.reset (reset),
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@ -605,8 +606,6 @@ module Vortex_SOC (
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// end
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// endgenerate
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//
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genvar l2c_curr_core;
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generate
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