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bitmanip logceil fix

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This commit is contained in:
Blaise Tine 2024-09-23 23:54:43 -07:00
parent 2cf483ddf5
commit a9a5ded030
4 changed files with 37 additions and 24 deletions
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22
sim/common/bitmanip.h
View file

@ -20,9 +20,9 @@ template <typename T>
constexpr uint32_t count_leading_zeros(T value) {
static_assert(std::is_integral<T>::value, "invalid data type");
if constexpr (sizeof(T) > 4) {
return value ? __builtin_clzll(value) : 64;
return value ? __builtin_clzll(value) : (sizeof(T) * 8);
} else {
return value ? __builtin_clz(value) : 32;
return value ? __builtin_clz(value) : (sizeof(T) * 8);
}
}
@ -30,9 +30,9 @@ template <typename T>
constexpr uint32_t count_trailing_zeros(T value) {
static_assert(std::is_integral<T>::value, "invalid data type");
if constexpr (sizeof(T) > 4) {
return value ? __builtin_ctzll(value) : 64;
return value ? __builtin_ctzll(value) : (sizeof(T) * 8);
} else {
return value ? __builtin_ctz(value) : 32;
return value ? __builtin_ctz(value) : (sizeof(T) * 8);
}
}
@ -45,7 +45,7 @@ constexpr bool ispow2(T value) {
template <typename T>
constexpr uint32_t log2ceil(T value) {
static_assert(std::is_integral<T>::value, "invalid data type");
return (sizeof(T) * 8) - count_leading_zeros(value - 1);
return (sizeof(T) * 8) - count_leading_zeros<T>(value - 1);
}
template <typename T>
@ -57,21 +57,13 @@ inline unsigned log2up(T value) {
template <typename T>
constexpr unsigned log2floor(T value) {
static_assert(std::is_integral<T>::value, "invalid data type");
if constexpr (sizeof(T) > 4) {
return 63 - count_leading_zeros(value);
} else {
return 31 - count_leading_zeros(value);
}
return (sizeof(T) * 8 - 1) - count_leading_zeros<T>(value);
}
template <typename T>
constexpr unsigned ceil2(T value) {
static_assert(std::is_integral<T>::value, "invalid data type");
if constexpr (sizeof(T) > 4) {
return 64 - count_leading_zeros(value);
} else {
return 32 - count_leading_zeros(value);
}
return (sizeof(T) * 8) - count_leading_zeros<T>(value);
}
inline uint64_t bit_clr(uint64_t bits, uint32_t index) {

26
sim/simx/cache_sim.cpp
View file

@ -170,6 +170,25 @@ struct bank_req_t {
}
};
inline std::ostream &operator<<(std::ostream &os, const bank_req_t& req) {
os << "set=" << req.set_id << ", rw=" << req.write;
os << std::dec << ", type=" << req.type;
os << ", tag=0x" << std::hex << req.tag;
os << ", req_tags={";
bool first_port = true;
for (auto& port : req.ports) {
if (port.valid) {
if (!first_port) os << ", ";
first_port = false;
os << "[" << std::dec << port.req_id << "]=0x" << std::hex << port.req_tag;
}
}
os << "}";
os << std::dec << ", cid=" << req.cid;
os << " (#" << req.uuid << ")";
return os;
}
struct mshr_entry_t {
bank_req_t bank_req;
uint32_t line_id;
@ -542,7 +561,7 @@ private:
uint64_t tag = mem_rsp.tag >> params_.log2_num_inputs;
MemRsp core_rsp{tag, mem_rsp.cid, mem_rsp.uuid};
simobject_->CoreRspPorts.at(req_id).push(core_rsp, config_.latency);
DT(3, simobject_->name() << " core-rsp: " << core_rsp);
DT(3, simobject_->name() << " bypass-core-rsp: " << core_rsp);
}
void processBypassRequest(const MemReq& core_req, uint32_t req_id) {
@ -550,13 +569,13 @@ private:
MemReq mem_req(core_req);
mem_req.tag = (core_req.tag << params_.log2_num_inputs) + req_id;
bypass_switch_->ReqIn.at(1).push(mem_req, 1);
DT(3, simobject_->name() << " dram-req: " << mem_req);
DT(3, simobject_->name() << " bypass-dram-req: " << mem_req);
}
if (core_req.write && config_.write_reponse) {
MemRsp core_rsp{core_req.tag, core_req.cid, core_req.uuid};
simobject_->CoreRspPorts.at(req_id).push(core_rsp, 1);
DT(3, simobject_->name() << " core-rsp: " << core_rsp);
DT(3, simobject_->name() << " bypass-core-rsp: " << core_rsp);
}
}
@ -694,6 +713,7 @@ private:
// allocate MSHR
auto mshr_id = bank.mshr.allocate(pipeline_req, (free_line_id != -1) ? free_line_id : repl_line_id);
DT(3, simobject_->name() << "-bank" << bank_id << " mshr-enqueue: " << pipeline_req);
// send fill request
if (!mshr_pending) {

4
sim/simx/mem_sim.cpp
View file

@ -77,7 +77,7 @@ public:
if (!rsp_args->request.write) {
MemRsp mem_rsp{rsp_args->request.tag, rsp_args->request.cid, rsp_args->request.uuid};
rsp_args->simobject->MemRspPorts.at(rsp_args->i).push(mem_rsp, 1);
DT(3, rsp_args->simobject->name() << " mem-rsp: " << mem_rsp << " bank: " << rsp_args->i);
DT(3, rsp_args->simobject->name() << " mem-rsp: bank=" << rsp_args->i << ", " << mem_rsp);
}
delete rsp_args;
},
@ -90,7 +90,7 @@ public:
continue;
}
DT(3, simobject_->name() << " mem-req: " << mem_req << " bank: " << i);
DT(3, simobject_->name() << " mem-req: bank=" << i << ", " << mem_req);
simobject_->MemReqPorts.at(i).pop();
counter++;

9
sim/simx/types.h
View file

@ -281,17 +281,18 @@ struct LsuReq {
};
inline std::ostream &operator<<(std::ostream &os, const LsuReq& req) {
os << "rw=" << req.write << ", mask=" << req.mask << ", ";
os << "rw=" << req.write << ", mask=" << req.mask << ", addr={";
bool first_addr = true;
for (size_t i = 0; i < req.mask.size(); ++i) {
os << "addr" << i << "=";
if (!first_addr) os << ", ";
first_addr = false;
if (req.mask.test(i)) {
os << "0x" << std::hex << req.addrs.at(i) << std::dec;
} else {
os << "-";
}
os << ", ";
}
os << "tag=0x" << std::hex << req.tag << std::dec << ", cid=" << req.cid;
os << "}, tag=0x" << std::hex << req.tag << std::dec << ", cid=" << req.cid;
os << " (#" << req.uuid << ")";
return os;
}