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minor update

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This commit is contained in:
Blaise Tine 2023-07-06 04:18:37 -04:00
parent e5442ef6f4
commit ab63f382da
4 changed files with 103 additions and 75 deletions
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81
hw/rtl/core/VX_ibuffer.sv
View file

@ -15,13 +15,16 @@ module VX_ibuffer #(
);
`UNUSED_PARAM (CORE_ID)
localparam NW_WIDTH = `UP(`NW_BITS);
localparam DATAW = `UP(`UUID_BITS) + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + (`NR_BITS * 4) + `XLEN + 1 + 1;
localparam NW_WIDTH = `UP(`NW_BITS);
localparam UUID_WIDTH = `UP(`UUID_BITS);
localparam DATAW = UUID_WIDTH + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + (`NR_BITS * 4) + `XLEN + 1 + 1;
wire [`NUM_WARPS-1:0][DATAW-1:0] q_data_out;
wire [DATAW-1:0] q_data_in;
wire [`NUM_WARPS-1:0] q_full, q_empty;
wire [`NUM_WARPS-1:0] deq_valid_in, deq_ready_in;
wire [`NUM_WARPS-1:0] q_full, q_empty, q_alm_empty;
wire enq_fire = decode_if.valid && decode_if.ready;
wire deq_fire = ibuffer_if.valid && ibuffer_if.ready;
assign q_data_in = {decode_if.uuid,
decode_if.tmask,
@ -40,8 +43,8 @@ module VX_ibuffer #(
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
wire q_push = decode_if.valid && decode_if.ready && (i == decode_if.wid);
wire q_pop = deq_valid_in[i] && deq_ready_in[i];
wire q_push = enq_fire && (i == decode_if.wid);
wire q_pop = deq_fire && (i == ibuffer_if.wid);
VX_fifo_queue #(
.DATAW (DATAW),
@ -56,8 +59,8 @@ module VX_ibuffer #(
.data_out (q_data_out[i]),
.full (q_full[i]),
.empty (q_empty[i]),
.alm_empty (q_alm_empty[i]),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
@ -70,6 +73,9 @@ module VX_ibuffer #(
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
assign scoreboard_if.valid[i] = ~q_empty[i];
assign scoreboard_if.uuid[i] = q_data_out[i][DATAW-1 -: UUID_WIDTH];
assign scoreboard_if.tmask[i] = q_data_out[i][DATAW-UUID_WIDTH-1 -: `NUM_THREADS];
assign scoreboard_if.PC[i] = q_data_out[i][DATAW-UUID_WIDTH-`NUM_THREADS-1 -: `XLEN];
assign scoreboard_if.rd[i] = q_data_out[i][3*`NR_BITS +: `NR_BITS];
assign scoreboard_if.rs1[i] = q_data_out[i][2*`NR_BITS +: `NR_BITS];
assign scoreboard_if.rs2[i] = q_data_out[i][1*`NR_BITS +: `NR_BITS];
@ -78,28 +84,44 @@ module VX_ibuffer #(
// round-robin select
wire [`NUM_WARPS-1:0][(NW_WIDTH+DATAW)-1:0] deq_data_in;
reg [`NUM_WARPS-1:0] valid_table_n, scb_ready;
logic deq_valid, deq_valid_n;
logic [NW_WIDTH-1:0] deq_wid, deq_wid_n;
reg [DATAW-1:0] deq_instr;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
assign deq_valid_in[i] = scoreboard_if.valid[i] && scoreboard_if.ready[i];
assign deq_data_in[i] = {NW_WIDTH'(i), q_data_out[i]};
end
always @(*) begin
valid_table_n = scoreboard_if.valid;
if (deq_fire) begin
valid_table_n[ibuffer_if.wid] = ~q_alm_empty[ibuffer_if.wid];
end
end
VX_rr_arbiter #(
.NUM_REQS (`NUM_WARPS)
) rr_arbiter (
.clk (clk),
.reset (reset),
.requests (valid_table_n),
.grant_index (deq_wid_n),
.grant_valid (deq_valid_n),
`UNUSED_PIN (grant_onehot),
`UNUSED_PIN (unlock)
);
VX_stream_arb #(
.NUM_INPUTS (`NUM_WARPS),
.DATAW (NW_WIDTH+DATAW),
.ARBITER ("R"),
.LOCK_ENABLE (0),
.BUFFERED (2)
) req_arb (
.clk (clk),
.reset (reset),
.valid_in (deq_valid_in),
.ready_in (deq_ready_in),
.data_in (deq_data_in),
.data_out ({
ibuffer_if.wid,
ibuffer_if.uuid,
always @(posedge clk) begin
if (reset) begin
deq_valid <= 0;
end else begin
deq_valid <= deq_valid_n;
end
deq_wid <= deq_wid_n;
deq_instr <= q_data_out[deq_wid_n];
scb_ready <= scoreboard_if.ready;
end
assign ibuffer_if.valid = deq_valid && scb_ready[deq_wid];
assign ibuffer_if.wid = deq_wid;
assign {ibuffer_if.uuid,
ibuffer_if.tmask,
ibuffer_if.PC,
ibuffer_if.ex_type,
@ -112,9 +134,6 @@ module VX_ibuffer #(
ibuffer_if.rd,
ibuffer_if.rs1,
ibuffer_if.rs2,
ibuffer_if.rs3}),
.valid_out (ibuffer_if.valid),
.ready_out (ibuffer_if.ready)
);
ibuffer_if.rs3} = deq_instr;
endmodule

45
hw/rtl/core/VX_issue.sv
View file

@ -29,7 +29,6 @@ module VX_issue #(
VX_ibuffer_if ibuffer_if();
VX_scoreboard_if scoreboard_if();
VX_gpr_stage_if gpr_stage_if();
wire [3:0] used_regs;
`RESET_RELAY (ibuf_reset, reset);
`RESET_RELAY (scoreboard_reset, reset);
@ -53,8 +52,7 @@ module VX_issue #(
.reset (scoreboard_reset),
.writeback_if (writeback_if),
.scoreboard_if (scoreboard_if),
.ibuffer_if (ibuffer_if),
.used_regs (used_regs)
.ibuffer_if (ibuffer_if)
);
VX_gpr_stage #(
@ -79,42 +77,18 @@ module VX_issue #(
.fpu_exe_if (fpu_exe_if),
`endif
.gpu_exe_if (gpu_exe_if)
);
wire ibuffer_if_fire = ibuffer_if.valid && ibuffer_if.ready;
reg [31:0] timeout_ctr;
always @(posedge clk) begin
if (reset) begin
timeout_ctr <= '0;
end else begin
if (ibuffer_if.valid && ~ibuffer_if.ready) begin
`ifdef DBG_TRACE_CORE_PIPELINE
`TRACE(3, ("%d: *** core%0d-stall: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, wb=%0d, cycles=%0d, inuse=%b%b%b%b, dispatch=%b (#%0d)\n",
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb, timeout_ctr,
used_regs[0], used_regs[1], used_regs[2], used_regs[3], ~ibuffer_if.ready, ibuffer_if.uuid));
`endif
timeout_ctr <= timeout_ctr + 1;
end else if (ibuffer_if_fire) begin
timeout_ctr <= '0;
end
end
end
`RUNTIME_ASSERT(timeout_ctr < `STALL_TIMEOUT,
("%t: *** core%0d-issue-timeout: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, wb=%0d, inuse=%b%b%b%b, dispatch=%b (#%0d)",
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb,
used_regs[0], used_regs[1], used_regs[2], used_regs[3], ~ibuffer_if.ready, ibuffer_if.uuid));
);
`ifdef DBG_SCOPE_ISSUE
if (CORE_ID == 0) begin
`ifdef SCOPE
localparam UUID_WIDTH = `UP(`UUID_BITS);
wire scoreboard_if_not_ready = ~scoreboard_if.ready;
wire ibuffer_if_fire = ibuffer_if.valid && ibuffer_if.ready;
wire ibuffer_if_not_ready = ~ibuffer_if.ready;
wire writeback_if_valid = writeback_if.valid;
VX_scope_tap #(
.SCOPE_ID (2),
.TRIGGERW (5),
.TRIGGERW (4),
.PROBEW (UUID_WIDTH + `NUM_THREADS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS +
1 + (`NR_BITS * 4) + `XLEN + 1 + 1 + (`NUM_THREADS * 3 * `XLEN) +
UUID_WIDTH + `NUM_THREADS + `NR_BITS + (`NUM_THREADS*`XLEN) + 1)
@ -125,8 +99,7 @@ module VX_issue #(
.stop(1'b0),
.triggers({
reset,
ibuffer_if_fire,
scoreboard_if_not_ready,
ibuffer_if_fire,
ibuffer_if_not_ready,
writeback_if_valid
}),
@ -144,9 +117,9 @@ module VX_issue #(
ibuffer_if.imm,
ibuffer_if.use_PC,
ibuffer_if.use_imm,
ibuffer_if.rs1_data,
ibuffer_if.rs2_data,
ibuffer_if.rs3_data,
gpr_stage_if.rs1_data,
gpr_stage_if.rs2_data,
gpr_stage_if.rs3_data,
writeback_if.uuid,
writeback_if.tmask,
writeback_if.rd,
@ -160,7 +133,7 @@ module VX_issue #(
`ifdef CHIPSCOPE
ila_issue ila_issue_inst (
.clk (clk),
.probe0 ({ibuffer_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.wid, ibuffer_if.ex_type, ibuffer_if.op_type, ibuffer_if.ready, ibuffer_if.valid, used_regs, scoreboard_if.ready, ibuffer_if.ready, ibuffer_if.ready, ibuffer_if.valid}),
.probe0 ({ibuffer_if.uuid, ibuffer.rs3, ibuffer.rs2, ibuffer.rs1, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.wid, ibuffer_if.ex_type, ibuffer_if.op_type, ibuffer_if.ready, ibuffer_if.valid}),
.probe1 ({writeback_if.uuid, writeback_if.data[0], writeback_if.PC, writeback_if.tmask, writeback_if.wid, writeback_if.eop, writeback_if.valid})
);
`endif

43
hw/rtl/core/VX_scoreboard.sv
View file

@ -8,9 +8,10 @@ module VX_scoreboard #(
VX_writeback_if.slave writeback_if,
VX_scoreboard_if.slave scoreboard_if,
VX_ibuffer_if.scoreboard ibuffer_if,
output wire [3:0] used_regs
VX_ibuffer_if.scoreboard ibuffer_if
);
`UNUSED_PARAM (CORE_ID)
localparam NW_WIDTH = `UP(`NW_BITS);
reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
@ -43,7 +44,9 @@ module VX_scoreboard #(
| inuse_regs_n[i][scoreboard_if.rs3[i]]);
end
reg [31:0] timeout_ctr;
wire [NW_WIDTH-1:0] wid_sel;
VX_lzc #(
.N (`NUM_WARPS),
.REVERSE (1)
@ -51,14 +54,38 @@ module VX_scoreboard #(
.data_in (scoreboard_if.valid),
.data_out (wid_sel),
`UNUSED_PIN (valid_out)
);
);
assign used_regs[0] = inuse_regs_n[wid_sel][scoreboard_if.rd[wid_sel]];
assign used_regs[1] = inuse_regs_n[wid_sel][scoreboard_if.rs1[wid_sel]];
assign used_regs[2] = inuse_regs_n[wid_sel][scoreboard_if.rs2[wid_sel]];
assign used_regs[3] = inuse_regs_n[wid_sel][scoreboard_if.rs3[wid_sel]];
wire used_rd = inuse_regs_n[wid_sel][scoreboard_if.rd[wid_sel]];
wire used_rs1 = inuse_regs_n[wid_sel][scoreboard_if.rs1[wid_sel]];
wire used_rs2 = inuse_regs_n[wid_sel][scoreboard_if.rs2[wid_sel]];
wire used_rs3 = inuse_regs_n[wid_sel][scoreboard_if.rs3[wid_sel]];
always @(posedge clk) begin
wire [`NUM_WARPS-1:0] scoreboard_fire = scoreboard_if.valid & scoreboard_if.ready;
always @(posedge clk) begin
if (reset) begin
timeout_ctr <= '0;
end else begin
if (scoreboard_if.valid != 0 && scoreboard_fire == 0) begin
`ifdef DBG_TRACE_CORE_PIPELINE
`TRACE(3, ("%d: *** core%0d-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b%b%b%b (#%0d)\n",
$time, CORE_ID, wid_sel, scoreboard_if.PC[wid_sel], scoreboard_if.tmask[wid_sel], timeout_ctr,
used_rd, used_rs1, used_rs2, used_rs3, scoreboard_if.uuid[wid_sel]));
`endif
timeout_ctr <= timeout_ctr + 1;
end else if (scoreboard_fire != 0) begin
timeout_ctr <= '0;
end
end
end
`RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT),
("%t: *** core%0d-issue-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b%b%b%b (#%0d)",
$time, CORE_ID, wid_sel, scoreboard_if.PC[wid_sel], scoreboard_if.tmask[wid_sel], timeout_ctr,
used_rd, used_rs1, used_rs2, used_rs3, scoreboard_if.uuid[wid_sel]));
always @(posedge clk) begin
if (release_reg) begin
`ASSERT(inuse_regs[writeback_if.wid][writeback_if.rd] != 0,
("%t: *** core%0d: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",

9
hw/rtl/interfaces/VX_scoreboard_if.sv
View file

@ -3,6 +3,9 @@
interface VX_scoreboard_if ();
wire [`NUM_WARPS-1:0] valid;
wire [`NUM_WARPS-1:0][`UP(`UUID_BITS)-1:0] uuid;
wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] tmask;
wire [`NUM_WARPS-1:0][`XLEN-1:0] PC;
wire [`NUM_WARPS-1:0][`NR_BITS-1:0] rd;
wire [`NUM_WARPS-1:0][`NR_BITS-1:0] rs1;
wire [`NUM_WARPS-1:0][`NR_BITS-1:0] rs2;
@ -11,6 +14,9 @@ interface VX_scoreboard_if ();
modport master (
output valid,
output uuid,
output tmask,
output PC,
output rd,
output rs1,
output rs2,
@ -20,6 +26,9 @@ interface VX_scoreboard_if ();
modport slave (
input valid,
input uuid,
input tmask,
input PC,
input rd,
input rs1,
input rs2,