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minor update

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This commit is contained in:
Blaise Tine 2024-10-20 20:07:34 -07:00
parent 0f380a3d78
commit acc1e3dfd8
14 changed files with 76 additions and 73 deletions
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2
hw/rtl/VX_cluster.sv
View file

@ -154,6 +154,6 @@ module VX_cluster import VX_gpu_pkg::*; #(
);
end
`BUFFER_EX(busy, (| per_socket_busy), 1'b1, (`NUM_SOCKETS > 1));
`BUFFER_EX(busy, (| per_socket_busy), 1'b1, 1, (`NUM_SOCKETS > 1));
endmodule

6
hw/rtl/VX_define.vh
View file

@ -335,10 +335,10 @@
.data_out (dst) \
)
`define BUFFER_EX(dst, src, ena, latency) \
`define BUFFER_EX(dst, src, ena, RSTW, latency) \
VX_pipe_register #( \
.DATAW ($bits(dst)), \
.RESETW ($bits(dst)), \
.RESETW (RSTW), \
.DEPTH (latency) \
) __``dst``__ ( \
.clk (clk), \
@ -348,7 +348,7 @@
.data_out (dst) \
)
`define BUFFER(dst, src) `BUFFER_EX(dst, src, 1'b1, 1)
`define BUFFER(dst, src) `BUFFER_EX(dst, src, 1'b1, 0, 1)
`define POP_COUNT_EX(out, in, model) \
VX_popcount #( \

2
hw/rtl/VX_socket.sv
View file

@ -237,6 +237,6 @@ module VX_socket import VX_gpu_pkg::*; #(
);
end
`BUFFER_EX(busy, (| per_core_busy), 1'b1, (`SOCKET_SIZE > 1));
`BUFFER_EX(busy, (| per_core_busy), 1'b1, 1, (`SOCKET_SIZE > 1));
endmodule

2
hw/rtl/Vortex.sv
View file

@ -159,7 +159,7 @@ module Vortex import VX_gpu_pkg::*; (
);
end
`BUFFER_EX(busy, (| per_cluster_busy), 1'b1, (`NUM_CLUSTERS > 1));
`BUFFER_EX(busy, (| per_cluster_busy), 1'b1, 1, (`NUM_CLUSTERS > 1));
`ifdef PERF_ENABLE

2
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -461,7 +461,7 @@ module VX_cache_bank #(
.write_word (write_word_st0),
.word_idx (word_idx_st0),
.write_byteen(byteen_st0),
.way_idx (way_idx_st1),
.way_idx_r (way_idx_st1),
// outputs
.read_data (read_data_st1),
.evict_byteen(evict_byteen_st1)

8
hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -47,7 +47,7 @@ module VX_cache_data #(
input wire [`CS_WORD_WIDTH-1:0] write_word,
input wire [WORD_SIZE-1:0] write_byteen,
input wire [`UP(`CS_WORD_SEL_BITS)-1:0] word_idx,
input wire [`CS_WAY_SEL_WIDTH-1:0] way_idx,
input wire [`CS_WAY_SEL_WIDTH-1:0] way_idx_r,
// outputs
output wire [`CS_LINE_WIDTH-1:0] read_data,
output wire [LINE_SIZE-1:0] evict_byteen
@ -94,11 +94,11 @@ module VX_cache_data #(
.rdata (byteen_rdata)
);
assign evict_byteen = byteen_rdata[way_idx];
assign evict_byteen = byteen_rdata[way_idx_r];
end else begin : g_no_dirty_bytes
`UNUSED_VAR (init)
`UNUSED_VAR (flush)
assign evict_byteen = '0;
assign evict_byteen = '1; // update whole line
end
wire [NUM_WAYS-1:0][`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] line_rdata;
@ -167,6 +167,6 @@ module VX_cache_data #(
end
end
assign read_data = line_rdata[way_idx];
assign read_data = line_rdata[way_idx_r];
endmodule

7
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -66,12 +66,13 @@ module VX_cache_tags #(
for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_tag_store
wire way_en = (NUM_WAYS == 1) || (evict_way == i);
wire do_init = init; // init all ways
wire do_fill = fill && way_en;
wire do_flush = flush && (!WRITEBACK || way_en); // flush the whole line in writethrough mode
wire do_write = WRITEBACK && write && tag_matches[i]; // only write on hit
wire do_write = WRITEBACK && write && tag_matches[i]; // only write on tag hit
//wire line_read = read || write || (WRITEBACK && (fill || flush));
wire line_write = init || do_fill || do_flush || do_write;
wire line_write = do_init || do_fill || do_flush || do_write;
wire line_valid = fill || write;
wire [TAG_WIDTH-1:0] line_wdata;
@ -90,7 +91,7 @@ module VX_cache_tags #(
.DATAW (TAG_WIDTH),
.SIZE (`CS_LINES_PER_BANK),
.OUT_REG (1),
.NEW_DATA (1)
.RDW_MODE ("W")
) tag_store (
.clk (clk),
.reset (reset),

12
hw/rtl/core/VX_operands.sv
View file

@ -61,7 +61,7 @@ module VX_operands import VX_gpu_pkg::*; #(
wire [NUM_BANKS-1:0] gpr_rd_valid, gpr_rd_ready;
wire [NUM_BANKS-1:0] gpr_rd_valid_st1, gpr_rd_valid_st2;
wire [NUM_BANKS-1:0][PER_BANK_ADDRW-1:0] gpr_rd_addr, gpr_rd_addr_st1;
wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st2;
wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data_st1, gpr_rd_data_st2;
wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rd_req_idx, gpr_rd_req_idx_st1, gpr_rd_req_idx_st2;
wire pipe_ready_in;
@ -178,14 +178,14 @@ module VX_operands import VX_gpu_pkg::*; #(
wire pipe_valid2_st1 = pipe_valid_st1 && ~has_collision_st1;
VX_pipe_buffer #(
.DATAW (NUM_BANKS + META_DATAW + NUM_BANKS * REQ_SEL_WIDTH)
.DATAW (NUM_BANKS * (1 + REQ_SEL_WIDTH + REGS_DATAW) + META_DATAW)
) pipe_reg2 (
.clk (clk),
.reset (reset),
.valid_in (pipe_valid2_st1),
.ready_in (pipe_ready_st1),
.data_in ({gpr_rd_valid_st1, pipe_data_st1, gpr_rd_req_idx_st1}),
.data_out ({gpr_rd_valid_st2, pipe_data_st2, gpr_rd_req_idx_st2}),
.data_in ({gpr_rd_valid_st1, gpr_rd_req_idx_st1, gpr_rd_data_st1, pipe_data_st1}),
.data_out ({gpr_rd_valid_st2, gpr_rd_req_idx_st2, gpr_rd_data_st2, pipe_data_st2}),
.valid_out(pipe_valid_st2),
.ready_out(pipe_ready_st2)
);
@ -270,7 +270,7 @@ module VX_operands import VX_gpu_pkg::*; #(
`ifdef GPR_RESET
.RESET_RAM (1),
`endif
.OUT_REG (1)
.OUT_REG (0)
) gpr_ram (
.clk (clk),
.reset (reset),
@ -280,7 +280,7 @@ module VX_operands import VX_gpu_pkg::*; #(
.waddr (gpr_wr_addr),
.wdata (writeback_if.data.data),
.raddr (gpr_rd_addr_st1[b]),
.rdata (gpr_rd_data_st2[b])
.rdata (gpr_rd_data_st1[b])
);
end

2
hw/rtl/core/VX_schedule.sv
View file

@ -388,7 +388,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
wire no_pending_instr = (& pending_warp_empty);
`BUFFER_EX(busy, (active_warps != 0 || ~no_pending_instr), 1'b1, 1);
`BUFFER_EX(busy, (active_warps != 0 || ~no_pending_instr), 1'b1, 1, 1);
// export CSRs
assign sched_csr_if.cycles = cycles;

4
hw/rtl/core/VX_scoreboard.sv
View file

@ -62,8 +62,8 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
.data_out (perf_sfu_per_cycle)
);
`BUFFER_EX(perf_units_per_cycle_r, perf_units_per_cycle, 1'b1, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT));
`BUFFER_EX(perf_sfu_per_cycle_r, perf_sfu_per_cycle, 1'b1, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT));
`BUFFER_EX(perf_units_per_cycle_r, perf_units_per_cycle, 1'b1, 0, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT));
`BUFFER_EX(perf_sfu_per_cycle_r, perf_sfu_per_cycle, 1'b1, 0, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT));
wire [PER_ISSUE_WARPS-1:0] stg_valid_in;
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_stg_valid_in

53
hw/rtl/libs/VX_dp_ram.sv
View file

@ -19,10 +19,9 @@ module VX_dp_ram #(
parameter SIZE = 1,
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter RW_ASSERT = 0,
parameter `STRING RDW_MODE = "R", // R: read-first, W: write-first
parameter RDW_ASSERT = 0,
parameter RESET_RAM = 0,
parameter NEW_DATA = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
@ -41,7 +40,8 @@ module VX_dp_ram #(
localparam WSELW = DATAW / WRENW;
`STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter"))
`UNUSED_PARAM (RW_ASSERT)
`STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W"), ("invalid parameter"))
`UNUSED_PARAM (RDW_ASSERT)
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin : g_init \
@ -73,16 +73,17 @@ module VX_dp_ram #(
end
`endif
if (OUT_REG) begin : g_sync
if (NEW_DATA) begin : g_new_data
wire cs = read || write;
if (RDW_MODE == "W") begin : g_new_data
(* rw_addr_collision = "yes" *) `RAM_ARRAY
`UNUSED_VAR (wren)
`RAM_INITIALIZATION
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE
end
if (read) begin
if (cs) begin
if (write) begin
`RAM_WRITE
end
addr_reg <= raddr;
end
end
@ -92,18 +93,19 @@ module VX_dp_ram #(
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (write) begin
`RAM_WRITE
end
if (read) begin
if (cs) begin
if (write) begin
`RAM_WRITE
end
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end
end else begin : g_async
if (NO_RWCHECK) begin : g_no_rwcehck
`NO_RW_RAM_CHECK `RAM_ARRAY
`UNUSED_VAR (read)
if (RDW_MODE == "W") begin : g_new_data
`RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
@ -111,8 +113,8 @@ module VX_dp_ram #(
end
end
assign rdata = ram[raddr];
end else begin : g_rwcheck
`RAM_ARRAY
end else begin : g_old_data
`NO_RW_RAM_CHECK `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
@ -142,10 +144,11 @@ module VX_dp_ram #(
end
if (OUT_REG) begin : g_sync
if (NEW_DATA) begin : g_new_data
wire cs = read || write;
if (RDW_MODE == "W") begin : g_new_data
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (read) begin
if (cs) begin
addr_reg <= raddr;
end
end
@ -153,14 +156,17 @@ module VX_dp_ram #(
end else begin : g_old_data
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (read) begin
if (cs) begin
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end
end else begin : g_async
if (NO_RWCHECK) begin : g_no_rwcheck
`UNUSED_VAR (read)
if (RDW_MODE == "W") begin : g_new_data
assign rdata = ram[raddr];
end else begin : g_old_data
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
@ -178,12 +184,9 @@ module VX_dp_ram #(
end
assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
if (RW_ASSERT) begin : g_rw_asert
if (RDW_ASSERT) begin : g_rw_asert
`RUNTIME_ASSERT(~read || (rdata == ram[raddr]), ("%t: read after write hazard", $time))
end
end else begin : g_rwcheck
`UNUSED_VAR (read)
assign rdata = ram[raddr];
end
end
`endif

2
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -105,7 +105,7 @@ module VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (DEPTH),
.OUT_REG (USE_BRAM),
.NEW_DATA (1)
.RDW_MODE ("W")
) dp_ram (
.clk (clk),
.reset (reset),

8
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -16,7 +16,7 @@
`TRACING_OFF
module VX_generic_arbiter #(
parameter NUM_REQS = 1,
parameter `STRING TYPE = "P",
parameter `STRING TYPE = "P", // P: priority, R: round-robin, M: matrix, C: cyclic
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
@ -27,6 +27,8 @@ module VX_generic_arbiter #(
output wire grant_valid,
input wire grant_ready
);
`STATIC_ASSERT((TYPE == "P" || TYPE == "R" || TYPE == "M" || TYPE == "C"), ("invalid parameter"))
if (TYPE == "P") begin : g_priority
`UNUSED_VAR (clk)
@ -84,10 +86,6 @@ module VX_generic_arbiter #(
.grant_ready (grant_ready)
);
end else begin : g_invalid
`ERROR(("invalid parameter"));
end
`RUNTIME_ASSERT (((~(| requests) != 1) || (grant_valid && (requests[grant_index] != 0) && (grant_onehot == (NUM_REQS'(1) << grant_index)))), ("%t: invalid arbiter grant!", $time))

39
hw/rtl/libs/VX_sp_ram.sv
View file

@ -19,10 +19,9 @@ module VX_sp_ram #(
parameter SIZE = 1,
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter RW_ASSERT = 0,
parameter `STRING RDW_MODE = "R", // R: read-first, W: write-first, N: no-change
parameter RDW_ASSERT = 0,
parameter RESET_RAM = 0,
parameter `STRING WRITE_MODE = "R", // R: read-first, W: write-first, N: no-change
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
@ -40,7 +39,8 @@ module VX_sp_ram #(
localparam WSELW = DATAW / WRENW;
`STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter"))
`UNUSED_PARAM (RW_ASSERT)
`STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W" || RDW_MODE == "N"), ("invalid parameter"))
`UNUSED_PARAM (RDW_ASSERT)
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin : g_init \
@ -73,7 +73,7 @@ module VX_sp_ram #(
`endif
if (OUT_REG) begin : g_sync
wire cs = read || write;
if (WRITE_MODE == "R") begin : g_read_first
if (RDW_MODE == "R") begin : g_read_first
`RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
@ -86,7 +86,7 @@ module VX_sp_ram #(
end
end
assign rdata = rdata_r;
end else if (WRITE_MODE == "W") begin : g_write_first
end else if (RDW_MODE == "W") begin : g_write_first
`UNUSED_VAR (wren)
`RAM_ARRAY
`RAM_INITIALIZATION
@ -100,7 +100,7 @@ module VX_sp_ram #(
end
end
assign rdata = ram[addr_reg];
end else if (WRITE_MODE == "N") begin : g_no_change
end else if (RDW_MODE == "N") begin : g_no_change
`RAM_ARRAY
`RAM_INITIALIZATION
reg [DATAW-1:0] rdata_r;
@ -116,8 +116,9 @@ module VX_sp_ram #(
assign rdata = rdata_r;
end
end else begin : g_async
if (NO_RWCHECK) begin : g_no_rwcehck
`NO_RW_RAM_CHECK `RAM_ARRAY
`UNUSED_VAR (read)
if (RDW_MODE == "W") begin : g_rwcehck
`RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
@ -125,8 +126,8 @@ module VX_sp_ram #(
end
end
assign rdata = ram[addr];
end else begin : g_rwcheck
`RAM_ARRAY
end else begin : g_no_rwcheck
`NO_RW_RAM_CHECK `RAM_ARRAY
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
@ -156,7 +157,7 @@ module VX_sp_ram #(
end
if (OUT_REG) begin : g_sync
if (WRITE_MODE == "R") begin : g_read_first
if (RDW_MODE == "R") begin : g_read_first
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (read || write) begin
@ -164,7 +165,7 @@ module VX_sp_ram #(
end
end
assign rdata = rdata_r;
end else if (WRITE_MODE == "W") begin : g_write_first
end else if (RDW_MODE == "W") begin : g_write_first
reg [ADDRW-1:0] addr_reg;
always @(posedge clk) begin
if (read || write) begin
@ -172,7 +173,7 @@ module VX_sp_ram #(
end
end
assign rdata = ram[addr_reg];
end else if (WRITE_MODE == "N") begin : g_no_change
end else if (RDW_MODE == "N") begin : g_no_change
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (read && ~write) begin
@ -182,7 +183,10 @@ module VX_sp_ram #(
assign rdata = rdata_r;
end
end else begin : g_async
if (NO_RWCHECK) begin : g_no_rwcheck
`UNUSED_VAR (read)
if (RDW_MODE == "W") begin : g_rwcheck
assign rdata = ram[addr];
end else begin : g_no_rwcheck
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
@ -198,12 +202,9 @@ module VX_sp_ram #(
end
end
assign rdata = (prev_write && (prev_waddr == addr)) ? prev_data : ram[addr];
if (RW_ASSERT) begin : g_rw_asert
if (RDW_ASSERT) begin : g_rw_asert
`RUNTIME_ASSERT(~read || (rdata == ram[addr]), ("%t: read after write hazard", $time))
end
end else begin : g_rwcheck
`UNUSED_VAR (read)
assign rdata = ram[addr];
end
end
`endif