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minor update

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This commit is contained in:
Blaise Tine 2024-03-25 15:01:40 -07:00
parent 896aa6b2a1
commit ae12b45f77
6 changed files with 19 additions and 19 deletions
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10
hw/rtl/core/VX_csr_data.sv
View file

@ -38,7 +38,7 @@ import VX_fpu_pkg::*;
VX_commit_csr_if.slave commit_csr_if,
`ifdef EXT_F_ENABLE
VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS],
VX_fpu_csr_if.slave fpu_csr_if [`NUM_FPU_BLOCKS],
`endif
input wire [`PERF_CTR_BITS-1:0] cycles,
@ -71,9 +71,9 @@ import VX_fpu_pkg::*;
wire [`NUM_FPU_BLOCKS-1:0][`NW_WIDTH-1:0] fpu_write_wid;
fflags_t [`NUM_FPU_BLOCKS-1:0] fpu_write_fflags;
for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
assign fpu_write_enable[i] = fpu_to_csr_if[i].write_enable;
assign fpu_write_wid[i] = fpu_to_csr_if[i].write_wid;
assign fpu_write_fflags[i] = fpu_to_csr_if[i].write_fflags;
assign fpu_write_enable[i] = fpu_csr_if[i].write_enable;
assign fpu_write_wid[i] = fpu_csr_if[i].write_wid;
assign fpu_write_fflags[i] = fpu_csr_if[i].write_fflags;
end
always @(*) begin
fcsr_n = fcsr;
@ -94,7 +94,7 @@ import VX_fpu_pkg::*;
end
for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
assign fpu_to_csr_if[i].read_frm = fcsr[fpu_to_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
assign fpu_csr_if[i].read_frm = fcsr[fpu_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
end
always @(posedge clk) begin

4
hw/rtl/core/VX_csr_unit.sv
View file

@ -28,7 +28,7 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
`endif
`ifdef EXT_F_ENABLE
VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS],
VX_fpu_csr_if.slave fpu_csr_if [`NUM_FPU_BLOCKS],
`endif
VX_commit_csr_if.slave commit_csr_if,
@ -88,7 +88,7 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
.thread_masks (sched_csr_if.thread_masks),
`ifdef EXT_F_ENABLE
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_csr_if (fpu_csr_if),
`endif
.read_enable (csr_req_valid && csr_rd_enable),

6
hw/rtl/core/VX_execute.sv
View file

@ -50,7 +50,7 @@ module VX_execute import VX_gpu_pkg::*; #(
);
`ifdef EXT_F_ENABLE
VX_fpu_to_csr_if fpu_to_csr_if[`NUM_FPU_BLOCKS]();
VX_fpu_csr_if fpu_csr_if[`NUM_FPU_BLOCKS]();
`endif
`RESET_RELAY (alu_reset, reset);
@ -90,7 +90,7 @@ module VX_execute import VX_gpu_pkg::*; #(
.reset (fpu_reset),
.dispatch_if (dispatch_if[`EX_FPU * `ISSUE_WIDTH +: `ISSUE_WIDTH]),
.commit_if (commit_if[`EX_FPU * `ISSUE_WIDTH +: `ISSUE_WIDTH]),
.fpu_to_csr_if (fpu_to_csr_if)
.fpu_csr_if (fpu_csr_if)
);
`endif
@ -107,7 +107,7 @@ module VX_execute import VX_gpu_pkg::*; #(
.dispatch_if (dispatch_if[`EX_SFU * `ISSUE_WIDTH +: `ISSUE_WIDTH]),
.commit_if (commit_if[`EX_SFU * `ISSUE_WIDTH +: `ISSUE_WIDTH]),
`ifdef EXT_F_ENABLE
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_csr_if (fpu_csr_if),
`endif
.commit_csr_if (commit_csr_if),
.sched_csr_if (sched_csr_if),

12
hw/rtl/core/VX_fpu_unit.sv
View file

@ -25,7 +25,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
// Outputs
VX_commit_if.master commit_if [`ISSUE_WIDTH],
VX_fpu_to_csr_if.master fpu_to_csr_if[`NUM_FPU_BLOCKS]
VX_fpu_csr_if.master fpu_csr_if[`NUM_FPU_BLOCKS]
);
`UNUSED_PARAM (CORE_ID)
localparam BLOCK_SIZE = `NUM_FPU_BLOCKS;
@ -105,9 +105,9 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
// resolve dynamic FRM from CSR
wire [`INST_FRM_BITS-1:0] fpu_req_frm;
`ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].read_wid, per_block_execute_if[block_idx].data.wid, block_idx, `NUM_FPU_BLOCKS)
`ASSIGN_BLOCKED_WID (fpu_csr_if[block_idx].read_wid, per_block_execute_if[block_idx].data.wid, block_idx, `NUM_FPU_BLOCKS)
assign fpu_req_frm = (per_block_execute_if[block_idx].data.op_type != `INST_FPU_MISC
&& fpu_frm == `INST_FRM_DYN) ? fpu_to_csr_if[block_idx].read_frm : fpu_frm;
&& fpu_frm == `INST_FRM_DYN) ? fpu_csr_if[block_idx].read_frm : fpu_frm;
// submit FPU request
@ -223,9 +223,9 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
assign fpu_rsp_fflags_q = fpu_rsp_fflags;
end
assign fpu_to_csr_if[block_idx].write_enable = fpu_rsp_fire && fpu_rsp_eop && fpu_rsp_has_fflags;
`ASSIGN_BLOCKED_WID (fpu_to_csr_if[block_idx].write_wid, fpu_rsp_wid, block_idx, `NUM_FPU_BLOCKS)
assign fpu_to_csr_if[block_idx].write_fflags = fpu_rsp_fflags_q;
assign fpu_csr_if[block_idx].write_enable = fpu_rsp_fire && fpu_rsp_eop && fpu_rsp_has_fflags;
`ASSIGN_BLOCKED_WID (fpu_csr_if[block_idx].write_wid, fpu_rsp_wid, block_idx, `NUM_FPU_BLOCKS)
assign fpu_csr_if[block_idx].write_fflags = fpu_rsp_fflags_q;
// send response

4
hw/rtl/core/VX_sfu_unit.sv
View file

@ -30,7 +30,7 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH],
`ifdef EXT_F_ENABLE
VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS],
VX_fpu_csr_if.slave fpu_csr_if [`NUM_FPU_BLOCKS],
`endif
VX_commit_csr_if.slave commit_csr_if,
VX_sched_csr_if.slave sched_csr_if,
@ -126,7 +126,7 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
`endif
`ifdef EXT_F_ENABLE
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_csr_if (fpu_csr_if),
`endif
.sched_csr_if (sched_csr_if),

2
hw/rtl/fpu/VX_fpu_to_csr_if.sv → hw/rtl/interfaces/VX_fpu_csr_if.sv
View file

@ -13,7 +13,7 @@
`include "VX_fpu_define.vh"
interface VX_fpu_to_csr_if import VX_fpu_pkg::*; ();
interface VX_fpu_csr_if import VX_fpu_pkg::*; ();
wire write_enable;
wire [`NW_WIDTH-1:0] write_wid;