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renamed rasterizer and render output bus interfaces

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This commit is contained in:
Blaise Tine 2023-06-22 12:22:33 -04:00
parent 09dcf6f4b2
commit b4a2c0204f
16 changed files with 239 additions and 239 deletions
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32
hw/rtl/VX_cluster.sv
View file

@ -111,9 +111,9 @@ module VX_cluster #(
.TAG_WIDTH (RCACHE_TAG_WIDTH)
) rcache_bus_if[`NUM_RASTER_UNITS]();
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (`NUM_THREADS)
) raster_req_if[`NUM_RASTER_UNITS]();
) raster_bus_if[`NUM_RASTER_UNITS]();
VX_dcr_write_if raster_dcr_write_tmp_if();
assign raster_dcr_write_tmp_if.valid = dcr_write_if.valid && (dcr_write_if.addr >= `DCR_RASTER_STATE_BEGIN && dcr_write_if.addr < `DCR_RASTER_STATE_END);
@ -145,14 +145,14 @@ module VX_cluster #(
.perf_raster_if(perf_raster_unit_if[i]),
`endif
.dcr_write_if (raster_dcr_write_if),
.raster_req_if (raster_req_if[i]),
.raster_bus_if (raster_bus_if[i]),
.cache_bus_if (rcache_bus_if[i])
);
end
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (`NUM_THREADS)
) per_socket_raster_req_if[`NUM_SOCKETS]();
) per_socket_raster_bus_if[`NUM_SOCKETS]();
`RESET_RELAY (raster_arb_reset, reset);
@ -165,8 +165,8 @@ module VX_cluster #(
) raster_arb (
.clk (clk),
.reset (raster_arb_reset),
.req_in_if (raster_req_if),
.req_out_if (per_socket_raster_req_if)
.bus_in_if (raster_bus_if),
.bus_out_if (per_socket_raster_bus_if)
);
`endif
@ -183,13 +183,13 @@ module VX_cluster #(
.TAG_WIDTH (OCACHE_TAG_WIDTH)
) ocache_bus_if[`NUM_ROP_UNITS]();
VX_rop_req_if #(
VX_rop_bus_if #(
.NUM_LANES (`NUM_THREADS)
) per_socket_rop_req_if[`NUM_SOCKETS]();
) per_socket_rop_bus_if[`NUM_SOCKETS]();
VX_rop_req_if #(
VX_rop_bus_if #(
.NUM_LANES (`NUM_THREADS)
) rop_req_if[`NUM_ROP_UNITS]();
) rop_bus_if[`NUM_ROP_UNITS]();
`RESET_RELAY (rop_arb_reset, reset);
@ -202,8 +202,8 @@ module VX_cluster #(
) rop_arb (
.clk (clk),
.reset (rop_arb_reset),
.req_in_if (per_socket_rop_req_if),
.req_out_if (rop_req_if)
.bus_in_if (per_socket_rop_bus_if),
.bus_out_if (rop_bus_if)
);
VX_dcr_write_if rop_dcr_write_tmp_if();
@ -228,7 +228,7 @@ module VX_cluster #(
.perf_rop_if (perf_rop_unit_if[i]),
`endif
.dcr_write_if (rop_dcr_write_if),
.rop_req_if (rop_req_if[i]),
.rop_bus_if (rop_bus_if[i]),
.cache_bus_if (ocache_bus_if[i])
);
end
@ -460,7 +460,7 @@ module VX_cluster #(
.perf_raster_if (perf_raster_total_if),
.perf_rcache_if (perf_rcache_total_if),
`endif
.raster_req_if (per_socket_raster_req_if[i]),
.raster_bus_if (per_socket_raster_bus_if[i]),
`endif
`ifdef EXT_ROP_ENABLE
@ -468,7 +468,7 @@ module VX_cluster #(
.perf_rop_if (perf_rop_total_if),
.perf_ocache_if (perf_ocache_total_if),
`endif
.rop_req_if (per_socket_rop_req_if[i]),
.rop_bus_if (per_socket_rop_bus_if[i]),
`endif
.gbar_bus_if (per_socket_gbar_bus_if[i]),

30
hw/rtl/VX_define.vh
View file

@ -383,22 +383,22 @@
assign src.rsp_tag[i] = dst[i].rsp_tag; \
assign dst[i].rsp_ready = src.rsp_ready[i]
`define ASSIGN_VX_RASTER_REQ_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.stamps = src.stamps; \
assign dst.done = src.done; \
assign src.ready = dst.ready
`define ASSIGN_VX_RASTER_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_stamps = src.req_stamps; \
assign dst.req_done = src.req_done; \
assign src.req_ready = dst.req_ready
`define ASSIGN_VX_ROP_REQ_IF(dst, src) \
assign dst.valid = src.valid; \
assign dst.uuid = src.uuid; \
assign dst.mask = src.mask; \
assign dst.pos_x = src.pos_x; \
assign dst.pos_y = src.pos_y; \
assign dst.color = src.color; \
assign dst.depth = src.depth; \
assign dst.face = src.face; \
assign src.ready = dst.ready
`define ASSIGN_VX_ROP_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \
assign dst.req_uuid = src.req_uuid; \
assign dst.req_mask = src.req_mask; \
assign dst.req_pos_x = src.req_pos_x; \
assign dst.req_pos_y = src.req_pos_y; \
assign dst.req_color = src.req_color; \
assign dst.req_depth = src.req_depth; \
assign dst.req_face = src.req_face; \
assign src.req_ready = dst.req_ready
`define ASSIGN_VX_TEX_BUS_IF(dst, src) \
assign dst.req_valid = src.req_valid; \

28
hw/rtl/VX_socket.sv
View file

@ -41,7 +41,7 @@ module VX_socket #(
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
`endif
VX_raster_req_if.slave raster_req_if,
VX_raster_bus_if.slave raster_bus_if,
`endif
`ifdef EXT_ROP_ENABLE
@ -49,7 +49,7 @@ module VX_socket #(
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
`endif
VX_rop_req_if.master rop_req_if,
VX_rop_bus_if.master rop_bus_if,
`endif
VX_gbar_bus_if.master gbar_bus_if,
@ -78,9 +78,9 @@ module VX_socket #(
`ifdef EXT_RASTER_ENABLE
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (`NUM_THREADS)
) per_core_raster_req_if[`SOCKET_SIZE](), raster_req_tmp_if[1]();
) per_core_raster_bus_if[`SOCKET_SIZE](), raster_bus_tmp_if[1]();
`RESET_RELAY (raster_arb_reset, reset);
@ -93,19 +93,19 @@ module VX_socket #(
) raster_arb (
.clk (clk),
.reset (raster_arb_reset),
.req_in_if (raster_req_tmp_if),
.req_out_if (per_core_raster_req_if)
.bus_in_if (raster_bus_tmp_if),
.bus_out_if (per_core_raster_bus_if)
);
`ASSIGN_VX_RASTER_REQ_IF (raster_req_tmp_if[0], raster_req_if);
`ASSIGN_VX_RASTER_BUS_IF (raster_bus_tmp_if[0], raster_bus_if);
`endif
`ifdef EXT_ROP_ENABLE
VX_rop_req_if #(
VX_rop_bus_if #(
.NUM_LANES (`NUM_THREADS)
) per_core_rop_req_if[`SOCKET_SIZE](), rop_req_tmp_if[1]();
) per_core_rop_bus_if[`SOCKET_SIZE](), rop_bus_tmp_if[1]();
`RESET_RELAY (rop_arb_reset, reset);
@ -118,11 +118,11 @@ module VX_socket #(
) rop_arb (
.clk (clk),
.reset (rop_arb_reset),
.req_in_if (per_core_rop_req_if),
.req_out_if (rop_req_tmp_if)
.bus_in_if (per_core_rop_bus_if),
.bus_out_if (rop_bus_tmp_if)
);
`ASSIGN_VX_ROP_REQ_IF (rop_req_if, rop_req_tmp_if[0]);
`ASSIGN_VX_ROP_BUS_IF (rop_bus_if, rop_bus_tmp_if[0]);
`endif
@ -315,7 +315,7 @@ module VX_socket #(
.perf_raster_if (perf_raster_if),
.perf_rcache_if (perf_rcache_if),
`endif
.raster_req_if (per_core_raster_req_if[i]),
.raster_bus_if (per_core_raster_bus_if[i]),
`endif
`ifdef EXT_ROP_ENABLE
@ -323,7 +323,7 @@ module VX_socket #(
.perf_rop_if (perf_rop_if),
.perf_ocache_if (perf_ocache_if),
`endif
.rop_req_if (per_core_rop_req_if[i]),
.rop_bus_if (per_core_rop_bus_if[i]),
`endif
.gbar_bus_if (per_core_gbar_bus_if[i]),

46
hw/rtl/core/VX_core.sv
View file

@ -60,7 +60,7 @@ module VX_core #(
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
`endif
VX_raster_req_if.slave raster_req_if,
VX_raster_bus_if.slave raster_bus_if,
`endif
`ifdef EXT_ROP_ENABLE
@ -68,7 +68,7 @@ module VX_core #(
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
`endif
VX_rop_req_if.master rop_req_if,
VX_rop_bus_if.master rop_bus_if,
`endif
VX_gbar_bus_if.master gbar_bus_if,
@ -214,7 +214,7 @@ module VX_core #(
`endif
`ifdef EXT_RASTER_ENABLE
.raster_req_if (raster_req_if),
.raster_bus_if (raster_bus_if),
`ifdef PERF_ENABLE
.perf_raster_if (perf_raster_if),
.perf_rcache_if (perf_rcache_if),
@ -222,7 +222,7 @@ module VX_core #(
`endif
`ifdef EXT_ROP_ENABLE
.rop_req_if (rop_req_if),
.rop_bus_if (rop_bus_if),
`ifdef PERF_ENABLE
.perf_rop_if (perf_rop_if),
.perf_ocache_if (perf_ocache_if),
@ -554,30 +554,30 @@ module VX_core_top #(
`endif
`ifdef EXT_RASTER_ENABLE
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (`NUM_THREADS)
) raster_req_if();
) raster_bus_if();
assign raster_req_if.valid = raster_req_valid;
assign raster_req_if.stamps = raster_req_stamps;
assign raster_req_if.done = raster_req_done;
assign raster_req_ready = raster_req_if.ready;
assign raster_bus_if.valid = raster_req_valid;
assign raster_bus_if.stamps = raster_req_stamps;
assign raster_bus_if.done = raster_req_done;
assign raster_req_ready = raster_bus_if.ready;
`endif
`ifdef EXT_ROP_ENABLE
VX_rop_req_if #(
VX_rop_bus_if #(
.NUM_LANES (`NUM_THREADS)
) rop_req_if();
) rop_bus_if();
assign rop_req_valid = rop_req_if.valid;
assign rop_req_uuid = rop_req_if.uuid;
assign rop_req_mask = rop_req_if.mask;
assign rop_req_pos_x = rop_req_if.pos_x;
assign rop_req_pos_y = rop_req_if.pos_y;
assign rop_req_color = rop_req_if.color;
assign rop_req_depth = rop_req_if.depth;
assign rop_req_face = rop_req_if.face;
assign rop_req_if.ready = rop_req_ready;
assign rop_req_valid = rop_bus_if.valid;
assign rop_req_uuid = rop_bus_if.uuid;
assign rop_req_mask = rop_bus_if.mask;
assign rop_req_pos_x = rop_bus_if.pos_x;
assign rop_req_pos_y = rop_bus_if.pos_y;
assign rop_req_color = rop_bus_if.color;
assign rop_req_depth = rop_bus_if.depth;
assign rop_req_face = rop_bus_if.face;
assign rop_bus_if.ready = rop_req_ready;
`endif
`ifdef SCOPE
@ -609,11 +609,11 @@ module VX_core_top #(
`endif
`ifdef EXT_RASTER_ENABLE
.raster_req_if (raster_req_if),
.raster_bus_if (raster_bus_if),
`endif
`ifdef EXT_ROP_ENABLE
.rop_req_if (rop_req_if),
.rop_bus_if (rop_bus_if),
`endif
.gbar_bus_if (gbar_bus_if),

8
hw/rtl/core/VX_execute.sv
View file

@ -44,7 +44,7 @@ module VX_execute #(
`endif
`ifdef EXT_RASTER_ENABLE
VX_raster_req_if.slave raster_req_if,
VX_raster_bus_if.slave raster_bus_if,
`ifdef PERF_ENABLE
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
@ -52,7 +52,7 @@ module VX_execute #(
`endif
`ifdef EXT_ROP_ENABLE
VX_rop_req_if.master rop_req_if,
VX_rop_bus_if.master rop_bus_if,
`ifdef PERF_ENABLE
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
@ -219,12 +219,12 @@ module VX_execute #(
`ifdef EXT_RASTER_ENABLE
.raster_csr_if (raster_csr_if),
.raster_req_if (raster_req_if),
.raster_bus_if (raster_bus_if),
`endif
`ifdef EXT_ROP_ENABLE
.rop_csr_if (rop_csr_if),
.rop_req_if (rop_req_if),
.rop_bus_if (rop_bus_if),
`endif
.warp_ctl_if (warp_ctl_if),

8
hw/rtl/core/VX_gpu_unit.sv
View file

@ -25,12 +25,12 @@ module VX_gpu_unit #(
`ifdef EXT_RASTER_ENABLE
VX_gpu_csr_if.slave raster_csr_if,
VX_raster_req_if.slave raster_req_if,
VX_raster_bus_if.slave raster_bus_if,
`endif
`ifdef EXT_ROP_ENABLE
VX_gpu_csr_if.slave rop_csr_if,
VX_rop_req_if.master rop_req_if,
VX_rop_bus_if.master rop_bus_if,
`endif
// Outputs
@ -205,7 +205,7 @@ module VX_gpu_unit #(
.clk (clk),
.reset (raster_reset),
.raster_csr_if (raster_csr_if),
.raster_req_if (raster_req_if),
.raster_bus_if (raster_bus_if),
.raster_agent_if (raster_agent_if),
.raster_commit_if (raster_commit_if)
);
@ -245,7 +245,7 @@ module VX_gpu_unit #(
.rop_csr_if (rop_csr_if),
.rop_agent_if (rop_agent_if),
.rop_commit_if (rop_commit_if),
.rop_req_if (rop_req_if)
.rop_bus_if (rop_bus_if)
);
assign rsp_arb_valid_in[RSP_ARB_IDX_ROP] = rop_commit_if.valid;

26
hw/rtl/raster/VX_raster_agent.sv
View file

@ -8,7 +8,7 @@ module VX_raster_agent #(
// Inputs
VX_raster_agent_if.slave raster_agent_if,
VX_raster_req_if.slave raster_req_if,
VX_raster_bus_if.slave raster_bus_if,
// Outputs
VX_commit_if.master raster_commit_if,
@ -23,7 +23,7 @@ module VX_raster_agent #(
// CSRs access
wire csr_write_enable = raster_req_if.valid && raster_agent_if.valid && raster_rsp_ready;
wire csr_write_enable = raster_bus_if.req_valid && raster_agent_if.valid && raster_rsp_ready;
VX_raster_csr #(
.CORE_ID (CORE_ID)
@ -35,7 +35,7 @@ module VX_raster_agent #(
.write_uuid (raster_agent_if.uuid),
.write_wid (raster_agent_if.wid),
.write_tmask (raster_agent_if.tmask),
.write_data (raster_req_if.stamps),
.write_data (raster_bus_if.req_stamps),
// outputs
.raster_csr_if (raster_csr_if)
);
@ -43,16 +43,16 @@ module VX_raster_agent #(
// it is possible to have ready = f(valid) when using arbiters,
// because of that we need to decouple raster_agent_if and raster_commit_if handshake with a pipe register
assign raster_agent_if.ready = raster_req_if.valid && raster_rsp_ready;
assign raster_agent_if.ready = raster_bus_if.req_valid && raster_rsp_ready;
assign raster_req_if.ready = raster_agent_if.valid && raster_rsp_ready;
assign raster_bus_if.req_ready = raster_agent_if.valid && raster_rsp_ready;
assign raster_rsp_valid = raster_agent_if.valid && raster_req_if.valid;
assign raster_rsp_valid = raster_agent_if.valid && raster_bus_if.req_valid;
wire [`NUM_THREADS-1:0][31:0] response_data;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign response_data[i] = {31'(raster_req_if.stamps[i].pid), ~raster_req_if.done};
assign response_data[i] = {31'(raster_bus_if.req_stamps[i].pid), ~raster_bus_if.req_done};
end
VX_skid_buffer #(
@ -77,12 +77,12 @@ module VX_raster_agent #(
for (integer i = 0; i < `NUM_THREADS; ++i) begin
`TRACE(1, ("%d: core%0d-raster-stamp[%0d]: wid=%0d, PC=0x%0h, tmask=%b, done=%b, x=%0d, y=%0d, mask=%0d, pid=%0d, bcoords={{0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}} (#%0d)\n",
$time, CORE_ID, i, raster_agent_if.wid, raster_agent_if.PC, raster_agent_if.tmask,
raster_req_if.done,
raster_req_if.stamps[i].pos_x, raster_req_if.stamps[i].pos_y, raster_req_if.stamps[i].mask, raster_req_if.stamps[i].pid,
raster_req_if.stamps[i].bcoords[0][0], raster_req_if.stamps[i].bcoords[1][0], raster_req_if.stamps[i].bcoords[2][0],
raster_req_if.stamps[i].bcoords[0][1], raster_req_if.stamps[i].bcoords[1][1], raster_req_if.stamps[i].bcoords[2][1],
raster_req_if.stamps[i].bcoords[0][2], raster_req_if.stamps[i].bcoords[1][2], raster_req_if.stamps[i].bcoords[2][2],
raster_req_if.stamps[i].bcoords[0][3], raster_req_if.stamps[i].bcoords[1][3], raster_req_if.stamps[i].bcoords[2][3], raster_agent_if.uuid));
raster_bus_if.req_done,
raster_bus_if.req_stamps[i].pos_x, raster_bus_if.req_stamps[i].pos_y, raster_bus_if.req_stamps[i].mask, raster_bus_if.req_stamps[i].pid,
raster_bus_if.req_stamps[i].bcoords[0][0], raster_bus_if.req_stamps[i].bcoords[1][0], raster_bus_if.req_stamps[i].bcoords[2][0],
raster_bus_if.req_stamps[i].bcoords[0][1], raster_bus_if.req_stamps[i].bcoords[1][1], raster_bus_if.req_stamps[i].bcoords[2][1],
raster_bus_if.req_stamps[i].bcoords[0][2], raster_bus_if.req_stamps[i].bcoords[1][2], raster_bus_if.req_stamps[i].bcoords[2][2],
raster_bus_if.req_stamps[i].bcoords[0][3], raster_bus_if.req_stamps[i].bcoords[1][3], raster_bus_if.req_stamps[i].bcoords[2][3], raster_agent_if.uuid));
end
end
end

18
hw/rtl/raster/VX_raster_arb.sv
View file

@ -11,10 +11,10 @@ module VX_raster_arb #(
input wire reset,
// input request
VX_raster_req_if.slave req_in_if [NUM_INPUTS],
VX_raster_bus_if.slave bus_in_if [NUM_INPUTS],
// output requests
VX_raster_req_if.master req_out_if [NUM_OUTPUTS]
VX_raster_bus_if.master bus_out_if [NUM_OUTPUTS]
);
localparam REQ_DATAW = NUM_LANES * $bits(raster_stamp_t) + 1;
@ -28,14 +28,14 @@ module VX_raster_arb #(
wire [NUM_INPUTS-1:0] done_mask;
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign done_mask[i] = req_in_if[i].done;
assign done_mask[i] = bus_in_if[i].req_done;
end
wire done_all = (& done_mask);
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign req_valid_in[i] = req_in_if[i].valid;
assign req_data_in[i] = {req_in_if[i].stamps, done_all};
assign req_in_if[i].ready = req_ready_in[i];
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign req_data_in[i] = {bus_in_if[i].req_stamps, done_all};
assign bus_in_if[i].req_ready = req_ready_in[i];
end
VX_stream_arb #(
@ -57,9 +57,9 @@ module VX_raster_arb #(
);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
assign req_out_if[i].valid = req_valid_out[i];
assign {req_out_if[i].stamps, req_out_if[i].done} = req_data_out[i];
assign req_ready_out[i] = req_out_if[i].ready;
assign bus_out_if[i].req_valid = req_valid_out[i];
assign {bus_out_if[i].req_stamps, bus_out_if[i].req_done} = req_data_out[i];
assign req_ready_out[i] = bus_out_if[i].req_ready;
end
endmodule

26
hw/rtl/raster/VX_raster_bus_if.sv Normal file
View file

@ -0,0 +1,26 @@
`include "VX_raster_define.vh"
interface VX_raster_bus_if #(
parameter NUM_LANES = 1
) ();
wire req_valid;
raster_stamp_t [NUM_LANES-1:0] req_stamps;
wire req_done;
wire req_ready;
modport master (
output req_valid,
output req_stamps,
output req_done,
input req_ready
);
modport slave (
input req_valid,
input req_stamps,
input req_done,
output req_ready
);
endinterface

26
hw/rtl/raster/VX_raster_req_if.sv
View file

@ -1,26 +0,0 @@
`include "VX_raster_define.vh"
interface VX_raster_req_if #(
parameter NUM_LANES = 1
) ();
wire valid;
raster_stamp_t [NUM_LANES-1:0] stamps;
wire done;
wire ready;
modport master (
output valid,
output stamps,
output done,
input ready
);
modport slave (
input valid,
input stamps,
input done,
output ready
);
endinterface

70
hw/rtl/raster/VX_raster_unit.sv
View file

@ -29,7 +29,7 @@ module VX_raster_unit #(
VX_dcr_write_if.slave dcr_write_if,
// Outputs
VX_raster_req_if.master raster_req_if
VX_raster_bus_if.master raster_bus_if
);
localparam EDGE_FUNC_LATENCY = `LATENCY_IMUL;
localparam SLICES_BITS = $clog2(NUM_SLICES+1);
@ -199,13 +199,13 @@ module VX_raster_unit #(
|| mem_unit_valid
|| ~no_pending_tiledata;
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (OUTPUT_QUADS)
) slice_raster_req_if[NUM_SLICES]();
) slice_raster_bus_if[NUM_SLICES]();
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (OUTPUT_QUADS)
) raster_req_tmp_if[1]();
) raster_bus_tmp_if[1]();
wire [NUM_SLICES-1:0] slice_valid_in;
wire [NUM_SLICES-1:0] slice_busy_out;
@ -251,19 +251,19 @@ module VX_raster_unit #(
.ready_in (slice_ready_in),
.valid_out (slice_valid_out[i]),
.stamps_out (slice_raster_req_if[i].stamps),
.stamps_out (slice_raster_bus_if[i].req_stamps),
.busy_out (slice_busy_out[i]),
.ready_out (slice_raster_req_if[i].ready)
.ready_out (slice_raster_bus_if[i].req_ready)
);
assign slice_raster_req_if[i].done = running
&& ~has_pending_inputs
&& ~(| slice_valid_in)
&& ~(| slice_busy_out)
&& ~(| slice_valid_out);
assign slice_raster_bus_if[i].req_done = running
&& ~has_pending_inputs
&& ~(| slice_valid_in)
&& ~(| slice_busy_out)
&& ~(| slice_valid_out);
assign slice_raster_req_if[i].valid = slice_valid_out[i]
|| slice_raster_req_if[i].done;
assign slice_raster_bus_if[i].req_valid = slice_valid_out[i]
|| slice_raster_bus_if[i].req_done;
end
`RESET_RELAY (raster_arb_reset, reset);
@ -276,18 +276,18 @@ module VX_raster_unit #(
) raster_arb (
.clk (clk),
.reset (raster_arb_reset),
.req_in_if (slice_raster_req_if),
.req_out_if (raster_req_tmp_if)
.bus_in_if (slice_raster_bus_if),
.bus_out_if (raster_bus_tmp_if)
);
`ASSIGN_VX_RASTER_REQ_IF (raster_req_if, raster_req_tmp_if[0]);
`ASSIGN_VX_RASTER_BUS_IF (raster_bus_if, raster_bus_tmp_if[0]);
`ifdef DBG_SCOPE_RASTER
if (INSTANCE_ID == "cluster0-raster0") begin
`ifdef SCOPE
wire cache_req_fire = cache_bus_if.req_valid && cache_bus_if.req_ready;
wire cache_rsp_fire = cache_bus_if.rsp_valid && cache_bus_if.rsp_ready;
wire raster_req_fire = raster_req_if.valid && raster_req_if.ready;
wire raster_req_fire = raster_bus_if.req_valid && raster_bus_if.req_ready;
VX_scope_tap #(
.SCOPE_ID (4),
.TRIGGERW (9),
@ -306,7 +306,7 @@ module VX_raster_unit #(
mem_unit_ready,
mem_unit_start,
mem_unit_valid,
raster_req_if.done
raster_bus_if.req_done
}),
.probes({
cache_bus_if.rsp_data,
@ -324,7 +324,7 @@ module VX_raster_unit #(
ila_raster ila_raster_inst (
.clk (clk),
.probe0 ({cache_bus_if.rsp_data, cache_bus_if.rsp_tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid, cache_bus_if.req_tag, cache_bus_if.req_addr, cache_bus_if.req_rw, cache_bus_if.req_valid, cache_bus_if.req_ready}),
.probe1 ({no_pending_tiledata, mem_unit_busy, mem_unit_ready, mem_unit_start, mem_unit_valid, raster_req_if.done, raster_req_if.valid, raster_req_if.ready})
.probe1 ({no_pending_tiledata, mem_unit_busy, mem_unit_ready, mem_unit_start, mem_unit_valid, raster_bus_if.req_done, raster_bus_if.req_valid, raster_bus_if.req_ready})
);
`endif
end
@ -352,7 +352,7 @@ module VX_raster_unit #(
end
end
wire perf_stall_cycle = raster_req_if.valid && ~raster_req_if.ready && ~raster_req_if.done;
wire perf_stall_cycle = raster_bus_if.req_valid && ~raster_bus_if.req_ready && ~raster_bus_if.req_done;
reg [`PERF_CTR_BITS-1:0] perf_mem_reads;
reg [`PERF_CTR_BITS-1:0] perf_mem_latency;
@ -377,15 +377,15 @@ module VX_raster_unit #(
`ifdef DBG_TRACE_RASTER
always @(posedge clk) begin
if (raster_req_if.valid && raster_req_if.ready) begin
if (raster_bus_if.req_valid && raster_bus_if.req_ready) begin
for (integer i = 0; i < OUTPUT_QUADS; ++i) begin
`TRACE(1, ("%d: %s-out[%0d]: done=%b, x=%0d, y=%0d, mask=%0d, pid=%0d, bcoords={{0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}}\n",
$time, INSTANCE_ID, i, raster_req_if.done,
raster_req_if.stamps[i].pos_x, raster_req_if.stamps[i].pos_y, raster_req_if.stamps[i].mask, raster_req_if.stamps[i].pid,
raster_req_if.stamps[i].bcoords[0][0], raster_req_if.stamps[i].bcoords[1][0], raster_req_if.stamps[i].bcoords[2][0],
raster_req_if.stamps[i].bcoords[0][1], raster_req_if.stamps[i].bcoords[1][1], raster_req_if.stamps[i].bcoords[2][1],
raster_req_if.stamps[i].bcoords[0][2], raster_req_if.stamps[i].bcoords[1][2], raster_req_if.stamps[i].bcoords[2][2],
raster_req_if.stamps[i].bcoords[0][3], raster_req_if.stamps[i].bcoords[1][3], raster_req_if.stamps[i].bcoords[2][3]));
$time, INSTANCE_ID, i, raster_bus_if.req_done,
raster_bus_if.req_stamps[i].pos_x, raster_bus_if.req_stamps[i].pos_y, raster_bus_if.req_stamps[i].mask, raster_bus_if.req_stamps[i].pid,
raster_bus_if.req_stamps[i].bcoords[0][0], raster_bus_if.req_stamps[i].bcoords[1][0], raster_bus_if.req_stamps[i].bcoords[2][0],
raster_bus_if.req_stamps[i].bcoords[0][1], raster_bus_if.req_stamps[i].bcoords[1][1], raster_bus_if.req_stamps[i].bcoords[2][1],
raster_bus_if.req_stamps[i].bcoords[0][2], raster_bus_if.req_stamps[i].bcoords[1][2], raster_bus_if.req_stamps[i].bcoords[2][2],
raster_bus_if.req_stamps[i].bcoords[0][3], raster_bus_if.req_stamps[i].bcoords[1][3], raster_bus_if.req_stamps[i].bcoords[2][3]));
end
end
end
@ -440,14 +440,14 @@ module VX_raster_unit_top #(
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
VX_raster_req_if #(
VX_raster_bus_if #(
.NUM_LANES (OUTPUT_QUADS)
) raster_req_if();
) raster_bus_if();
assign raster_req_valid = raster_req_if.valid;
assign raster_req_stamps = raster_req_if.stamps;
assign raster_req_if.done = raster_req_done;
assign raster_req_if.ready = raster_req_ready;
assign raster_req_valid = raster_bus_if.valid;
assign raster_req_stamps = raster_bus_if.stamps;
assign raster_bus_if.done = raster_req_done;
assign raster_bus_if.ready = raster_req_ready;
VX_cache_bus_if #(
.NUM_REQS (RCACHE_NUM_REQS),
@ -493,7 +493,7 @@ module VX_raster_unit_top #(
.perf_raster_if(perf_raster_if),
`endif
.dcr_write_if (dcr_write_if),
.raster_req_if (raster_req_if),
.raster_bus_if (raster_bus_if),
.cache_bus_if (cache_bus_if)
);

10
hw/rtl/rop/VX_rop_agent.sv
View file

@ -12,7 +12,7 @@ module VX_rop_agent #(
// Outputs
VX_commit_if.master rop_commit_if,
VX_rop_req_if.master rop_req_if
VX_rop_bus_if.master rop_bus_if
);
`UNUSED_PARAM (CORE_ID)
@ -52,10 +52,10 @@ module VX_rop_agent #(
.reset (reset),
.valid_in (rop_req_valid),
.ready_in (rop_req_ready),
.data_in ({rop_agent_if.uuid, rop_agent_if.tmask, rop_agent_if.pos_x, rop_agent_if.pos_y, rop_agent_if.color, rop_agent_if.depth, rop_agent_if.face}),
.data_out ({rop_req_if.uuid, rop_req_if.mask, rop_req_if.pos_x, rop_req_if.pos_y, rop_req_if.color, rop_req_if.depth, rop_req_if.face}),
.valid_out (rop_req_if.valid),
.ready_out (rop_req_if.ready)
.data_in ({rop_agent_if.uuid, rop_agent_if.tmask, rop_agent_if.pos_x, rop_agent_if.pos_y, rop_agent_if.color, rop_agent_if.depth, rop_agent_if.face}),
.data_out ({rop_bus_if.req_uuid, rop_bus_if.req_mask, rop_bus_if.req_pos_x, rop_bus_if.req_pos_y, rop_bus_if.req_color, rop_bus_if.req_depth, rop_bus_if.req_face}),
.valid_out (rop_bus_if.req_valid),
.ready_out (rop_bus_if.req_ready)
);
assign rop_req_valid = rop_agent_if.valid && rop_rsp_ready;

16
hw/rtl/rop/VX_rop_arb.sv
View file

@ -11,10 +11,10 @@ module VX_rop_arb #(
input wire reset,
// input requests
VX_rop_req_if.slave req_in_if [NUM_INPUTS],
VX_rop_bus_if.slave bus_in_if [NUM_INPUTS],
// output request
VX_rop_req_if.master req_out_if [NUM_OUTPUTS]
VX_rop_bus_if.master bus_out_if [NUM_OUTPUTS]
);
localparam UUID_WIDTH = `UP(`UUID_BITS);
@ -29,9 +29,9 @@ module VX_rop_arb #(
wire [NUM_OUTPUTS-1:0] req_ready_out;
for (genvar i = 0; i < NUM_INPUTS; ++i) begin
assign req_valid_in[i] = req_in_if[i].valid;
assign req_data_in[i] = {req_in_if[i].uuid, req_in_if[i].mask, req_in_if[i].pos_x, req_in_if[i].pos_y, req_in_if[i].color, req_in_if[i].depth, req_in_if[i].face};
assign req_in_if[i].ready = req_ready_in[i];
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign req_data_in[i] = {bus_in_if[i].req_uuid, bus_in_if[i].req_mask, bus_in_if[i].req_pos_x, bus_in_if[i].req_pos_y, bus_in_if[i].req_color, bus_in_if[i].req_depth, bus_in_if[i].req_face};
assign bus_in_if[i].req_ready = req_ready_in[i];
end
VX_stream_arb #(
@ -53,9 +53,9 @@ module VX_rop_arb #(
);
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
assign req_out_if[i].valid = req_valid_out[i];
assign {req_out_if[i].uuid, req_out_if[i].mask, req_out_if[i].pos_x, req_out_if[i].pos_y, req_out_if[i].color, req_out_if[i].depth, req_out_if[i].face} = req_data_out[i];
assign req_ready_out[i] = req_out_if[i].ready;
assign bus_out_if[i].req_valid = req_valid_out[i];
assign {bus_out_if[i].req_uuid, bus_out_if[i].req_mask, bus_out_if[i].req_pos_x, bus_out_if[i].req_pos_y, bus_out_if[i].req_color, bus_out_if[i].req_depth, bus_out_if[i].req_face} = req_data_out[i];
assign req_ready_out[i] = bus_out_if[i].req_ready;
end
endmodule

43
hw/rtl/rop/VX_rop_bus_if.sv Normal file
View file

@ -0,0 +1,43 @@
`include "VX_rop_define.vh"
interface VX_rop_bus_if #(
parameter NUM_LANES = 1
) ();
wire req_valid;
wire [`UP(`UUID_BITS)-1:0] req_uuid;
wire [NUM_LANES-1:0] req_mask;
wire [NUM_LANES-1:0][`ROP_DIM_BITS-1:0] req_pos_x;
wire [NUM_LANES-1:0][`ROP_DIM_BITS-1:0] req_pos_y;
rgba_t [NUM_LANES-1:0] req_color;
wire [NUM_LANES-1:0][`ROP_DEPTH_BITS-1:0] req_depth;
wire [NUM_LANES-1:0] req_face;
wire req_ready;
modport master (
output req_valid,
output req_uuid,
output req_mask,
output req_pos_x,
output req_pos_y,
output req_color,
output req_depth,
output req_face,
input req_ready
);
modport slave (
input req_valid,
input req_uuid,
input req_mask,
input req_pos_x,
input req_pos_y,
input req_color,
input req_depth,
input req_face,
output req_ready
);
endinterface

43
hw/rtl/rop/VX_rop_req_if.sv
View file

@ -1,43 +0,0 @@
`include "VX_rop_define.vh"
interface VX_rop_req_if #(
parameter NUM_LANES = 1
) ();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;
wire [NUM_LANES-1:0] mask;
wire [NUM_LANES-1:0][`ROP_DIM_BITS-1:0] pos_x;
wire [NUM_LANES-1:0][`ROP_DIM_BITS-1:0] pos_y;
rgba_t [NUM_LANES-1:0] color;
wire [NUM_LANES-1:0][`ROP_DEPTH_BITS-1:0] depth;
wire [NUM_LANES-1:0] face;
wire ready;
modport master (
output valid,
output uuid,
output mask,
output pos_x,
output pos_y,
output color,
output depth,
output face,
input ready
);
modport slave (
input valid,
input uuid,
input mask,
input pos_x,
input pos_y,
input color,
input depth,
input face,
output ready
);
endinterface

48
hw/rtl/rop/VX_rop_unit.sv
View file

@ -17,7 +17,7 @@ module VX_rop_unit #(
// Inputs
VX_dcr_write_if.slave dcr_write_if,
VX_rop_req_if.slave rop_req_if
VX_rop_bus_if.slave rop_bus_if
);
localparam UUID_WIDTH = `UP(`UUID_BITS);
localparam MEM_TAG_WIDTH = UUID_WIDTH + NUM_LANES * (`ROP_DIM_BITS + `ROP_DIM_BITS + 32 + `ROP_DEPTH_BITS + 1);
@ -223,7 +223,7 @@ module VX_rop_unit #(
wire pending_reads_full;
assign mem_req_tag = {rop_req_if.uuid, rop_req_if.pos_x, rop_req_if.pos_y, rop_req_if.color, rop_req_if.depth, rop_req_if.face};
assign mem_req_tag = {rop_bus_if.req_uuid, rop_bus_if.req_pos_x, rop_bus_if.req_pos_y, rop_bus_if.req_color, rop_bus_if.req_depth, rop_bus_if.req_face};
assign {mem_rsp_uuid, mem_rsp_pos_x, mem_rsp_pos_y, blend_src_color, ds_depth_ref, ds_face} = mem_rsp_tag;
assign ds_tag_in = {mem_rsp_pos_x, mem_rsp_pos_y, mem_rsp_mask, ds_face, blend_src_color};
@ -232,9 +232,9 @@ module VX_rop_unit #(
assign blend_tag_in = {mem_rsp_pos_x, mem_rsp_pos_y, mem_rsp_mask};
assign {blend_write_pos_x, blend_write_pos_y, blend_rsp_mask} = blend_tag_out;
wire color_write = write_bypass && rop_req_if.valid;
wire color_write = write_bypass && rop_bus_if.req_valid;
wire ds_blend_read = mem_readen && rop_req_if.valid && ~pending_reads_full;
wire ds_blend_read = mem_readen && rop_bus_if.req_valid && ~pending_reads_full;
wire ds_blend_write = (ds_color_writeen && blend_writeen) ? (ds_valid_out && blend_valid_out) :
(ds_color_writeen ? ds_valid_out :
@ -246,11 +246,11 @@ module VX_rop_unit #(
wire [NUM_LANES-1:0] color_bypass_mask, ds_color_write_mask;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign ds_read_mask[i] = rop_req_if.mask[i] && ds_enable;
assign blend_read_mask[i] = rop_req_if.mask[i] && blend_writeen;
assign ds_read_mask[i] = rop_bus_if.req_mask[i] && ds_enable;
assign blend_read_mask[i] = rop_bus_if.req_mask[i] && blend_writeen;
assign ds_write_mask[i] = ds_rsp_mask[i] && (stencil_writeen || (depth_writeen && ds_pass_out[i]));
assign blend_write_mask[i] = blend_rsp_mask[i] && blend_writeen && (~ds_enable || ds_pass_out[i]);
assign color_bypass_mask[i] = rop_req_if.mask[i] && color_writeen;
assign color_bypass_mask[i] = rop_bus_if.req_mask[i] && color_writeen;
assign ds_color_write_mask[i] = ds_rsp_mask[i] && ds_pass_out[i];
end
@ -259,15 +259,15 @@ module VX_rop_unit #(
assign mem_req_c_mask = write_bypass ? color_bypass_mask : (blend_valid_out ? blend_write_mask : (ds_valid_out ? ds_color_write_mask : blend_read_mask));
assign mem_req_rw = ds_blend_write || write_bypass;
assign mem_req_face = ds_write_face;
assign mem_req_pos_x = ds_valid_out ? ds_write_pos_x : (blend_valid_out ? blend_write_pos_x : rop_req_if.pos_x);
assign mem_req_pos_y = ds_valid_out ? ds_write_pos_y : (blend_valid_out ? blend_write_pos_y : rop_req_if.pos_y);
assign mem_req_color = blend_enable ? blend_color_out : (ds_enable ? ds_write_color : rop_req_if.color);
assign mem_req_pos_x = ds_valid_out ? ds_write_pos_x : (blend_valid_out ? blend_write_pos_x : rop_bus_if.req_pos_x);
assign mem_req_pos_y = ds_valid_out ? ds_write_pos_y : (blend_valid_out ? blend_write_pos_y : rop_bus_if.req_pos_y);
assign mem_req_color = blend_enable ? blend_color_out : (ds_enable ? ds_write_color : rop_bus_if.req_color);
assign mem_req_depth = ds_depth_out;
assign mem_req_stencil = ds_stencil_out;
assign ds_ready_out = mem_req_ready && (~blend_writeen || blend_valid_out);
assign blend_ready_out = mem_req_ready && (~ds_color_writeen || ds_valid_out);
assign rop_req_if.ready = mem_req_ready && ~ds_blend_write && ~pending_reads_full;
assign rop_bus_if.req_ready = mem_req_ready && ~ds_blend_write && ~pending_reads_full;
assign ds_valid_in = ds_enable && mem_rsp_valid && (~blend_enable || blend_ready_in);
assign blend_valid_in = blend_enable && mem_rsp_valid && (~ds_enable || ds_ready_in);
@ -346,7 +346,7 @@ module VX_rop_unit #(
end
end
wire perf_stall_cycle = rop_req_if.valid & ~rop_req_if.ready;
wire perf_stall_cycle = rop_bus_if.req_valid & ~rop_bus_if.req_ready;
reg [`PERF_CTR_BITS-1:0] perf_mem_reads;
reg [`PERF_CTR_BITS-1:0] perf_mem_writes;
@ -421,19 +421,19 @@ module VX_rop_unit_top #(
assign dcr_write_if.addr = dcr_write_addr;
assign dcr_write_if.data = dcr_write_data;
VX_rop_req_if #(
VX_rop_bus_if #(
.NUM_LANES (NUM_LANES)
) rop_req_if();
) rop_bus_if();
assign rop_req_if.valid = rop_req_valid;
assign rop_req_if.uuid = rop_req_uuid;
assign rop_req_if.mask = rop_req_mask;
assign rop_req_if.pos_x = rop_req_pos_x;
assign rop_req_if.pos_y = rop_req_pos_y;
assign rop_req_if.color = rop_req_color;
assign rop_req_if.depth = rop_req_depth;
assign rop_req_if.face = rop_req_face;
assign rop_req_ready = rop_req_if.ready;
assign rop_bus_if.req_valid = rop_req_valid;
assign rop_bus_if.req_uuid = rop_req_uuid;
assign rop_bus_if.req_mask = rop_req_mask;
assign rop_bus_if.req_pos_x = rop_req_pos_x;
assign rop_bus_if.req_pos_y = rop_req_pos_y;
assign rop_bus_if.req_color = rop_req_color;
assign rop_bus_if.req_depth = rop_req_depth;
assign rop_bus_if.req_face = rop_req_face;
assign rop_req_ready = rop_bus_if.req_ready;
VX_cache_bus_if #(
.NUM_REQS (OCACHE_NUM_REQS),
@ -464,7 +464,7 @@ module VX_rop_unit_top #(
.perf_rop_if (perf_rop_if),
`endif
.dcr_write_if (dcr_write_if),
.rop_req_if (rop_req_if),
.rop_bus_if (rop_bus_if),
.cache_bus_if (cache_bus_if)
);