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minor updates

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This commit is contained in:
Blaise Tine 2023-06-26 07:50:29 -04:00
parent ea59247048
commit ba1f3df2c4
5 changed files with 28 additions and 27 deletions
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2
hw/rtl/VX_config.vh
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@ -310,7 +310,7 @@
// Pipeline latencies /////////////////////////////////////////////////////////
`ifndef LATENCY_IMUL
`define LATENCY_IMUL 3
`define LATENCY_IMUL 1
`endif
`ifndef LATENCY_FNCP

0
hw/rtl/core/VX_gpu_types.vh → hw/rtl/VX_gpu_types.vh
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40
hw/rtl/core/VX_core.sv
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@ -551,13 +551,13 @@ module VX_core_top #(
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
) tex_bus_if();
assign tex_req_valid = tex_bus_if.req_req_valid;
assign tex_req_mask = tex_bus_if.req_req_mask;
assign tex_req_coords = tex_bus_if.req_req_coords;
assign tex_req_lod = tex_bus_if.req_req_lod;
assign tex_req_stage = tex_bus_if.req_req_stage;
assign tex_req_tag = tex_bus_if.req_req_tag;
assign tex_bus_if.req_req_ready = tex_req_ready;
assign tex_req_valid = tex_bus_if.req_valid;
assign tex_req_mask = tex_bus_if.req_mask;
assign tex_req_coords = tex_bus_if.req_coords;
assign tex_req_lod = tex_bus_if.req_lod;
assign tex_req_stage = tex_bus_if.req_stage;
assign tex_req_tag = tex_bus_if.req_tag;
assign tex_bus_if.req_ready = tex_req_ready;
assign tex_bus_if.rsp_valid = tex_rsp_valid;
assign tex_bus_if.rsp_texels = tex_rsp_texels;
@ -570,10 +570,10 @@ module VX_core_top #(
.NUM_LANES (`NUM_THREADS)
) raster_bus_if();
assign raster_bus_if.valid = raster_req_valid;
assign raster_bus_if.stamps = raster_req_stamps;
assign raster_bus_if.done = raster_req_done;
assign raster_req_ready = raster_bus_if.ready;
assign raster_bus_if.req_valid = raster_req_valid;
assign raster_bus_if.req_stamps = raster_req_stamps;
assign raster_bus_if.req_done = raster_req_done;
assign raster_req_ready = raster_bus_if.req_ready;
`endif
`ifdef EXT_ROP_ENABLE
@ -581,15 +581,15 @@ module VX_core_top #(
.NUM_LANES (`NUM_THREADS)
) rop_bus_if();
assign rop_req_valid = rop_bus_if.valid;
assign rop_req_uuid = rop_bus_if.uuid;
assign rop_req_mask = rop_bus_if.mask;
assign rop_req_pos_x = rop_bus_if.pos_x;
assign rop_req_pos_y = rop_bus_if.pos_y;
assign rop_req_color = rop_bus_if.color;
assign rop_req_depth = rop_bus_if.depth;
assign rop_req_face = rop_bus_if.face;
assign rop_bus_if.ready = rop_req_ready;
assign rop_req_valid = rop_bus_if.req_valid;
assign rop_req_uuid = rop_bus_if.req_uuid;
assign rop_req_mask = rop_bus_if.req_mask;
assign rop_req_pos_x = rop_bus_if.req_pos_x;
assign rop_req_pos_y = rop_bus_if.req_pos_y;
assign rop_req_color = rop_bus_if.req_color;
assign rop_req_depth = rop_bus_if.req_depth;
assign rop_req_face = rop_bus_if.req_face;
assign rop_bus_if.req_ready = rop_req_ready;
`endif
`ifdef SCOPE

8
hw/rtl/raster/VX_raster_unit.sv
View file

@ -444,10 +444,10 @@ module VX_raster_unit_top #(
.NUM_LANES (OUTPUT_QUADS)
) raster_bus_if();
assign raster_req_valid = raster_bus_if.valid;
assign raster_req_stamps = raster_bus_if.stamps;
assign raster_bus_if.done = raster_req_done;
assign raster_bus_if.ready = raster_req_ready;
assign raster_req_valid = raster_bus_if.req_valid;
assign raster_req_stamps = raster_bus_if.req_stamps;
assign raster_bus_if.req_done = raster_req_done;
assign raster_bus_if.req_ready = raster_req_ready;
VX_cache_bus_if #(
.NUM_REQS (RCACHE_NUM_REQS),

5
hw/rtl/tex/VX_tex_sampler.sv
View file

@ -45,6 +45,7 @@ module VX_tex_sampler #(
VX_pipe_register #(
.DATAW (1 + REQ_INFOW + (NUM_LANES * 2 * `TEX_BLEND_FRAC) + (NUM_LANES * 4 * 32)),
.DEPTH (2),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
@ -83,7 +84,7 @@ module VX_tex_sampler #(
VX_shift_register #(
.DATAW (1 + REQ_INFOW + (NUM_LANES * `TEX_BLEND_FRAC)),
.DEPTH (3),
.DEPTH (2),
.RESETW (1)
) shift_reg1 (
.clk (clk),
@ -111,7 +112,7 @@ module VX_tex_sampler #(
VX_shift_register #(
.DATAW (1 + REQ_INFOW),
.DEPTH (3),
.DEPTH (1),
.RESETW (1)
) shift_reg2 (
.clk (clk),