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minor update

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This commit is contained in:
Blaise Tine 2024-02-15 04:31:13 -08:00
parent 413e933b8a
commit bb3a49f95b
2 changed files with 14 additions and 14 deletions
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6
hw/rtl/libs/VX_mem_scheduler.sv
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@ -22,7 +22,7 @@ module VX_mem_scheduler #(
parameter WORD_SIZE = 4,
parameter LINE_SIZE = 4,
parameter TAG_WIDTH = 8,
parameter TAG_ID_WIDTH = 0, // lower section of the request tag contains the tag identifier
parameter TAG_ID_WIDTH = 8, // lower section of the request tag contains the tag identifier
parameter UUID_WIDTH = 0, // upper section of the request tag contains the UUID
parameter QUEUE_SIZE = 8,
parameter RSP_PARTIAL = 0,
@ -181,7 +181,7 @@ module VX_mem_scheduler #(
assign ibuf_push = reqq_push && ~core_req_rw;
assign ibuf_pop = crsp_valid && crsp_ready && rsp_complete;
assign ibuf_raddr = mem_rsp_tag_s[0 +: QUEUE_ADDRW];
assign ibuf_raddr = mem_rsp_tag_s[BATCH_SEL_BITS +: QUEUE_ADDRW];
assign ibuf_din = core_req_tag[TAG_ID_WIDTH-1:0];
VX_index_buffer #(
@ -363,7 +363,7 @@ module VX_mem_scheduler #(
assign rsp_batch_idx = mem_rsp_tag_s[BATCH_SEL_BITS-1:0];
end else begin
assign rsp_batch_idx = '0;
end
end
assign rsp_complete = ~(| rsp_rem_mask_n);

22
hw/unittest/mem_streamer/memsim.cpp
View file

@ -105,24 +105,24 @@ void MemSim::reset() {
}
void MemSim::attach_core() {
if (msu_->req_ready) {
msu_->req_valid = generate_rand(0, 1);
msu_->req_rw = generate_rand(0, 1);
msu_->req_mask = generate_rand(0b0001, 0b1111);
msu_->req_byteen = 0b1;
msu_->req_addr = generate_rand(0, 0x10000000);
msu_->req_data = generate_rand(0x60000000, 0x80000000);
msu_->req_tag = generate_rand(0x00, 0xFF);
if (msu_->core_req_ready) {
msu_->core_req_valid = generate_rand(0, 1);
msu_->core_req_rw = generate_rand(0, 1);
msu_->core_req_mask = generate_rand(0b0001, 0b1111);
msu_->core_req_byteen = 0b1;
msu_->core_req_addr = generate_rand(0, 0x10000000);
msu_->core_req_data = generate_rand(0x60000000, 0x80000000);
msu_->core_req_tag = generate_rand(0x00, 0xFF);
}
msu_->rsp_ready = true;
msu_->core_rsp_ready = true;
}
void MemSim::attach_ram (RAM *ram) {
req_t req;
req.valid = msu_->mem_req_valid;
req.valid = msu_->mem_req_valid;
req.rw = msu_->mem_req_rw;
req.byteen = msu_->mem_req_byteen;
req.byteen = msu_->mem_req_byteen;
req.addr = msu_->mem_req_addr;
req.data = msu_->mem_req_data;
req.tag = msu_->mem_req_tag;