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bilinear sampling
This commit is contained in:
Krishna Yalamarthy
parent
8fa78ef059
commit
c0fdee5787
5 changed files with 229 additions and 67 deletions
71
hw/rtl/tex_unit/VX_bilerp.v
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71
hw/rtl/tex_unit/VX_bilerp.v
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@ -0,0 +1,71 @@
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`include "VX_tex_define.vh"
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module VX_bilerp #(
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parameter CORE_ID = 0
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) (
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input wire [`BLEND_FRAC_64-1:0] blendU, //blendU
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input wire [`BLEND_FRAC_64-1:0] blendV, //blendV
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input wire [3:0][63:0] texels,
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input wire [`TEX_FORMAT_BITS-1:0] color_enable,
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output wire [31:0] sampled_data
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR(color_enable)
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wire [63:0] UL_lerp;
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wire [63:0] UH_lerp;
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wire [63:0] V_lerp;
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reg [31:0] sampled_r;
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VX_lerp_64 #(
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) UL_lerp (
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.blend(blendU),
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.in_texels({texels[1], texels[0]}),
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.lerp_texel(UL_lerp)
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);
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VX_lerp_64 #(
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) UH_lerp (
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.blend(blendU),
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.in_texels({texels[3], texels[2]}),
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.lerp_texel(UH_lerp)
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);
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VX_lerp_64 #(
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) V_lerp (
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.blend(blendV),
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.in_texels({UH_lerp, UL_lerp}),
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.lerp_texel(V_lerp)
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);
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always @(*) begin
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if(color_enable[3]==1) //R
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sampled_r[31:24] = V_lerp[55:48];
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else
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sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
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if(color_enable[2]==1) //G
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sampled_r[23:16] = V_lerp[39:32];
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else
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sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
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if(color_enable[1]==1) //B
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sampled_r[15:8] = V_lerp[23:16];
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else
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sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
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if(color_enable[0]==1) //A
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sampled_r[7:0] = V_lerp[7:0];
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else
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sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};
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end
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assign sampled_data = sampled_r;
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endmodule
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18
hw/rtl/tex_unit/VX_lerp.v
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18
hw/rtl/tex_unit/VX_lerp.v
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@ -0,0 +1,18 @@
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`include "VX_tex_define.vh"
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module VX_lerp_64 #(
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) (
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input wire [`BLEND_FRAC_64-1:0] blend,
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input wire [1:0][63:0] in_texels,
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output wire [63:0] lerp_texel
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);
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wire [63:0] lerp_i1;
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wire [63:0] lerp_i2; // >> BLEND_FRAC_64 / >> 8
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assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend;
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assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]};
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assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff;
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endmodule
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@ -11,6 +11,9 @@
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`define CLAMP(x,lo,hi) ((x < lo) ? lo : ((x > hi) ? hi : x))
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`define BLEND_FRAC_64 8
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`define LERP_64(x1,x2,frac) ((x2 + (((x1 - x2) * frac) >> `BLEND_FRAC_64)) & 64'h00ff00ff00ff00ff)
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`define TEX_ADDR_BITS 32
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`define TEX_FORMAT_BITS 3
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`define TEX_WRAP_BITS 2
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@ -26,7 +29,7 @@
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`define MAX_COLOR_WIDTH 8
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`define NUM_COLOR_CHANNEL 4
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`define TEX_COLOR_BITS 32
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`define TEX_COLOR_BITS 8
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`define R5G6B5 `TEX_FORMAT_BITS'h1
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`define R8G8B8 `TEX_FORMAT_BITS'h2
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@ -1,55 +1,101 @@
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`include "VX_tex_define.vh"
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module VX_tex_format #(
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parameter CORE_ID = 0
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parameter CORE_ID = 0,
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parameter NUM_TEXELS = 4 //BILINEAR
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) (
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input wire [31:0] texel_data,
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input wire [NUM_TEXELS-1:0][31:0] texel_data,
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input wire [`TEX_FORMAT_BITS-1:0] format,
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output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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output wire [`TEX_COLOR_BITS-1:0] R,
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output wire [`TEX_COLOR_BITS-1:0] G,
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output wire [`TEX_COLOR_BITS-1:0] B,
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output wire [`TEX_COLOR_BITS-1:0] A
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output wire [NUM_TEXELS-1:0][63:0] formatted_texel
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
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reg [`TEX_COLOR_BITS-1:0] R_r;
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reg [`TEX_COLOR_BITS-1:0] G_r;
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reg [`TEX_COLOR_BITS-1:0] B_r;
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reg [`TEX_COLOR_BITS-1:0] A_r;
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reg [NUM_TEXELS][63:0] formatted_texel_r;
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always @(*) begin
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case (format)
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`R5G6B5: begin
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R_r = `TEX_COLOR_BITS'(texel_data[15:11]);
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G_r = `TEX_COLOR_BITS'(texel_data[10:5]);
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B_r = `TEX_COLOR_BITS'(texel_data[4:0]);
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A_r = {`TEX_COLOR_BITS{1'b0}};
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color_enable_r = 4'b1110;
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end
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`R8G8B8: begin
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R_r = `TEX_COLOR_BITS'(texel_data[23:16]);
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G_r = `TEX_COLOR_BITS'(texel_data[15:8]);
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B_r = `TEX_COLOR_BITS'(texel_data[7:0]);
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A_r = {`TEX_COLOR_BITS{1'b0}};
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color_enable_r = 4'b1110;
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end
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default: begin // `R8G8B8A8:
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R_r = `TEX_COLOR_BITS'(texel_data[31:24]);
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G_r = `TEX_COLOR_BITS'(texel_data[23:16]);
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B_r = `TEX_COLOR_BITS'(texel_data[15:8]);
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A_r = `TEX_COLOR_BITS'(texel_data[7:0]);
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color_enable_r = 4'b1111;
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end
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endcase
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for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
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case (format)
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`R5G6B5: begin
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
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formatted_texel_r[i][7:0] = {`TEX_COLOR_BITS{1'b0}};
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if (i == 0)
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color_enable_r = 4'b1110;
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end
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`R8G8B8: begin
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][7:0] = {`TEX_COLOR_BITS{1'b0}};
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if (i == 0)
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color_enable_r = 4'b1110;
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end
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default: begin // `R8G8B8A8:
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][7:0] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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if (i == 0)
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color_enable_r = 4'b1111;
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end
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endcase
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end
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end
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assign color_enable = color_enable_r;
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assign R = R_r;
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assign G = G_r;
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assign B = B_r;
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assign A = A_r;
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assign formatted_texel = formatted_texel_r & 64'h00ff00ff00ff00ff;
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endmodule
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// module VX_tex_format #(
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// parameter CORE_ID = 0
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// ) (
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// input wire [`TEX_FORMAT_BITS-1:0] format,
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// input wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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// input wire [`TEX_COLOR_BITS-1:0] R,
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// input wire [`TEX_COLOR_BITS-1:0] G,
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// input wire [`TEX_COLOR_BITS-1:0] B,
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// input wire [`TEX_COLOR_BITS-1:0] A,
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// output wire [31:0] texel_sampled
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// );
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// `UNUSED_PARAM (CORE_ID)
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// `UNUSED_VAR(color_enable)
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// reg [63:0] sampled_r;
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// always @(*) begin
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// case (format)
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// `R5G6B5: begin
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// sampled_r[31:16] = 'd0;
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// sampled_r[15:11] = R[4:0];
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// sampled_r[10:5] = G[5:0];
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// sampled_r[4:0] = B[4:0];
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// end
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// `R8G8B8: begin
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// sampled_r[31:24] = 'd0;
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// sampled_r[23:16] = R;
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// sampled_r[15:8] = G;
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// sampled_r[7:0] = B;
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// end
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// default: begin // `R8G8B8A8:
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// sampled_r[31:24] = R;
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// sampled_r[23:16] = R;
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// sampled_r[15:8] = G;
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// sampled_r[7:0] = A;
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// end
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// endcase
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// end
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// assign texel_sampled = sampled_r;
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// endmodule
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endmodule
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@ -33,47 +33,71 @@ module VX_tex_sampler #(
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`UNUSED_PARAM (CORE_ID)
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wire [31:0] req_data [`NUM_THREADS-1:0];
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if (req_filter == 0) begin // point sampling
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wire [31:0] req_data [`NUM_THREADS-1:0];
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for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
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req_data[i] = req_texels[i][0]
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end
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end else begin // bilinear sampling
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for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
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// wire [3:0][63:0] formatted_data;
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// wire [`TEX_FORMAT_BITS-1:0] color_enable;
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VX_tex_format #(
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.CORE_ID (CORE_ID)
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) tex_format_point (
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.CORE_ID (CORE_ID),
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.NUM_TEXELS (4)
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) tex_format_texel (
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.texel_data (req_texels[i]),
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.format (req_format),
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.color_enable (),
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.R(req_data[i][`RBEGIN +: 8]),
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.G(req_data[i][`GBEGIN +: 8]),
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.B(req_data[i][`BBEGIN +: 8]),
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.A(req_data[i][`ABEGIN +: 8])
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);
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.color_enable (color_enable),
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.formatted_texel(formatted_data)
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);
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//blendU/blendV calculation
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wire [`BLEND_FRAC_64-1:0] blendU;
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wire [`BLEND_FRAC_64-1:0] blendV;
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assign blendU = req_u[i][`BLEND_FRAC_64-1:0];
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assign blendV = req_v[i][`BLEND_FRAC_64-1:0];
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VX_bilerp #(
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.CORE_ID (CORE_ID)
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) tex_bilerp (
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.blendU(blendU), //blendU
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.blendV(blendV), //blendV
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.color_enable(color_enable),
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.texels(formatted_data),
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.sampled_data(req_data[i])
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);
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end
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
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);
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// output
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assign stall_out = ~rsp_ready;
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assign req_ready = rsp_ready;
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end else begin // bilinear sampling
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// TO DO
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end
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assign stall_out = ~rsp_ready;
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assign req_ready = rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
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);
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endmodule
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