mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-22 21:09:15 -04:00
tcache disable fix
This commit is contained in:
Blaise Tine
parent
a82ae7df59
commit
c13efc9d10
9 changed files with 73 additions and 70 deletions
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@ -316,17 +316,23 @@
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assign dst.tag = src.tag; \
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assign src.ready = dst.ready
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`define ASSIGN_VX_MEM_REQ_IF_XTAG(dst, src) \
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`define ASSIGN_VX_MEM_REQ_IF_X(dst, src, TD, TS) \
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assign dst.valid = src.valid; \
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assign dst.rw = src.rw; \
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assign dst.byteen = src.byteen; \
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assign dst.addr = src.addr; \
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assign dst.data = src.data; \
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if (TD != TS) \
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assign dst.tag = {src.tag, {(TD-TS){1'b0}}}; \
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else \
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assign dst.tag = src.tag; \
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assign src.ready = dst.ready
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`define ASSIGN_VX_MEM_RSP_IF_XTAG(dst, src) \
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`define ASSIGN_VX_MEM_RSP_IF_X(dst, src, TD, TS) \
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assign dst.valid = src.valid; \
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assign dst.data = src.data; \
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assign dst.tag = src.tag[TS-1 -: TD]; \
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assign src.ready = dst.ready
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`define ASSIGN_VX_CACHE_REQ_IF(dst, src) \
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@ -60,7 +60,7 @@ localparam ICACHE_NUM_REQS = 1;
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localparam ICACHE_NUM_BANKS = 1;
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// Memory request data bits
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localparam ICACHE_MEM_DATA_WIDTH= (ICACHE_LINE_SIZE * 8);
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localparam ICACHE_MEM_DATA_WIDTH = (ICACHE_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef ICACHE_ENABLE
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@ -86,7 +86,7 @@ localparam LSU_MEM_REQS = `NUM_THREADS;
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// Batch select bits
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localparam DCACHE_NUM_BATCHES = ((LSU_MEM_REQS + DCACHE_NUM_REQS - 1) / DCACHE_NUM_REQS);
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localparam DCACHE_BATCH_SEL_BITS= `CLOG2(DCACHE_NUM_BATCHES);
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localparam DCACHE_BATCH_SEL_BITS = `CLOG2(DCACHE_NUM_BATCHES);
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// Core request tag Id bits
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localparam LSUQ_TAG_BITS = (`CLOG2(`LSUQ_SIZE) + DCACHE_BATCH_SEL_BITS);
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@ -97,10 +97,10 @@ localparam DCACHE_TAG_WIDTH = (`UP(`UUID_BITS) + DCACHE_TAG_ID_BITS);
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localparam DCACHE_ARB_TAG_WIDTH = (DCACHE_TAG_WIDTH + `CLOG2(`SOCKET_SIZE));
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// Memory request data bits
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localparam DCACHE_MEM_DATA_WIDTH= (DCACHE_LINE_SIZE * 8);
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localparam DCACHE_MEM_DATA_WIDTH = (DCACHE_LINE_SIZE * 8);
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// Memory request tag bits
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localparam DCACHE_NOSM_TAG_WIDTH= (DCACHE_ARB_TAG_WIDTH - `SM_ENABLED);
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localparam DCACHE_NOSM_TAG_WIDTH = (DCACHE_ARB_TAG_WIDTH - `SM_ENABLED);
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`ifdef DCACHE_ENABLE
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localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_MEM_TAG_WIDTH(`DCACHE_MSHR_SIZE, `DCACHE_NUM_BANKS, DCACHE_NUM_REQS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_NOSM_TAG_WIDTH, `NUM_SOCKETS, `NUM_DCACHES);
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`else
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@ -123,7 +123,7 @@ localparam TCACHE_NUM_REQS = `TCACHE_NUM_BANKS;
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localparam TEX_MEM_REQS = (4 * `NUM_THREADS);
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// Batch select bits
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localparam TCACHE_BATCH_SEL_BITS=`ARB_SEL_BITS(TEX_MEM_REQS, TCACHE_NUM_REQS);
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localparam TCACHE_BATCH_SEL_BITS =`ARB_SEL_BITS(TEX_MEM_REQS, TCACHE_NUM_REQS);
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// Core request tag Id bits
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localparam TCACHE_TAG_ID_BITS = (`CLOG2(`TEX_MEM_QUEUE_SIZE) + TCACHE_BATCH_SEL_BITS);
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@ -132,7 +132,7 @@ localparam TCACHE_TAG_ID_BITS = (`CLOG2(`TEX_MEM_QUEUE_SIZE) + TCACHE_BATCH_SEL_
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localparam TCACHE_TAG_WIDTH = (`UP(`UUID_BITS) + TCACHE_TAG_ID_BITS);
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// Memory request data bits
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localparam TCACHE_MEM_DATA_WIDTH= (TCACHE_LINE_SIZE * 8);
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localparam TCACHE_MEM_DATA_WIDTH = (TCACHE_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef TCACHE_ENABLE
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@ -157,7 +157,7 @@ localparam RCACHE_NUM_REQS = `RCACHE_NUM_BANKS;
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localparam RASTER_MEM_REQS = 9;
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// Batch select bits
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localparam RCACHE_BATCH_SEL_BITS= `ARB_SEL_BITS(RASTER_MEM_REQS, RCACHE_NUM_REQS);
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localparam RCACHE_BATCH_SEL_BITS = `ARB_SEL_BITS(RASTER_MEM_REQS, RCACHE_NUM_REQS);
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// Core request tag Id bits
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localparam RCACHE_TAG_ID_BITS = (`CLOG2(`RASTER_MEM_QUEUE_SIZE) + RCACHE_BATCH_SEL_BITS);
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@ -191,7 +191,7 @@ localparam OCACHE_NUM_REQS = `OCACHE_NUM_BANKS;
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localparam ROP_MEM_REQS = (2 * `NUM_THREADS);
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// Batch select bits
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localparam OCACHE_BATCH_SEL_BITS= `ARB_SEL_BITS(ROP_MEM_REQS, OCACHE_NUM_REQS);
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localparam OCACHE_BATCH_SEL_BITS = `ARB_SEL_BITS(ROP_MEM_REQS, OCACHE_NUM_REQS);
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// Core request tag Id bits
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localparam OCACHE_TAG_ID_BITS = (`CLOG2(`ROP_MEM_QUEUE_SIZE) + OCACHE_BATCH_SEL_BITS);
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@ -200,11 +200,11 @@ localparam OCACHE_TAG_ID_BITS = (`CLOG2(`ROP_MEM_QUEUE_SIZE) + OCACHE_BATCH_SEL_
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localparam OCACHE_TAG_WIDTH = (`UP(`UUID_BITS) + OCACHE_TAG_ID_BITS);
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// Memory request data bits
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localparam OCACHE_MEM_DATA_WIDTH= (OCACHE_LINE_SIZE * 8);
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localparam OCACHE_MEM_DATA_WIDTH = (OCACHE_LINE_SIZE * 8);
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// Memory request tag bits
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`ifdef OCACHE_ENABLE
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localparam OCACHE_MEM_TAG_WIDTH= `CACHE_CLUSTER_MEM_TAG_WIDTH(`OCACHE_MSHR_SIZE, `OCACHE_NUM_BANKS, `NUM_OCACHES);
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localparam OCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_MEM_TAG_WIDTH(`OCACHE_MSHR_SIZE, `OCACHE_NUM_BANKS, `NUM_OCACHES);
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`else
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localparam OCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(OCACHE_NUM_REQS, OCACHE_LINE_SIZE, OCACHE_WORD_SIZE, OCACHE_TAG_WIDTH, `NUM_ROP_UNITS, `NUM_OCACHES);
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`endif
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@ -212,9 +212,9 @@ localparam OCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(OCACHE_NUM_REQ
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/////////////////////////////// L1 Parameters /////////////////////////////////
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localparam L1_MEM_TAG_WIDTH = `MAX(`MAX(`MAX(`MAX(ICACHE_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH),
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(`TCACHE_ENABLED ? TCACHE_MEM_TAG_WIDTH : 0)),
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(`RCACHE_ENABLED ? RCACHE_MEM_TAG_WIDTH : 0)),
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(`OCACHE_ENABLED ? OCACHE_MEM_TAG_WIDTH : 0));
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(`EXT_TEX_ENABLED ? TCACHE_MEM_TAG_WIDTH : 0)),
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(`EXT_RASTER_ENABLED ? RCACHE_MEM_TAG_WIDTH : 0)),
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(`EXT_ROP_ENABLED ? OCACHE_MEM_TAG_WIDTH : 0));
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localparam NUM_L1_OUTPUTS = (2 + `EXT_TEX_ENABLED + `EXT_RASTER_ENABLED + `EXT_ROP_ENABLED);
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@ -56,7 +56,7 @@ module VX_mem_unit # (
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VX_perf_cache_if perf_l2cache_if();
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`endif
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/////////////////////////////// I-Cache ///////////////////////////////////
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/////////////////////////////// I-Cache ///////////////////////////////////
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VX_mem_req_if #(
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.DATA_WIDTH (ICACHE_MEM_DATA_WIDTH),
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@ -103,7 +103,7 @@ module VX_mem_unit # (
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.mem_rsp_if (icache_mem_rsp_if)
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);
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/////////////////////////////// D-Cache ///////////////////////////////////
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/////////////////////////////// D-Cache ///////////////////////////////////
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VX_mem_req_if #(
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.DATA_WIDTH (DCACHE_MEM_DATA_WIDTH),
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@ -165,7 +165,7 @@ module VX_mem_unit # (
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.mem_rsp_if (dcache_mem_rsp_if)
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);
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////////////////////////////// Shared Memory //////////////////////////////
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////////////////////////////// Shared Memory //////////////////////////////
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`ifdef SM_ENABLE
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@ -274,7 +274,7 @@ module VX_mem_unit # (
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`endif
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/////////////////////////////// T-Cache ///////////////////////////////////
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/////////////////////////////// T-Cache ///////////////////////////////////
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`ifdef EXT_TEX_ENABLE
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@ -327,7 +327,7 @@ module VX_mem_unit # (
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`endif
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/////////////////////////////// O-Cache ///////////////////////////////////
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/////////////////////////////// O-Cache ///////////////////////////////////
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`ifdef EXT_ROP_ENABLE
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@ -381,7 +381,7 @@ module VX_mem_unit # (
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`endif
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/////////////////////////////// R-Cache ///////////////////////////////////
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/////////////////////////////// R-Cache ///////////////////////////////////
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`ifdef EXT_RASTER_ENABLE
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@ -434,7 +434,7 @@ module VX_mem_unit # (
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`endif
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/////////////////////////////// L2-Cache //////////////////////////////////
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/////////////////////////////// L2-Cache //////////////////////////////////
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VX_mem_req_if #(
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.DATA_WIDTH (L2_WORD_SIZE * 8),
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@ -455,40 +455,25 @@ module VX_mem_unit # (
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`UNUSED_PARAM (R_MEM_ARB_IDX)
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`UNUSED_PARAM (O_MEM_ARB_IDX)
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`ASSIGN_VX_MEM_REQ_IF_XTAG (l2_mem_req_if[I_MEM_ARB_IDX], icache_mem_req_if);
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assign l2_mem_req_if[I_MEM_ARB_IDX].tag = L1_MEM_TAG_WIDTH'(icache_mem_req_if.tag);
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`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[I_MEM_ARB_IDX], icache_mem_req_if, L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_RSP_IF_X (icache_mem_rsp_if, l2_mem_rsp_if[I_MEM_ARB_IDX], ICACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_RSP_IF_XTAG (icache_mem_rsp_if, l2_mem_rsp_if[I_MEM_ARB_IDX]);
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assign icache_mem_rsp_if.tag = ICACHE_MEM_TAG_WIDTH'(l2_mem_rsp_if[I_MEM_ARB_IDX].tag);
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`ASSIGN_VX_MEM_REQ_IF_XTAG (l2_mem_req_if[D_MEM_ARB_IDX], dcache_mem_req_if);
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assign l2_mem_req_if[D_MEM_ARB_IDX].tag = L1_MEM_TAG_WIDTH'(dcache_mem_req_if.tag);
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`ASSIGN_VX_MEM_RSP_IF_XTAG (dcache_mem_rsp_if, l2_mem_rsp_if[D_MEM_ARB_IDX]);
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assign dcache_mem_rsp_if.tag = DCACHE_MEM_TAG_WIDTH'(l2_mem_rsp_if[D_MEM_ARB_IDX].tag);
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`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[D_MEM_ARB_IDX], dcache_mem_req_if, L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_RSP_IF_X (dcache_mem_rsp_if, l2_mem_rsp_if[D_MEM_ARB_IDX], DCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
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`ifdef EXT_TEX_ENABLE
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`ASSIGN_VX_MEM_REQ_IF_XTAG (l2_mem_req_if[T_MEM_ARB_IDX], tcache_mem_req_if);
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assign l2_mem_req_if[T_MEM_ARB_IDX].tag = L1_MEM_TAG_WIDTH'(tcache_mem_req_if.tag);
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`ASSIGN_VX_MEM_RSP_IF_XTAG (tcache_mem_rsp_if, l2_mem_rsp_if[T_MEM_ARB_IDX]);
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assign tcache_mem_rsp_if.tag = TCACHE_MEM_TAG_WIDTH'(l2_mem_rsp_if[T_MEM_ARB_IDX].tag);
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`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[T_MEM_ARB_IDX], tcache_mem_req_if, L1_MEM_TAG_WIDTH, TCACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_RSP_IF_X (tcache_mem_rsp_if, l2_mem_rsp_if[T_MEM_ARB_IDX], TCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
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`endif
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`ifdef EXT_RASTER_ENABLE
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`ASSIGN_VX_MEM_REQ_IF_XTAG (l2_mem_req_if[R_MEM_ARB_IDX], rcache_mem_req_if);
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assign l2_mem_req_if[R_MEM_ARB_IDX].tag = L1_MEM_TAG_WIDTH'(rcache_mem_req_if.tag);
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`ASSIGN_VX_MEM_RSP_IF_XTAG (rcache_mem_rsp_if, l2_mem_rsp_if[R_MEM_ARB_IDX]);
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assign rcache_mem_rsp_if.tag = RCACHE_MEM_TAG_WIDTH'(l2_mem_rsp_if[R_MEM_ARB_IDX].tag);
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`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[R_MEM_ARB_IDX], rcache_mem_req_if, L1_MEM_TAG_WIDTH, RCACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_RSP_IF_X (rcache_mem_rsp_if, l2_mem_rsp_if[R_MEM_ARB_IDX], RCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
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`endif
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`ifdef EXT_ROP_ENABLE
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`ASSIGN_VX_MEM_REQ_IF_XTAG (l2_mem_req_if[O_MEM_ARB_IDX], ocache_mem_req_if);
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assign l2_mem_req_if[O_MEM_ARB_IDX].tag = L1_MEM_TAG_WIDTH'(ocache_mem_req_if.tag);
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`ASSIGN_VX_MEM_RSP_IF_XTAG (ocache_mem_rsp_if, l2_mem_rsp_if[O_MEM_ARB_IDX]);
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assign ocache_mem_rsp_if.tag = OCACHE_MEM_TAG_WIDTH'(l2_mem_rsp_if[O_MEM_ARB_IDX].tag);
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`ASSIGN_VX_MEM_REQ_IF_X (l2_mem_req_if[O_MEM_ARB_IDX], ocache_mem_req_if, L1_MEM_TAG_WIDTH, OCACHE_MEM_TAG_WIDTH);
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`ASSIGN_VX_MEM_RSP_IF_X (ocache_mem_rsp_if, l2_mem_rsp_if[O_MEM_ARB_IDX], OCACHE_MEM_TAG_WIDTH, L1_MEM_TAG_WIDTH);
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`endif
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`RESET_RELAY (l2_reset, reset);
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20
hw/rtl/cache/VX_cache_bank.sv
vendored
20
hw/rtl/cache/VX_cache_bank.sv
vendored
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@ -195,7 +195,13 @@ module VX_cache_bank #(
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wire creq_fire = creq_valid && creq_ready;
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wire [TAG_WIDTH-1:0] mshr_creq_tag = mshr_enable ? mshr_tag[0] : creq_tag[0];
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`ASSIGN_REQ_UUID (req_uuid_sel, mshr_creq_tag)
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if (UUID_WIDTH != 0) begin
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assign req_uuid_sel = mshr_creq_tag[TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid_sel = 0;
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end
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`UNUSED_VAR (mshr_creq_tag)
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wire [`LINE_WIDTH-1:0] wdata_sel;
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@ -230,7 +236,11 @@ module VX_cache_bank #(
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.data_out ({valid_st0, is_init_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_st0})
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);
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`ASSIGN_REQ_UUID (req_uuid_st0, tag_st0[0])
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if (UUID_WIDTH != 0) begin
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assign req_uuid_st0 = tag_st0[0][TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid_st0 = 0;
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end
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wire do_read_st0 = valid_st0 && is_read_st0;
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wire do_mshr_st0 = valid_st0 && is_mshr_st0;
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@ -289,7 +299,11 @@ module VX_cache_bank #(
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, is_hit_st1, way_sel_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_idx_st1, pmask_st1, tag_st1, mshr_id_st1, mshr_pending_st1})
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);
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`ASSIGN_REQ_UUID (req_uuid_st1, tag_st1[0])
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if (UUID_WIDTH != 0) begin
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assign req_uuid_st1 = tag_st1[0][TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid_st1 = 0;
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end
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wire do_read_st1 = valid_st1 && is_read_st1;
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wire do_write_st1 = valid_st1 && is_write_st1;
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7
hw/rtl/cache/VX_cache_define.vh
vendored
7
hw/rtl/cache/VX_cache_define.vh
vendored
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@ -45,13 +45,6 @@
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`define LINE_TAG_ADDR(x) x[`LINE_ADDR_WIDTH-1 : `LINE_SEL_BITS]
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`define ASSIGN_REQ_UUID(dst, tag) \
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if (UUID_WIDTH != 0) begin \
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assign dst = tag[TAG_WIDTH-1 -: UUID_WIDTH]; \
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end else begin \
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assign dst = 0; \
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end
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///////////////////////////////////////////////////////////////////////////////
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`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SEL_BITS'(i)}
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11
hw/rtl/cache/VX_cache_wrap.sv
vendored
11
hw/rtl/cache/VX_cache_wrap.sv
vendored
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@ -459,8 +459,13 @@ module VX_cache_wrap #(
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wire [`UP(UUID_WIDTH)-1:0] core_req_uuid;
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wire [`UP(UUID_WIDTH)-1:0] core_rsp_uuid;
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`ASSIGN_REQ_UUID (core_req_uuid, core_req_if[i].tag)
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`ASSIGN_REQ_UUID (core_rsp_uuid, core_rsp_if[i].tag)
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if (UUID_WIDTH != 0) begin
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assign core_req_uuid = core_req_if[i].tag[TAG_WIDTH-1 -: UUID_WIDTH];
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assign core_rsp_uuid = core_rsp_if[i].tag[TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign core_req_uuid = 0;
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assign core_rsp_uuid = 0;
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end
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wire core_req_fire = core_req_if[i].valid && core_req_if[i].ready;
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||||
wire core_rsp_fire = core_rsp_if[i].valid && core_rsp_if[i].ready;
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||||
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|
@ -481,7 +486,7 @@ module VX_cache_wrap #(
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|||
wire [`UP(UUID_WIDTH)-1:0] mem_req_uuid;
|
||||
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_uuid;
|
||||
|
||||
if ((UUID_WIDTH != 0) && (NC_ENABLE || PASSTHRU)) begin
|
||||
if ((UUID_WIDTH != 0) && (NC_BYPASS != 0)) begin
|
||||
assign mem_req_uuid = mem_req_if.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
|
||||
assign mem_rsp_uuid = mem_rsp_if.tag[MEM_TAG_WIDTH-1 -: UUID_WIDTH];
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||||
end else begin
|
||||
|
|
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|||
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|
@ -252,7 +252,7 @@ module VX_warp_sched #(
|
|||
assign {schedule_tmask, schedule_pc} = schedule_data[schedule_wid];
|
||||
|
||||
`ifndef NDEBUG
|
||||
assign instr_uuid = (issued_instrs[schedule_wid] * `NUM_WARPS * `NUM_CORES * `NUM_CLUSTERS)
|
||||
assign instr_uuid = UUID_WIDTH'(issued_instrs[schedule_wid] * `NUM_WARPS * `NUM_CORES * `NUM_CLUSTERS)
|
||||
+ UUID_WIDTH'(`NUM_WARPS * CORE_ID)
|
||||
+ UUID_WIDTH'(schedule_wid);
|
||||
`else
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ module VX_mem_scheduler #(
|
|||
parameter ADDR_WIDTH = 32,
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter TAG_WIDTH = 32,
|
||||
parameter MEM_TAG_ID = 0,
|
||||
parameter UUID_WIDTH = 0,
|
||||
parameter MEM_TAG_ID = 0, // upper section of the tag sent to the memory interface
|
||||
parameter UUID_WIDTH = 0, // upper section of the mem_tag_id containing the UUID
|
||||
parameter QUEUE_SIZE = 16,
|
||||
parameter RSP_PARTIAL = 0,
|
||||
parameter CORE_OUT_REG = 0,
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ module VX_tex_unit #(
|
|||
wire req_ready;
|
||||
|
||||
for (genvar i = 0; i < NUM_LANES; ++i) begin
|
||||
assign sel_miplevel[i] = tex_req_if.lod[i][`TEX_LOD_BITS-1:0];
|
||||
assign sel_miplevel[i] = tex_req_if.lod[i][`TEX_LOD_BITS-1:0];
|
||||
assign sel_mipoff[i] = tex_dcrs.mipoff[sel_miplevel[i]];
|
||||
end
|
||||
|
||||
|
|
@ -279,7 +279,7 @@ endmodule
|
|||
module VX_tex_unit_top #(
|
||||
parameter `STRING_TYPE INSTANCE_ID = "",
|
||||
parameter NUM_LANES = `NUM_THREADS,
|
||||
parameter TAG_WIDTH = 8
|
||||
parameter TAG_WIDTH = `TEX_REQ_TAG_WIDTH
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
|
@ -290,15 +290,15 @@ module VX_tex_unit_top #(
|
|||
|
||||
input wire tex_req_valid,
|
||||
input wire [NUM_LANES-1:0] tex_req_mask,
|
||||
input wire [1:0][NUM_LANES-1:0][31:0] tex_req_coords,
|
||||
input wire [1:0][NUM_LANES-1:0][31:0] tex_req_coords,
|
||||
input wire [NUM_LANES-1:0][`TEX_LOD_BITS-1:0] tex_req_lod,
|
||||
input wire [`TEX_STAGE_BITS-1:0] tex_req_stage,
|
||||
input wire [`TEX_REQ_TAG_WIDTH-1:0] tex_req_tag,
|
||||
input wire [TAG_WIDTH-1:0] tex_req_tag,
|
||||
output wire tex_req_ready,
|
||||
|
||||
output wire tex_rsp_valid,
|
||||
output wire [NUM_LANES-1:0][31:0] tex_rsp_texels,
|
||||
output wire [`TEX_REQ_TAG_WIDTH-1:0] tex_rsp_tag,
|
||||
output wire [TAG_WIDTH-1:0] tex_rsp_tag,
|
||||
input wire tex_rsp_ready,
|
||||
|
||||
output wire [TCACHE_NUM_REQS-1:0] cache_req_valid,
|
||||
|
|
@ -325,12 +325,12 @@ module VX_tex_unit_top #(
|
|||
|
||||
VX_tex_req_if #(
|
||||
.NUM_LANES (NUM_LANES),
|
||||
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
|
||||
.TAG_WIDTH (TAG_WIDTH)
|
||||
) tex_req_if();
|
||||
|
||||
VX_tex_rsp_if #(
|
||||
.NUM_LANES (NUM_LANES),
|
||||
.TAG_WIDTH (`TEX_REQ_TAG_WIDTH)
|
||||
.TAG_WIDTH (TAG_WIDTH)
|
||||
) tex_rsp_if();
|
||||
|
||||
assign tex_req_if.valid = tex_req_valid;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue