minor update

hw/rtl/libs/VX_lerp_fx.sv

@@ -1,20 +0,0 @@
-`include "VX_platform.vh"
-
-`TRACING_OFF
-module VX_lerp_fx #(
-    parameter N = 8,
-    parameter F = N
-) (
-    input wire [N-1:0]  in1,
-    input wire [N-1:0]  in2,
-    input wire [F-1:0]  frac,
-    output wire [N-1:0] out
-);
-    wire [F-1:0] One  = {F{1'b1}};
-    wire [F-1:0] Half = One >> 1;
-    wire [F-1:0] sub  = One - frac;
-    wire [N+F:0] tmp  = in1 * sub + in2 * frac + (N+F+1)'(Half);
-    assign out = N'((tmp + (tmp >> F)) >> F);
-
-endmodule
-`TRACING_ON

hw/rtl/tex_unit/VX_tex_lerp.sv

@@ -0,0 +1,15 @@
+`include "VX_platform.vh"
+
+`TRACING_OFF
+module VX_tex_lerp (
+    input wire [7:0]  in1,
+    input wire [7:0]  in2,
+    input wire [7:0]  frac,
+    output wire [7:0] out
+);
+    wire [7:0] sub = (8'hff - frac);
+    wire [16:0] tmp = in1 * sub + in2 * frac + 16'h80;
+    assign out = 8'((tmp + (tmp >> 8)) >> 8);
+
+endmodule
+`TRACING_ON

hw/rtl/tex_unit/VX_tex_sampler.sv

@@ -58,20 +58,14 @@ module VX_tex_sampler #(
 
     for (genvar i = 0; i < NUM_LANES; ++i) begin
         for (genvar j = 0; j < 4; ++j) begin
-            VX_lerp_fx #(
-                .N (8),
-                .F (`TEX_BLEND_FRAC)
-            ) tex_lerp_ul (
+            VX_tex_lerp tex_lerp_ul (
                 .in1  (fmt_texels_s0[i][0][j*8 +: 8]),
                 .in2  (fmt_texels_s0[i][1][j*8 +: 8]),
                 .frac (req_blends_s0[i][0]),
                 .out  (texel_ul[i][j*8 +: 8])
             );
                 
-            VX_lerp_fx #(
-                .N (8),
-                .F (`TEX_BLEND_FRAC)
-            ) tex_lerp_uh (
+            VX_tex_lerp tex_lerp_uh (
                 .in1  (fmt_texels_s0[i][2][j*8 +: 8]),
                 .in2  (fmt_texels_s0[i][3][j*8 +: 8]),
                 .frac (req_blends_s0[i][0]),
@@ -95,10 +89,7 @@ module VX_tex_sampler #(
 
     for (genvar i = 0; i < NUM_LANES; ++i) begin
         for (genvar j = 0; j < 4; ++j) begin
-            VX_lerp_fx #(
-                .N (8),
-                .F (`TEX_BLEND_FRAC)
-            ) tex_lerp_v (
+            VX_tex_lerp tex_lerp_v (
                 .in1  (texel_ul_s1[i][j*8 +: 8]),
                 .in2  (texel_uh_s1[i][j*8 +: 8]),
                 .frac (blend_v_s1[i]),

tests/opencl/common.mk

@@ -4,7 +4,7 @@ TARGET   ?= hw_emu
 PLATFORM ?= xilinx_u280_xdma_201920_3
 
 XRT_SYN_DIR  ?= ../../../hw/syn/xilinx/xrt
-XRT_BUILD_DIR = $(XRT_SYN_DIR)/build_$(PLATFORM)_$(TARGET)/bin
+FPGA_BIN_DIR ?= $(XRT_SYN_DIR)/build_$(PLATFORM)_$(TARGET)/bin
 
 LLVM_VORTEX ?= /opt/llvm-vortex
 RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
@@ -63,9 +63,9 @@ run-opae: $(PROJECT) kernel.pocl
 
 run-xrt: $(PROJECT) kernel.pocl
 ifeq ($(TARGET), hw)
-	XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(XRT_BUILD_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(XRT_BUILD_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_RT_PATH)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+	XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_RT_PATH)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
 else
-	XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(XRT_BUILD_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(XRT_BUILD_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_RT_PATH)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)	
+	XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(POCL_RT_PATH)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)	
 endif
 
 .depend: $(SRCS)

tests/regression/common.mk

@@ -4,7 +4,7 @@ TARGET   ?= hw_emu
 PLATFORM ?= xilinx_u280_xdma_201920_3
 
 XRT_SYN_DIR  ?= ../../../hw/syn/xilinx/xrt
-XRT_BUILD_DIR = $(XRT_SYN_DIR)/build_$(PLATFORM)_$(TARGET)/bin
+FPGA_BIN_DIR ?= $(XRT_SYN_DIR)/build_$(PLATFORM)_$(TARGET)/bin
 
 RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
 
@@ -88,9 +88,9 @@ run-rtlsim: $(PROJECT) kernel.bin
 
 run-xrt: $(PROJECT) kernel.bin
 ifeq ($(TARGET), hw)
-	XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(XRT_BUILD_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(XRT_BUILD_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
+	XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)
 else
-	XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(XRT_BUILD_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(XRT_BUILD_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)	
+	XCL_EMULATION_MODE=$(TARGET) XRT_INI_PATH=$(XRT_SYN_DIR)/xrt.ini EMCONFIG_PATH=$(FPGA_BIN_DIR) XRT_DEVICE_INDEX=0 XRT_XCLBIN_PATH=$(FPGA_BIN_DIR)/vortex_afu.xclbin LD_LIBRARY_PATH=$(XILINX_XRT)/lib:$(VORTEX_RT_PATH)/xrt:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS)	
 endif
 
 .depend: $(SRCS)

tests/regression/draw3d/main.cpp

@@ -545,7 +545,7 @@ int main(int argc, char *argv[]) {
   cleanup();  
 
   if (reference_file) {
-    auto errors = CompareImages(output_file, reference_file, FORMAT_A8R8G8B8);
+    auto errors = CompareImages(output_file, reference_file, FORMAT_A8R8G8B8, 2);
     if (0 == errors) {
       std::cout << "PASSED!" << std::endl;
     } else {