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execute units interfaces refactoring

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This commit is contained in:
Blaise Tine 2023-06-22 16:26:25 -04:00
parent a4c8ea0d8d
commit eb4cbbd4e2
20 changed files with 302 additions and 302 deletions
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60
hw/rtl/core/VX_alu_unit.sv
View file

@ -7,7 +7,7 @@ module VX_alu_unit #(
input wire reset,
// Inputs
VX_alu_req_if.slave alu_req_if,
VX_alu_exe_if.slave alu_exe_if,
// Outputs
VX_branch_ctl_if.master branch_ctl_if,
@ -37,26 +37,26 @@ module VX_alu_unit #(
wire ready_in;
`ifdef XLEN_64
wire is_alu_w = `INST_ALU_IS_W(alu_req_if.op_mod);
wire is_alu_w = `INST_ALU_IS_W(alu_exe_if.op_mod);
`else
wire is_alu_w = 0;
`endif
`UNUSED_VAR (alu_req_if.op_mod)
`UNUSED_VAR (alu_exe_if.op_mod)
wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(alu_req_if.op_type);
wire [`INST_BR_BITS-1:0] br_op = `INST_BR_BITS'(alu_req_if.op_type);
wire is_br_op = `INST_ALU_IS_BR(alu_req_if.op_mod);
wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(alu_exe_if.op_type);
wire [`INST_BR_BITS-1:0] br_op = `INST_BR_BITS'(alu_exe_if.op_type);
wire is_br_op = `INST_ALU_IS_BR(alu_exe_if.op_mod);
wire is_sub_op = `INST_ALU_IS_SUB(alu_op);
wire alu_signed = `INST_ALU_SIGNED(alu_op);
wire [1:0] alu_op_class = `INST_ALU_CLASS(alu_op);
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in1 = alu_req_if.rs1_data;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2 = alu_req_if.rs2_data;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in1 = alu_exe_if.rs1_data;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2 = alu_exe_if.rs2_data;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in1_PC = alu_req_if.use_PC ? {`NUM_THREADS{alu_req_if.PC}} : alu_in1;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2_imm = alu_req_if.use_imm ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2_br = (alu_req_if.use_imm && ~is_br_op) ? {`NUM_THREADS{alu_req_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in1_PC = alu_exe_if.use_PC ? {`NUM_THREADS{alu_exe_if.PC}} : alu_in1;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2_imm = alu_exe_if.use_imm ? {`NUM_THREADS{alu_exe_if.imm}} : alu_in2;
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_in2_br = (alu_exe_if.use_imm && ~is_br_op) ? {`NUM_THREADS{alu_exe_if.imm}} : alu_in2;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];
@ -108,8 +108,8 @@ module VX_alu_unit #(
// branch
wire [`XLEN-1:0] br_dest = add_result[alu_req_if.tid][`XLEN-1:0];
wire [`XLEN:0] cmp_result = sub_result[alu_req_if.tid][`XLEN:0];
wire [`XLEN-1:0] br_dest = add_result[alu_exe_if.tid][`XLEN-1:0];
wire [`XLEN:0] cmp_result = sub_result[alu_exe_if.tid][`XLEN:0];
wire is_less = cmp_result[`XLEN];
wire is_equal = ~(| cmp_result[`XLEN-1:0]);
@ -117,7 +117,7 @@ module VX_alu_unit #(
wire [`NUM_THREADS-1:0][`XLEN-1:0] alu_jal_result;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign alu_jal_result[i] = (is_br_op && is_br_static) ? alu_req_if.next_PC : alu_result[i];
assign alu_jal_result[i] = (is_br_op && is_br_static) ? alu_exe_if.next_PC : alu_result[i];
end
// output
@ -149,7 +149,7 @@ module VX_alu_unit #(
.clk (clk),
.reset (reset),
.enable (alu_ready_in),
.data_in ({alu_valid_in, alu_req_if.uuid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, is_less, is_equal, br_dest}),
.data_in ({alu_valid_in, alu_exe_if.uuid, alu_exe_if.wid, alu_exe_if.tmask, alu_exe_if.PC, alu_exe_if.rd, alu_exe_if.wb, alu_jal_result, is_br_op, br_op, is_less, is_equal, br_dest}),
.data_out ({alu_valid_out, alu_uuid, alu_wid, alu_tmask, alu_PC, alu_rd, alu_wb, alu_data, is_br_op_r, br_op_r, is_less_r, is_equal_r, br_dest_r})
);
@ -177,7 +177,7 @@ module VX_alu_unit #(
wire muldiv_wb;
wire [`NUM_THREADS-1:0][`XLEN-1:0] muldiv_data;
wire [`INST_M_BITS-1:0] muldiv_op = `INST_M_BITS'(alu_req_if.op_type);
wire [`INST_M_BITS-1:0] muldiv_op = `INST_M_BITS'(alu_exe_if.op_type);
`RESET_RELAY (muldiv_reset, reset);
@ -188,15 +188,15 @@ module VX_alu_unit #(
// Inputs
.valid_in (muldiv_valid_in),
.alu_op (muldiv_op),
.op_mod (alu_req_if.op_mod),
.uuid_in (alu_req_if.uuid),
.wid_in (alu_req_if.wid),
.tmask_in (alu_req_if.tmask),
.PC_in (alu_req_if.PC),
.rd_in (alu_req_if.rd),
.wb_in (alu_req_if.wb),
.alu_in1 (alu_req_if.rs1_data),
.alu_in2 (alu_req_if.rs2_data),
.op_mod (alu_exe_if.op_mod),
.uuid_in (alu_exe_if.uuid),
.wid_in (alu_exe_if.wid),
.tmask_in (alu_exe_if.tmask),
.PC_in (alu_exe_if.PC),
.rd_in (alu_exe_if.rd),
.wb_in (alu_exe_if.wb),
.alu_in1 (alu_exe_if.rs1_data),
.alu_in2 (alu_exe_if.rs2_data),
.ready_in (muldiv_ready_in),
// Outputs
@ -211,15 +211,15 @@ module VX_alu_unit #(
.ready_out (muldiv_ready_out)
);
wire is_muldiv_op = `INST_ALU_IS_M(alu_req_if.op_mod);
wire is_muldiv_op = `INST_ALU_IS_M(alu_exe_if.op_mod);
assign alu_valid_in = alu_req_if.valid && ~is_muldiv_op;
assign muldiv_valid_in = alu_req_if.valid && is_muldiv_op;
assign alu_valid_in = alu_exe_if.valid && ~is_muldiv_op;
assign muldiv_valid_in = alu_exe_if.valid && is_muldiv_op;
assign ready_in = is_muldiv_op ? muldiv_ready_in : alu_ready_in;
`else
assign alu_valid_in = alu_req_if.valid;
assign alu_valid_in = alu_exe_if.valid;
assign ready_in = alu_ready_in;
`endif
@ -260,7 +260,7 @@ module VX_alu_unit #(
assign alu_commit_if.eop = 1'b1;
// can accept new request?
assign alu_req_if.ready = ready_in;
assign alu_exe_if.ready = ready_in;
`ifdef DBG_TRACE_CORE_PIPELINE
always @(posedge clk) begin

30
hw/rtl/core/VX_core.sv
View file

@ -86,13 +86,13 @@ module VX_core #(
VX_commit_csr_if commit_csr_if();
VX_branch_ctl_if branch_ctl_if();
VX_warp_ctl_if warp_ctl_if();
VX_alu_req_if alu_req_if();
VX_lsu_req_if lsu_req_if();
VX_csr_req_if csr_req_if();
VX_alu_exe_if alu_exe_if();
VX_lsu_exe_if lsu_exe_if();
VX_csr_exe_if csr_exe_if();
`ifdef EXT_F_ENABLE
VX_fpu_agent_if fpu_agent_if();
VX_fpu_exe_if fpu_exe_if();
`endif
VX_gpu_req_if gpu_req_if();
VX_gpu_exe_if gpu_exe_if();
VX_schedule_if schedule_if();
VX_fetch_if fetch_if();
VX_decode_if decode_if();
@ -185,13 +185,13 @@ module VX_core #(
.decode_if (decode_if),
.writeback_if (writeback_if),
.alu_req_if (alu_req_if),
.lsu_req_if (lsu_req_if),
.csr_req_if (csr_req_if),
.alu_exe_if (alu_exe_if),
.lsu_exe_if (lsu_exe_if),
.csr_exe_if (csr_exe_if),
`ifdef EXT_F_ENABLE
.fpu_agent_if (fpu_agent_if),
.fpu_exe_if (fpu_exe_if),
`endif
.gpu_req_if (gpu_req_if)
.gpu_exe_if (gpu_exe_if)
);
VX_execute #(
@ -212,7 +212,7 @@ module VX_core #(
.dcache_bus_if (dcache_bus_if),
`ifdef EXT_F_ENABLE
.fpu_agent_if (fpu_agent_if),
.fpu_exe_if (fpu_exe_if),
.fpu_bus_if (fpu_bus_if),
.fpu_commit_if (fpu_commit_if),
`endif
@ -244,10 +244,10 @@ module VX_core #(
.commit_csr_if (commit_csr_if),
.sched_csr_if (sched_csr_if),
.alu_req_if (alu_req_if),
.lsu_req_if (lsu_req_if),
.csr_req_if (csr_req_if),
.gpu_req_if (gpu_req_if),
.alu_exe_if (alu_exe_if),
.lsu_exe_if (lsu_exe_if),
.csr_exe_if (csr_exe_if),
.gpu_exe_if (gpu_exe_if),
.warp_ctl_if (warp_ctl_if),
.branch_ctl_if (branch_ctl_if),

96
hw/rtl/core/VX_csr_unit.sv
View file

@ -43,7 +43,7 @@ module VX_csr_unit #(
VX_commit_csr_if.slave commit_csr_if,
VX_sched_csr_if.slave sched_csr_if,
VX_csr_req_if.slave csr_req_if,
VX_csr_exe_if.slave csr_exe_if,
VX_commit_if.master csr_commit_if,
`ifdef EXT_F_ENABLE
@ -75,68 +75,68 @@ module VX_csr_unit #(
`endif
);
wire csr_req_valid = csr_req_if.valid && ~csr_access_pending;
wire csr_req_valid = csr_exe_if.valid && ~csr_access_pending;
wire csr_req_ready;
// can accept new request?
assign csr_req_if.ready = csr_req_ready && ~csr_access_pending;
assign csr_exe_if.ready = csr_req_ready && ~csr_access_pending;
wire csr_write_enable = (csr_req_if.op_type == `INST_CSR_RW);
wire csr_write_enable = (csr_exe_if.op_type == `INST_CSR_RW);
`ifdef EXT_TEX_ENABLE
wire tex_addr_enable = (csr_req_if.addr >= `CSR_TEX_BEGIN && csr_req_if.addr < `CSR_TEX_END);
wire tex_addr_enable = (csr_exe_if.addr >= `CSR_TEX_BEGIN && csr_exe_if.addr < `CSR_TEX_END);
assign tex_csr_if.read_enable = csr_req_valid && ~csr_write_enable && tex_addr_enable;
assign tex_csr_if.read_uuid = csr_req_if.uuid;
assign tex_csr_if.read_wid = csr_req_if.wid;
assign tex_csr_if.read_tmask = csr_req_if.tmask;
assign tex_csr_if.read_addr = csr_req_if.addr;
assign tex_csr_if.read_uuid = csr_exe_if.uuid;
assign tex_csr_if.read_wid = csr_exe_if.wid;
assign tex_csr_if.read_tmask = csr_exe_if.tmask;
assign tex_csr_if.read_addr = csr_exe_if.addr;
`UNUSED_VAR (tex_csr_if.read_data)
assign tex_csr_if.write_enable = csr_req_valid && csr_write_enable && tex_addr_enable;
assign tex_csr_if.write_uuid = csr_req_if.uuid;
assign tex_csr_if.write_wid = csr_req_if.wid;
assign tex_csr_if.write_tmask = csr_req_if.tmask;
assign tex_csr_if.write_addr = csr_req_if.addr;
assign tex_csr_if.write_data = csr_req_if.rs1_data;
assign tex_csr_if.write_uuid = csr_exe_if.uuid;
assign tex_csr_if.write_wid = csr_exe_if.wid;
assign tex_csr_if.write_tmask = csr_exe_if.tmask;
assign tex_csr_if.write_addr = csr_exe_if.addr;
assign tex_csr_if.write_data = csr_exe_if.rs1_data;
`endif
`ifdef EXT_RASTER_ENABLE
wire raster_addr_enable = (csr_req_if.addr >= `CSR_RASTER_BEGIN && csr_req_if.addr < `CSR_RASTER_END);
wire raster_addr_enable = (csr_exe_if.addr >= `CSR_RASTER_BEGIN && csr_exe_if.addr < `CSR_RASTER_END);
assign raster_csr_if.read_enable = csr_req_valid && ~csr_write_enable && raster_addr_enable;
assign raster_csr_if.read_uuid = csr_req_if.uuid;
assign raster_csr_if.read_wid = csr_req_if.wid;
assign raster_csr_if.read_tmask = csr_req_if.tmask;
assign raster_csr_if.read_addr = csr_req_if.addr;
assign raster_csr_if.read_uuid = csr_exe_if.uuid;
assign raster_csr_if.read_wid = csr_exe_if.wid;
assign raster_csr_if.read_tmask = csr_exe_if.tmask;
assign raster_csr_if.read_addr = csr_exe_if.addr;
assign raster_csr_if.write_enable = csr_req_valid && csr_write_enable && raster_addr_enable;
assign raster_csr_if.write_uuid = csr_req_if.uuid;
assign raster_csr_if.write_wid = csr_req_if.wid;
assign raster_csr_if.write_tmask = csr_req_if.tmask;
assign raster_csr_if.write_addr = csr_req_if.addr;
assign raster_csr_if.write_data = csr_req_if.rs1_data;
assign raster_csr_if.write_uuid = csr_exe_if.uuid;
assign raster_csr_if.write_wid = csr_exe_if.wid;
assign raster_csr_if.write_tmask = csr_exe_if.tmask;
assign raster_csr_if.write_addr = csr_exe_if.addr;
assign raster_csr_if.write_data = csr_exe_if.rs1_data;
`endif
`ifdef EXT_ROP_ENABLE
wire rop_addr_enable = (csr_req_if.addr >= `CSR_ROP_BEGIN && csr_req_if.addr < `CSR_ROP_END);
wire rop_addr_enable = (csr_exe_if.addr >= `CSR_ROP_BEGIN && csr_exe_if.addr < `CSR_ROP_END);
assign rop_csr_if.read_enable = csr_req_valid && ~csr_write_enable && rop_addr_enable;
assign rop_csr_if.read_uuid = csr_req_if.uuid;
assign rop_csr_if.read_wid = csr_req_if.wid;
assign rop_csr_if.read_tmask = csr_req_if.tmask;
assign rop_csr_if.read_addr = csr_req_if.addr;
assign rop_csr_if.read_uuid = csr_exe_if.uuid;
assign rop_csr_if.read_wid = csr_exe_if.wid;
assign rop_csr_if.read_tmask = csr_exe_if.tmask;
assign rop_csr_if.read_addr = csr_exe_if.addr;
`UNUSED_VAR (rop_csr_if.read_data)
assign rop_csr_if.write_enable = csr_req_valid && csr_write_enable && rop_addr_enable;
assign rop_csr_if.write_uuid = csr_req_if.uuid;
assign rop_csr_if.write_wid = csr_req_if.wid;
assign rop_csr_if.write_tmask = csr_req_if.tmask;
assign rop_csr_if.write_addr = csr_req_if.addr;
assign rop_csr_if.write_data = csr_req_if.rs1_data;
assign rop_csr_if.write_uuid = csr_exe_if.uuid;
assign rop_csr_if.write_wid = csr_exe_if.wid;
assign rop_csr_if.write_tmask = csr_exe_if.tmask;
assign rop_csr_if.write_addr = csr_exe_if.addr;
assign rop_csr_if.write_data = csr_exe_if.rs1_data;
`endif
VX_csr_data #(
@ -173,17 +173,17 @@ module VX_csr_unit #(
`endif
.read_enable (csr_req_valid && csr_rd_enable),
.read_uuid (csr_req_if.uuid),
.read_wid (csr_req_if.wid),
.read_tmask (csr_req_if.tmask),
.read_addr (csr_req_if.addr),
.read_uuid (csr_exe_if.uuid),
.read_wid (csr_exe_if.wid),
.read_tmask (csr_exe_if.tmask),
.read_addr (csr_exe_if.addr),
.read_data_ro (csr_read_data_ro[31:0]),
.read_data_rw (csr_read_data_rw[31:0]),
.write_enable (csr_req_valid && csr_wr_enable),
.write_uuid (csr_req_if.uuid),
.write_wid (csr_req_if.wid),
.write_addr (csr_req_if.addr),
.write_uuid (csr_exe_if.uuid),
.write_wid (csr_exe_if.wid),
.write_addr (csr_exe_if.addr),
.write_data (csr_write_data[31:0])
);
@ -193,8 +193,8 @@ module VX_csr_unit #(
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign wtid[i] = 32'(i);
assign ltid[i] = (32'(csr_req_if.wid) << `NT_BITS) + i;
assign gtid[i] = 32'((CORE_ID << (`NW_BITS + `NT_BITS)) + (32'(csr_req_if.wid) << `NT_BITS) + i);
assign ltid[i] = (32'(csr_exe_if.wid) << `NT_BITS) + i;
assign gtid[i] = 32'((CORE_ID << (`NW_BITS + `NT_BITS)) + (32'(csr_exe_if.wid) << `NT_BITS) + i);
end
always @(*) begin
@ -204,7 +204,7 @@ module VX_csr_unit #(
csr_read_data = raster_csr_if.read_data;
end else
`endif
case (csr_req_if.addr)
case (csr_exe_if.addr)
`CSR_WTID : csr_read_data = wtid;
`CSR_LTID : csr_read_data = ltid;
`CSR_GTID : csr_read_data = gtid;
@ -217,7 +217,7 @@ module VX_csr_unit #(
// CSR write
assign csr_req_data = csr_req_if.use_imm ? 32'(csr_req_if.imm) : csr_req_if.rs1_data[csr_req_if.tid];
assign csr_req_data = csr_exe_if.use_imm ? 32'(csr_exe_if.imm) : csr_exe_if.rs1_data[csr_exe_if.tid];
assign csr_wr_enable = (csr_write_enable || (csr_req_data != 0))
`ifdef EXT_ROP_ENABLE
@ -226,7 +226,7 @@ module VX_csr_unit #(
;
always @(*) begin
case (csr_req_if.op_type)
case (csr_exe_if.op_type)
`INST_CSR_RW: begin
csr_write_data = csr_req_data;
end
@ -250,7 +250,7 @@ module VX_csr_unit #(
.reset (reset),
.valid_in (csr_req_valid),
.ready_in (csr_req_ready),
.data_in ({csr_req_if.uuid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.rd, csr_req_if.wb, csr_read_data}),
.data_in ({csr_exe_if.uuid, csr_exe_if.wid, csr_exe_if.tmask, csr_exe_if.PC, csr_exe_if.rd, csr_exe_if.wb, csr_read_data}),
.data_out ({csr_commit_if.uuid, csr_commit_if.wid, csr_commit_if.tmask, csr_commit_if.PC, csr_commit_if.rd, csr_commit_if.wb, csr_commit_data}),
.valid_out (csr_commit_if.valid),
.ready_out (csr_commit_if.ready)
@ -268,7 +268,7 @@ module VX_csr_unit #(
if (reset) begin
req_pending_r <= 0;
end else begin
if (csr_req_if.valid && csr_req_if.ready) begin
if (csr_exe_if.valid && csr_exe_if.ready) begin
req_pending_r <= 1;
end
if (csr_commit_if.valid && csr_commit_if.ready) begin

42
hw/rtl/core/VX_dispatch.sv
View file

@ -8,13 +8,13 @@ module VX_dispatch (
VX_dispatch_if.slave dispatch_if,
// outputs
VX_alu_req_if.master alu_req_if,
VX_lsu_req_if.master lsu_req_if,
VX_csr_req_if.master csr_req_if,
VX_alu_exe_if.master alu_exe_if,
VX_lsu_exe_if.master lsu_exe_if,
VX_csr_exe_if.master csr_exe_if,
`ifdef EXT_F_ENABLE
VX_fpu_agent_if.master fpu_agent_if,
VX_fpu_exe_if.master fpu_exe_if,
`endif
VX_gpu_req_if.master gpu_req_if
VX_gpu_exe_if.master gpu_exe_if
);
localparam UUID_WIDTH = `UP(`UUID_BITS);
localparam NW_WIDTH = `UP(`NW_BITS);
@ -53,9 +53,9 @@ module VX_dispatch (
.valid_in (alu_req_valid),
.ready_in (alu_req_ready),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, next_PC, alu_op_type, dispatch_if.op_mod, dispatch_if.imm, dispatch_if.use_PC, dispatch_if.use_imm, dispatch_if.rd, dispatch_if.wb, tid, dispatch_if.rs1_data, dispatch_if.rs2_data}),
.data_out ({alu_req_if.uuid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}),
.valid_out (alu_req_if.valid),
.ready_out (alu_req_if.ready)
.data_out ({alu_exe_if.uuid, alu_exe_if.wid, alu_exe_if.tmask, alu_exe_if.PC, alu_exe_if.next_PC, alu_exe_if.op_type, alu_exe_if.op_mod, alu_exe_if.imm, alu_exe_if.use_PC, alu_exe_if.use_imm, alu_exe_if.rd, alu_exe_if.wb, alu_exe_if.tid, alu_exe_if.rs1_data, alu_exe_if.rs2_data}),
.valid_out (alu_exe_if.valid),
.ready_out (alu_exe_if.ready)
);
// lsu unit
@ -72,9 +72,9 @@ module VX_dispatch (
.valid_in (lsu_req_valid),
.ready_in (lsu_req_ready),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, lsu_op_type, dispatch_if.imm, dispatch_if.rd, dispatch_if.wb, dispatch_if.rs1_data, dispatch_if.rs2_data}),
.data_out ({lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
.valid_out (lsu_req_if.valid),
.ready_out (lsu_req_if.ready)
.data_out ({lsu_exe_if.uuid, lsu_exe_if.wid, lsu_exe_if.tmask, lsu_exe_if.PC, lsu_exe_if.op_type, lsu_exe_if.offset, lsu_exe_if.rd, lsu_exe_if.wb, lsu_exe_if.base_addr, lsu_exe_if.store_data}),
.valid_out (lsu_exe_if.valid),
.ready_out (lsu_exe_if.ready)
);
// csr unit
@ -98,9 +98,9 @@ module VX_dispatch (
.valid_in (csr_req_valid),
.ready_in (csr_req_ready),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, csr_op_type, csr_addr, dispatch_if.rd, dispatch_if.wb, dispatch_if.use_imm, csr_imm, tid, csr_data}),
.data_out ({csr_req_if.uuid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.imm, csr_req_if.tid, csr_req_if.rs1_data}),
.valid_out (csr_req_if.valid),
.ready_out (csr_req_if.ready)
.data_out ({csr_exe_if.uuid, csr_exe_if.wid, csr_exe_if.tmask, csr_exe_if.PC, csr_exe_if.op_type, csr_exe_if.addr, csr_exe_if.rd, csr_exe_if.wb, csr_exe_if.use_imm, csr_exe_if.imm, csr_exe_if.tid, csr_exe_if.rs1_data}),
.valid_out (csr_exe_if.valid),
.ready_out (csr_exe_if.ready)
);
// fpu unit
@ -119,10 +119,10 @@ module VX_dispatch (
.reset (reset),
.valid_in (fpu_req_valid),
.ready_in (fpu_req_ready),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, fpu_op_type, fpu_fmt, fpu_frm, dispatch_if.rd, dispatch_if.rs1_data, dispatch_if.rs2_data, dispatch_if.rs3_data}),
.data_out ({fpu_agent_if.uuid, fpu_agent_if.wid, fpu_agent_if.tmask, fpu_agent_if.PC, fpu_agent_if.op_type, fpu_agent_if.fmt, fpu_agent_if.frm, fpu_agent_if.rd, fpu_agent_if.rs1_data, fpu_agent_if.rs2_data, fpu_agent_if.rs3_data}),
.valid_out (fpu_agent_if.valid),
.ready_out (fpu_agent_if.ready)
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, fpu_op_type, fpu_fmt, fpu_frm, dispatch_if.rd, dispatch_if.rs1_data, dispatch_if.rs2_data, dispatch_if.rs3_data}),
.data_out ({fpu_exe_if.uuid, fpu_exe_if.wid, fpu_exe_if.tmask, fpu_exe_if.PC, fpu_exe_if.op_type, fpu_exe_if.fmt, fpu_exe_if.frm, fpu_exe_if.rd, fpu_exe_if.rs1_data, fpu_exe_if.rs2_data, fpu_exe_if.rs3_data}),
.valid_out (fpu_exe_if.valid),
.ready_out (fpu_exe_if.ready)
);
`else
`UNUSED_VAR (dispatch_if.rs3_data)
@ -142,9 +142,9 @@ module VX_dispatch (
.valid_in (gpu_req_valid),
.ready_in (gpu_req_ready),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, next_PC, gpu_op_type, dispatch_if.op_mod, dispatch_if.rd, dispatch_if.wb, tid, dispatch_if.rs1_data, dispatch_if.rs2_data, dispatch_if.rs3_data}),
.data_out ({gpu_req_if.uuid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.op_mod, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.tid, gpu_req_if.rs1_data, gpu_req_if.rs2_data, gpu_req_if.rs3_data}),
.valid_out (gpu_req_if.valid),
.ready_out (gpu_req_if.ready)
.data_out ({gpu_exe_if.uuid, gpu_exe_if.wid, gpu_exe_if.tmask, gpu_exe_if.PC, gpu_exe_if.next_PC, gpu_exe_if.op_type, gpu_exe_if.op_mod, gpu_exe_if.rd, gpu_exe_if.wb, gpu_exe_if.tid, gpu_exe_if.rs1_data, gpu_exe_if.rs2_data, gpu_exe_if.rs3_data}),
.valid_out (gpu_exe_if.valid),
.ready_out (gpu_exe_if.ready)
);
// can take next request?

28
hw/rtl/core/VX_execute.sv
View file

@ -30,7 +30,7 @@ module VX_execute #(
`endif
`ifdef EXT_F_ENABLE
VX_fpu_agent_if.slave fpu_agent_if,
VX_fpu_exe_if.slave fpu_exe_if,
VX_fpu_bus_if.master fpu_bus_if,
VX_commit_if.master fpu_commit_if,
`endif
@ -59,18 +59,18 @@ module VX_execute #(
`endif
`endif
VX_alu_req_if.slave alu_req_if,
VX_alu_exe_if.slave alu_exe_if,
VX_branch_ctl_if.master branch_ctl_if,
VX_commit_if.master alu_commit_if,
VX_lsu_req_if.slave lsu_req_if,
VX_lsu_exe_if.slave lsu_exe_if,
VX_commit_if.master ld_commit_if,
VX_commit_if.master st_commit_if,
VX_csr_req_if.slave csr_req_if,
VX_csr_exe_if.slave csr_exe_if,
VX_commit_if.master csr_commit_if,
VX_gpu_req_if.slave gpu_req_if,
VX_gpu_exe_if.slave gpu_exe_if,
VX_warp_ctl_if.master warp_ctl_if,
VX_commit_if.master gpu_commit_if,
@ -112,7 +112,7 @@ module VX_execute #(
) alu_unit (
.clk (clk),
.reset (alu_reset),
.alu_req_if (alu_req_if),
.alu_exe_if (alu_exe_if),
.branch_ctl_if (branch_ctl_if),
.alu_commit_if (alu_commit_if)
);
@ -126,7 +126,7 @@ module VX_execute #(
.clk (clk),
.reset (lsu_reset),
.cache_bus_if (dcache_bus_if),
.lsu_req_if (lsu_req_if),
.lsu_exe_if (lsu_exe_if),
.ld_commit_if (ld_commit_if),
.st_commit_if (st_commit_if)
);
@ -180,7 +180,7 @@ module VX_execute #(
.commit_csr_if (commit_csr_if),
.sched_csr_if (sched_csr_if),
.csr_req_if (csr_req_if),
.csr_exe_if (csr_exe_if),
.csr_commit_if (csr_commit_if)
);
@ -192,7 +192,7 @@ module VX_execute #(
) fpu_agent (
.clk (clk),
.reset (fpu_reset),
.fpu_agent_if (fpu_agent_if),
.fpu_exe_if (fpu_exe_if),
.fpu_bus_if (fpu_bus_if),
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_commit_if (fpu_commit_if),
@ -206,7 +206,7 @@ module VX_execute #(
) gpu_unit (
.clk (clk),
.reset (gpu_reset),
.gpu_req_if (gpu_req_if),
.gpu_exe_if (gpu_exe_if),
`ifdef PERF_ENABLE
.gpu_perf_if (gpu_perf_if),
@ -235,9 +235,9 @@ module VX_execute #(
);
// simulation helper signal to get RISC-V tests Pass/Fail status
assign sim_ebreak = alu_req_if.valid && alu_req_if.ready
&& `INST_ALU_IS_BR(alu_req_if.op_mod)
&& (`INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_EBREAK
|| `INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_ECALL);
assign sim_ebreak = alu_exe_if.valid && alu_exe_if.ready
&& `INST_ALU_IS_BR(alu_exe_if.op_mod)
&& (`INST_BR_BITS'(alu_exe_if.op_type) == `INST_BR_EBREAK
|| `INST_BR_BITS'(alu_exe_if.op_type) == `INST_BR_ECALL);
endmodule

138
hw/rtl/core/VX_gpu_unit.sv
View file

@ -16,7 +16,7 @@ module VX_gpu_unit #(
`endif
// Inputs
VX_gpu_req_if.slave gpu_req_if,
VX_gpu_exe_if.slave gpu_exe_if,
`ifdef EXT_TEX_ENABLE
VX_gpu_csr_if.slave tex_csr_if,
@ -70,7 +70,7 @@ module VX_gpu_unit #(
reg gpu_req_ready;
wire csr_ready = ~csr_pending;
assign gpu_req_valid = gpu_req_if.valid && csr_ready;
assign gpu_req_valid = gpu_exe_if.valid && csr_ready;
// Warp control block
@ -79,28 +79,28 @@ module VX_gpu_unit #(
gpu_barrier_t barrier;
gpu_split_t split;
wire is_wspawn = (gpu_req_if.op_type == `INST_GPU_WSPAWN);
wire is_tmc = (gpu_req_if.op_type == `INST_GPU_TMC);
wire is_split = (gpu_req_if.op_type == `INST_GPU_SPLIT);
wire is_join = (gpu_req_if.op_type == `INST_GPU_JOIN);
wire is_bar = (gpu_req_if.op_type == `INST_GPU_BAR);
wire is_pred = (gpu_req_if.op_type == `INST_GPU_PRED);
wire is_wspawn = (gpu_exe_if.op_type == `INST_GPU_WSPAWN);
wire is_tmc = (gpu_exe_if.op_type == `INST_GPU_TMC);
wire is_split = (gpu_exe_if.op_type == `INST_GPU_SPLIT);
wire is_join = (gpu_exe_if.op_type == `INST_GPU_JOIN);
wire is_bar = (gpu_exe_if.op_type == `INST_GPU_BAR);
wire is_pred = (gpu_exe_if.op_type == `INST_GPU_PRED);
wire [`XLEN-1:0] rs1_data = gpu_req_if.rs1_data[gpu_req_if.tid];
wire [`XLEN-1:0] rs2_data = gpu_req_if.rs2_data[gpu_req_if.tid];
wire [`XLEN-1:0] rs1_data = gpu_exe_if.rs1_data[gpu_exe_if.tid];
wire [`XLEN-1:0] rs2_data = gpu_exe_if.rs2_data[gpu_exe_if.tid];
wire [`NUM_THREADS-1:0] taken_tmask;
wire [`NUM_THREADS-1:0] not_taken_tmask;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire taken = (gpu_req_if.rs1_data[i] != 0);
assign taken_tmask[i] = gpu_req_if.tmask[i] && taken;
assign not_taken_tmask[i] = gpu_req_if.tmask[i] && ~taken;
wire taken = (gpu_exe_if.rs1_data[i] != 0);
assign taken_tmask[i] = gpu_exe_if.tmask[i] && taken;
assign not_taken_tmask[i] = gpu_exe_if.tmask[i] && ~taken;
end
// tmc
wire [`NUM_THREADS-1:0] pred_mask = (taken_tmask != 0) ? taken_tmask : gpu_req_if.tmask;
wire [`NUM_THREADS-1:0] pred_mask = (taken_tmask != 0) ? taken_tmask : gpu_exe_if.tmask;
assign tmc.valid = is_tmc || is_pred;
assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0];
@ -122,7 +122,7 @@ module VX_gpu_unit #(
assign split.diverged = (| taken_tmask) && (| not_taken_tmask);
assign split.then_tmask = taken_tmask;
assign split.else_tmask = not_taken_tmask;
assign split.pc = gpu_req_if.next_PC;
assign split.pc = gpu_exe_if.next_PC;
// barrier
@ -139,31 +139,31 @@ module VX_gpu_unit #(
wire wctl_req_ready = wctl_rsp_ready;
assign rsp_arb_valid_in[RSP_ARB_IDX_GPU] = wctl_rsp_valid;
assign rsp_arb_data_in[RSP_ARB_IDX_GPU] = {gpu_req_if.uuid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, `NR_BITS'(0), 1'b0, RSP_DATAW'(wctl_rsp_data), 1'b1, ~is_join};
assign rsp_arb_data_in[RSP_ARB_IDX_GPU] = {gpu_exe_if.uuid, gpu_exe_if.wid, gpu_exe_if.tmask, gpu_exe_if.PC, `NR_BITS'(0), 1'b0, RSP_DATAW'(wctl_rsp_data), 1'b1, ~is_join};
assign wctl_rsp_ready = rsp_arb_ready_in[RSP_ARB_IDX_GPU];
`UNUSED_VAR (gpu_req_if.op_mod)
`UNUSED_VAR (gpu_req_if.rs3_data)
`UNUSED_VAR (gpu_req_if.wb)
`UNUSED_VAR (gpu_req_if.rd)
`UNUSED_VAR (gpu_exe_if.op_mod)
`UNUSED_VAR (gpu_exe_if.rs3_data)
`UNUSED_VAR (gpu_exe_if.wb)
`UNUSED_VAR (gpu_exe_if.rd)
`ifdef EXT_TEX_ENABLE
VX_tex_agent_if tex_agent_if();
VX_tex_exe_if tex_exe_if();
VX_commit_if tex_commit_if();
assign tex_agent_if.valid = gpu_req_valid && (gpu_req_if.op_type == `INST_GPU_TEX);
assign tex_agent_if.uuid = gpu_req_if.uuid;
assign tex_agent_if.wid = gpu_req_if.wid;
assign tex_agent_if.tmask = gpu_req_if.tmask;
assign tex_agent_if.PC = gpu_req_if.PC;
assign tex_agent_if.rd = gpu_req_if.rd;
assign tex_agent_if.stage = gpu_req_if.op_mod[`TEX_STAGE_BITS-1:0];
assign tex_exe_if.valid = gpu_req_valid && (gpu_exe_if.op_type == `INST_GPU_TEX);
assign tex_exe_if.uuid = gpu_exe_if.uuid;
assign tex_exe_if.wid = gpu_exe_if.wid;
assign tex_exe_if.tmask = gpu_exe_if.tmask;
assign tex_exe_if.PC = gpu_exe_if.PC;
assign tex_exe_if.rd = gpu_exe_if.rd;
assign tex_exe_if.stage = gpu_exe_if.op_mod[`TEX_STAGE_BITS-1:0];
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign tex_agent_if.coords[0][i] = gpu_req_if.rs1_data[i];
assign tex_agent_if.coords[1][i] = gpu_req_if.rs2_data[i];
assign tex_agent_if.lod[i] = gpu_req_if.rs3_data[i][0 +: `TEX_LOD_BITS];
assign tex_exe_if.coords[0][i] = gpu_exe_if.rs1_data[i];
assign tex_exe_if.coords[1][i] = gpu_exe_if.rs2_data[i];
assign tex_exe_if.lod[i] = gpu_exe_if.rs3_data[i][0 +: `TEX_LOD_BITS];
end
`RESET_RELAY (tex_reset, reset);
@ -174,7 +174,7 @@ module VX_gpu_unit #(
.clk (clk),
.reset (tex_reset),
.tex_csr_if (tex_csr_if),
.tex_agent_if (tex_agent_if),
.tex_exe_if (tex_exe_if),
.tex_commit_if (tex_commit_if),
.tex_bus_if (tex_bus_if)
);
@ -187,15 +187,15 @@ module VX_gpu_unit #(
`ifdef EXT_RASTER_ENABLE
VX_raster_agent_if raster_agent_if();
VX_commit_if raster_commit_if();
VX_raster_exe_if raster_exe_if();
VX_commit_if raster_commit_if();
assign raster_agent_if.valid = gpu_req_valid && (gpu_req_if.op_type == `INST_GPU_RASTER);
assign raster_agent_if.uuid = gpu_req_if.uuid;
assign raster_agent_if.wid = gpu_req_if.wid;
assign raster_agent_if.tmask = gpu_req_if.tmask;
assign raster_agent_if.PC = gpu_req_if.PC;
assign raster_agent_if.rd = gpu_req_if.rd;
assign raster_exe_if.valid = gpu_req_valid && (gpu_exe_if.op_type == `INST_GPU_RASTER);
assign raster_exe_if.uuid = gpu_exe_if.uuid;
assign raster_exe_if.wid = gpu_exe_if.wid;
assign raster_exe_if.tmask = gpu_exe_if.tmask;
assign raster_exe_if.PC = gpu_exe_if.PC;
assign raster_exe_if.rd = gpu_exe_if.rd;
`RESET_RELAY (raster_reset, reset);
@ -206,7 +206,7 @@ module VX_gpu_unit #(
.reset (raster_reset),
.raster_csr_if (raster_csr_if),
.raster_bus_if (raster_bus_if),
.raster_agent_if (raster_agent_if),
.raster_exe_if (raster_exe_if),
.raster_commit_if (raster_commit_if)
);
@ -218,21 +218,21 @@ module VX_gpu_unit #(
`ifdef EXT_ROP_ENABLE
VX_rop_agent_if rop_agent_if();
VX_commit_if rop_commit_if();
VX_rop_exe_if rop_exe_if();
VX_commit_if rop_commit_if();
assign rop_agent_if.valid = gpu_req_valid && (gpu_req_if.op_type == `INST_GPU_ROP);
assign rop_agent_if.uuid = gpu_req_if.uuid;
assign rop_agent_if.wid = gpu_req_if.wid;
assign rop_agent_if.tmask = gpu_req_if.tmask;
assign rop_agent_if.PC = gpu_req_if.PC;
assign rop_exe_if.valid = gpu_req_valid && (gpu_exe_if.op_type == `INST_GPU_ROP);
assign rop_exe_if.uuid = gpu_exe_if.uuid;
assign rop_exe_if.wid = gpu_exe_if.wid;
assign rop_exe_if.tmask = gpu_exe_if.tmask;
assign rop_exe_if.PC = gpu_exe_if.PC;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign rop_agent_if.face[i] = gpu_req_if.rs1_data[i][0];
assign rop_agent_if.pos_x[i] = gpu_req_if.rs1_data[i][1 +: `ROP_DIM_BITS];
assign rop_agent_if.pos_y[i] = gpu_req_if.rs1_data[i][16 +: `ROP_DIM_BITS];
assign rop_agent_if.color[i] = gpu_req_if.rs2_data[i];
assign rop_agent_if.depth[i] = gpu_req_if.rs3_data[i][`ROP_DEPTH_BITS-1:0];
assign rop_exe_if.face[i] = gpu_exe_if.rs1_data[i][0];
assign rop_exe_if.pos_x[i] = gpu_exe_if.rs1_data[i][1 +: `ROP_DIM_BITS];
assign rop_exe_if.pos_y[i] = gpu_exe_if.rs1_data[i][16 +: `ROP_DIM_BITS];
assign rop_exe_if.color[i] = gpu_exe_if.rs2_data[i];
assign rop_exe_if.depth[i] = gpu_exe_if.rs3_data[i][`ROP_DEPTH_BITS-1:0];
end
`RESET_RELAY (rop_reset, reset);
@ -243,7 +243,7 @@ module VX_gpu_unit #(
.clk (clk),
.reset (rop_reset),
.rop_csr_if (rop_csr_if),
.rop_agent_if (rop_agent_if),
.rop_exe_if (rop_exe_if),
.rop_commit_if (rop_commit_if),
.rop_bus_if (rop_bus_if)
);
@ -268,7 +268,7 @@ module VX_gpu_unit #(
wire [`NUM_THREADS-1:0][31:0] imadd_data_out;
wire imadd_ready_out;
assign imadd_valid_in = gpu_req_valid && (gpu_req_if.op_type == `INST_GPU_IMADD);
assign imadd_valid_in = gpu_req_valid && (gpu_exe_if.op_type == `INST_GPU_IMADD);
`RESET_RELAY (imadd_reset, reset);
@ -284,11 +284,11 @@ module VX_gpu_unit #(
// Inputs
.valid_in (imadd_valid_in),
.shift_in ({gpu_req_if.op_mod[1:0], 3'b0}),
.data1_in (gpu_req_if.rs1_data),
.data2_in (gpu_req_if.rs2_data),
.data3_in (gpu_req_if.rs3_data),
.tag_in ({gpu_req_if.uuid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.rd}),
.shift_in ({gpu_exe_if.op_mod[1:0], 3'b0}),
.data1_in (gpu_exe_if.rs1_data),
.data2_in (gpu_exe_if.rs2_data),
.data3_in (gpu_exe_if.rs3_data),
.tag_in ({gpu_exe_if.uuid, gpu_exe_if.wid, gpu_exe_if.tmask, gpu_exe_if.PC, gpu_exe_if.rd}),
.ready_in (imadd_ready_in),
// Outputs
@ -307,15 +307,15 @@ module VX_gpu_unit #(
// can accept new request?
always @(*) begin
case (gpu_req_if.op_type)
case (gpu_exe_if.op_type)
`ifdef EXT_TEX_ENABLE
`INST_GPU_TEX: gpu_req_ready = tex_agent_if.ready;
`INST_GPU_TEX: gpu_req_ready = tex_exe_if.ready;
`endif
`ifdef EXT_RASTER_ENABLE
`INST_GPU_RASTER: gpu_req_ready = raster_agent_if.ready;
`INST_GPU_RASTER: gpu_req_ready = raster_exe_if.ready;
`endif
`ifdef EXT_ROP_ENABLE
`INST_GPU_ROP: gpu_req_ready = rop_agent_if.ready;
`INST_GPU_ROP: gpu_req_ready = rop_exe_if.ready;
`endif
`ifdef EXT_IMADD_ENABLE
`INST_GPU_IMADD: gpu_req_ready = imadd_ready_in;
@ -323,7 +323,7 @@ module VX_gpu_unit #(
default: gpu_req_ready = wctl_req_ready;
endcase
end
assign gpu_req_if.ready = gpu_req_ready && csr_ready;
assign gpu_exe_if.ready = gpu_req_ready && csr_ready;
// response arbitration
@ -347,7 +347,7 @@ module VX_gpu_unit #(
// warp control reponse
wire gpu_req_fire = gpu_req_if.valid && gpu_req_if.ready;
wire gpu_req_fire = gpu_exe_if.valid && gpu_exe_if.ready;
wire gpu_commit_fire = gpu_commit_if.valid && gpu_commit_if.ready;
assign warp_ctl_if.valid = gpu_commit_fire && rsp_is_wctl;
@ -378,7 +378,7 @@ module VX_gpu_unit #(
if (reset) begin
perf_tex_stalls <= '0;
end else begin
perf_tex_stalls <= perf_tex_stalls + `PERF_CTR_BITS'(tex_agent_if.valid && ~tex_agent_if.ready);
perf_tex_stalls <= perf_tex_stalls + `PERF_CTR_BITS'(tex_exe_if.valid && ~tex_exe_if.ready);
end
end
assign gpu_perf_if.tex_stalls = perf_tex_stalls;
@ -389,7 +389,7 @@ module VX_gpu_unit #(
if (reset) begin
perf_raster_stalls <= '0;
end else begin
perf_raster_stalls <= perf_raster_stalls + `PERF_CTR_BITS'(raster_agent_if.valid && ~raster_agent_if.ready);
perf_raster_stalls <= perf_raster_stalls + `PERF_CTR_BITS'(raster_exe_if.valid && ~raster_exe_if.ready);
end
end
assign gpu_perf_if.raster_stalls = perf_raster_stalls;
@ -400,7 +400,7 @@ module VX_gpu_unit #(
if (reset) begin
perf_rop_stalls <= '0;
end else begin
perf_rop_stalls <= perf_rop_stalls + `PERF_CTR_BITS'(rop_agent_if.valid && ~rop_agent_if.ready);
perf_rop_stalls <= perf_rop_stalls + `PERF_CTR_BITS'(rop_exe_if.valid && ~rop_exe_if.ready);
end
end
assign gpu_perf_if.rop_stalls = perf_rop_stalls;

20
hw/rtl/core/VX_issue.sv
View file

@ -18,13 +18,13 @@ module VX_issue #(
VX_decode_if.slave decode_if,
VX_writeback_if.slave writeback_if,
VX_alu_req_if.master alu_req_if,
VX_lsu_req_if.master lsu_req_if,
VX_csr_req_if.master csr_req_if,
VX_alu_exe_if.master alu_exe_if,
VX_lsu_exe_if.master lsu_exe_if,
VX_csr_exe_if.master csr_exe_if,
`ifdef EXT_F_ENABLE
VX_fpu_agent_if.master fpu_agent_if,
VX_fpu_exe_if.master fpu_exe_if,
`endif
VX_gpu_req_if.master gpu_req_if
VX_gpu_exe_if.master gpu_exe_if
);
VX_ibuffer_if ibuffer_if();
VX_gpr_stage_if gpr_stage_if();
@ -123,13 +123,13 @@ module VX_issue #(
.clk (clk),
.reset (dispatch_reset),
.dispatch_if(dispatch_if),
.alu_req_if (alu_req_if),
.lsu_req_if (lsu_req_if),
.csr_req_if (csr_req_if),
.alu_exe_if (alu_exe_if),
.lsu_exe_if (lsu_exe_if),
.csr_exe_if (csr_exe_if),
`ifdef EXT_F_ENABLE
.fpu_agent_if(fpu_agent_if),
.fpu_exe_if (fpu_exe_if),
`endif
.gpu_req_if (gpu_req_if)
.gpu_exe_if (gpu_exe_if)
);
wire ibuffer_if_fire = ibuffer_if.valid && ibuffer_if.ready;

68
hw/rtl/core/VX_lsu_unit.sv
View file

@ -17,7 +17,7 @@ module VX_lsu_unit #(
VX_cache_bus_if.master cache_bus_if,
// inputs
VX_lsu_req_if.slave lsu_req_if,
VX_lsu_exe_if.slave lsu_exe_if,
// outputs
VX_commit_if.master ld_commit_if,
@ -61,7 +61,7 @@ module VX_lsu_unit #(
wire [`NUM_THREADS-1:0][`XLEN-1:0] full_addr;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign full_addr[i] = lsu_req_if.base_addr[i][`XLEN-1:0] + lsu_req_if.offset;
assign full_addr[i] = lsu_exe_if.base_addr[i][`XLEN-1:0] + lsu_exe_if.offset;
end
// detect duplicate addresses
@ -70,9 +70,9 @@ module VX_lsu_unit #(
if (`NUM_THREADS > 1) begin
wire [`NUM_THREADS-2:0] addr_matches;
for (genvar i = 0; i < (`NUM_THREADS-1); ++i) begin
assign addr_matches[i] = (lsu_req_if.base_addr[i+1] == lsu_req_if.base_addr[0]) || ~lsu_req_if.tmask[i+1];
assign addr_matches[i] = (lsu_exe_if.base_addr[i+1] == lsu_exe_if.base_addr[0]) || ~lsu_exe_if.tmask[i+1];
end
assign lsu_is_dup = lsu_req_if.tmask[0] && (& addr_matches);
assign lsu_is_dup = lsu_exe_if.tmask[0] && (& addr_matches);
end else begin
assign lsu_is_dup = 0;
end
@ -101,11 +101,11 @@ module VX_lsu_unit #(
wire lsu_valid, lsu_ready;
// fence: stall the pipeline until all pending requests are sent
wire is_fence = `INST_LSU_IS_FENCE(lsu_req_if.op_type);
wire is_fence = `INST_LSU_IS_FENCE(lsu_exe_if.op_type);
wire fence_wait = is_fence && ~mem_req_empty;
assign lsu_valid = lsu_req_if.valid && ~fence_wait;
assign lsu_req_if.ready = lsu_ready && ~fence_wait;
assign lsu_valid = lsu_exe_if.valid && ~fence_wait;
assign lsu_exe_if.ready = lsu_ready && ~fence_wait;
// schedule memory request
@ -129,10 +129,10 @@ module VX_lsu_unit #(
assign lsu_ready = mem_req_ready;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign mem_req_mask[i] = lsu_req_if.tmask[i] && (~lsu_is_dup || (i == 0));
assign mem_req_mask[i] = lsu_exe_if.tmask[i] && (~lsu_is_dup || (i == 0));
end
assign mem_req_rw = ~lsu_req_if.wb;
assign mem_req_rw = ~lsu_exe_if.wb;
// address formatting
@ -146,8 +146,8 @@ module VX_lsu_unit #(
// data formatting
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
always @(*) begin
mem_req_byteen[i] = {DCACHE_WORD_SIZE{lsu_req_if.wb}};
case (`INST_LSU_WSIZE(lsu_req_if.op_type))
mem_req_byteen[i] = {DCACHE_WORD_SIZE{lsu_exe_if.wb}};
case (`INST_LSU_WSIZE(lsu_exe_if.op_type))
0: begin // 8-bit
mem_req_byteen[i][req_align[i]] = 1;
end
@ -168,28 +168,28 @@ module VX_lsu_unit #(
end
// memory misalignment not supported!
wire lsu_req_fire = lsu_req_if.valid && lsu_req_if.ready;
`RUNTIME_ASSERT((~lsu_req_fire || ~lsu_req_if.tmask[i] || is_fence || (full_addr[i] % (1 << `INST_LSU_WSIZE(lsu_req_if.op_type))) == 0),
("misaligned memory access, PC=0x%0h, addr=0x%0h, wsize=%0d!", lsu_req_if.PC, full_addr[i], `INST_LSU_WSIZE(lsu_req_if.op_type)));
wire lsu_req_fire = lsu_exe_if.valid && lsu_exe_if.ready;
`RUNTIME_ASSERT((~lsu_req_fire || ~lsu_exe_if.tmask[i] || is_fence || (full_addr[i] % (1 << `INST_LSU_WSIZE(lsu_exe_if.op_type))) == 0),
("misaligned memory access, PC=0x%0h, addr=0x%0h, wsize=%0d!", lsu_exe_if.PC, full_addr[i], `INST_LSU_WSIZE(lsu_exe_if.op_type)));
always @(*) begin
mem_req_data[i] = lsu_req_if.store_data[i];
mem_req_data[i] = lsu_exe_if.store_data[i];
case (req_align[i])
1: mem_req_data[i][`XLEN-1:8] = lsu_req_if.store_data[i][`XLEN-9:0];
2: mem_req_data[i][`XLEN-1:16] = lsu_req_if.store_data[i][`XLEN-17:0];
3: mem_req_data[i][`XLEN-1:24] = lsu_req_if.store_data[i][`XLEN-25:0];
1: mem_req_data[i][`XLEN-1:8] = lsu_exe_if.store_data[i][`XLEN-9:0];
2: mem_req_data[i][`XLEN-1:16] = lsu_exe_if.store_data[i][`XLEN-17:0];
3: mem_req_data[i][`XLEN-1:24] = lsu_exe_if.store_data[i][`XLEN-25:0];
`ifdef XLEN_64
4: mem_req_data[i][`XLEN-1:32] = lsu_req_if.store_data[i][`XLEN-33:0];
5: mem_req_data[i][`XLEN-1:40] = lsu_req_if.store_data[i][`XLEN-41:0];
6: mem_req_data[i][`XLEN-1:48] = lsu_req_if.store_data[i][`XLEN-49:0];
7: mem_req_data[i][`XLEN-1:56] = lsu_req_if.store_data[i][`XLEN-57:0];
4: mem_req_data[i][`XLEN-1:32] = lsu_exe_if.store_data[i][`XLEN-33:0];
5: mem_req_data[i][`XLEN-1:40] = lsu_exe_if.store_data[i][`XLEN-41:0];
6: mem_req_data[i][`XLEN-1:48] = lsu_exe_if.store_data[i][`XLEN-49:0];
7: mem_req_data[i][`XLEN-1:56] = lsu_exe_if.store_data[i][`XLEN-57:0];
`endif
default:;
endcase
end
end
assign mem_req_tag = {lsu_req_if.uuid, lsu_addr_type, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rd, lsu_req_if.op_type, req_align, lsu_is_dup};
assign mem_req_tag = {lsu_exe_if.uuid, lsu_addr_type, lsu_exe_if.wid, lsu_exe_if.tmask, lsu_exe_if.PC, lsu_exe_if.rd, lsu_exe_if.op_type, req_align, lsu_is_dup};
VX_cache_bus_if #(
.NUM_REQS (DCACHE_NUM_REQS),
@ -324,10 +324,10 @@ module VX_lsu_unit #(
// send store commit
assign st_commit_if.valid = mem_req_fire && mem_req_rw;
assign st_commit_if.uuid = lsu_req_if.uuid;
assign st_commit_if.wid = lsu_req_if.wid;
assign st_commit_if.tmask = lsu_req_if.tmask;
assign st_commit_if.PC = lsu_req_if.PC;
assign st_commit_if.uuid = lsu_exe_if.uuid;
assign st_commit_if.wid = lsu_exe_if.wid;
assign st_commit_if.tmask = lsu_exe_if.tmask;
assign st_commit_if.PC = lsu_exe_if.PC;
assign st_commit_if.rd = '0;
assign st_commit_if.wb = 0;
assign st_commit_if.eop = 1;
@ -405,7 +405,7 @@ module VX_lsu_unit #(
.start(1'b0),
.stop(1'b0),
.triggers({reset, mem_req_fire, mem_rsp_fire}),
.probes({lsu_req_if.uuid, full_addr, mem_req_rw, mem_req_byteen, mem_req_data, rsp_uuid, rsp_data}),
.probes({lsu_exe_if.uuid, full_addr, mem_req_rw, mem_req_byteen, mem_req_data, rsp_uuid, rsp_data}),
.bus_in(scope_bus_in),
.bus_out(scope_bus_out)
);
@ -416,7 +416,7 @@ module VX_lsu_unit #(
wire [31:0] rsp_data_0 = rsp_data[0];
ila_lsu ila_lsu_inst (
.clk (clk),
.probe0 ({mem_req_data_0, lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.PC, mem_req_mask, full_addr_0, mem_req_byteen, mem_req_rw, mem_req_ready, mem_req_valid}),
.probe0 ({mem_req_data_0, lsu_exe_if.uuid, lsu_exe_if.wid, lsu_exe_if.PC, mem_req_mask, full_addr_0, mem_req_byteen, mem_req_rw, mem_req_ready, mem_req_valid}),
.probe1 ({rsp_data_0, rsp_uuid, mem_rsp_eop, rsp_pc, rsp_rd, rsp_tmask, rsp_wid, mem_rsp_ready, mem_rsp_valid}),
.probe2 ({cache_bus_if.req_data, cache_bus_if.req_tag, cache_bus_if.req_byteen, cache_bus_if.req_addr, cache_bus_if.req_rw, cache_bus_if.req_ready, cache_bus_if.req_valid}),
.probe3 ({cache_bus_if.rsp_data, cache_bus_if.rsp_tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid})
@ -429,24 +429,24 @@ module VX_lsu_unit #(
`ifdef DBG_TRACE_CORE_DCACHE
always @(posedge clk) begin
if (lsu_req_if.valid && fence_wait) begin
if (lsu_exe_if.valid && fence_wait) begin
`TRACE(1, ("%d: *** D$%0d fence wait\n", $time, CORE_ID));
end
if (mem_req_fire) begin
if (mem_req_rw) begin
`TRACE(1, ("%d: D$%0d Wr Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, mem_req_mask));
`TRACE(1, ("%d: D$%0d Wr Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, lsu_exe_if.wid, lsu_exe_if.PC, mem_req_mask));
`TRACE_ARRAY1D(1, full_addr, `NUM_THREADS);
`TRACE(1, (", tag=0x%0h, byteen=0x%0h, type=", mem_req_tag, mem_req_byteen));
`TRACE_ARRAY1D(1, lsu_addr_type, `NUM_THREADS);
`TRACE(1, (", data="));
`TRACE_ARRAY1D(1, mem_req_data, `NUM_THREADS);
`TRACE(1, (", is_dup=%b (#%0d)\n", lsu_is_dup, lsu_req_if.uuid));
`TRACE(1, (", is_dup=%b (#%0d)\n", lsu_is_dup, lsu_exe_if.uuid));
end else begin
`TRACE(1, ("%d: D$%0d Rd Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.PC, mem_req_mask));
`TRACE(1, ("%d: D$%0d Rd Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, lsu_exe_if.wid, lsu_exe_if.PC, mem_req_mask));
`TRACE_ARRAY1D(1, full_addr, `NUM_THREADS);
`TRACE(1, (", tag=0x%0h, byteen=0x%0h, type=", mem_req_tag, mem_req_byteen));
`TRACE_ARRAY1D(1, lsu_addr_type, `NUM_THREADS);
`TRACE(1, (", rd=%0d, is_dup=%b (#%0d)\n", lsu_req_if.rd, lsu_is_dup, lsu_req_if.uuid));
`TRACE(1, (", rd=%0d, is_dup=%b (#%0d)\n", lsu_exe_if.rd, lsu_is_dup, lsu_exe_if.uuid));
end
end
if (mem_rsp_fire) begin

22
hw/rtl/fpu/VX_fpu_agent.sv
View file

@ -11,7 +11,7 @@ module VX_fpu_agent #(
input wire clk,
input wire reset,
VX_fpu_agent_if.slave fpu_agent_if,
VX_fpu_exe_if.slave fpu_exe_if,
VX_fpu_to_csr_if.master fpu_to_csr_if,
VX_commit_if.master fpu_commit_if,
@ -36,7 +36,7 @@ module VX_fpu_agent #(
wire [`FPU_REQ_TAG_WIDTH-1:0] req_tag, rsp_tag;
wire mdata_full;
wire fpu_agent_fire = fpu_agent_if.valid && fpu_agent_if.ready;
wire fpu_agent_fire = fpu_exe_if.valid && fpu_exe_if.ready;
wire fpu_rsp_fire = fpu_bus_if.rsp_valid && fpu_bus_if.rsp_ready;
assign rsp_tag = fpu_bus_if.rsp_tag;
@ -51,8 +51,8 @@ module VX_fpu_agent #(
.write_addr (req_tag),
.read_addr (rsp_tag),
.release_addr (rsp_tag),
.write_data ({fpu_agent_if.uuid, fpu_agent_if.wid, fpu_agent_if.tmask, fpu_agent_if.PC, fpu_agent_if.rd}),
.read_data ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd}),
.write_data ({fpu_exe_if.uuid, fpu_exe_if.wid, fpu_exe_if.tmask, fpu_exe_if.PC, fpu_exe_if.rd}),
.read_data ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd}),
.release_slot (fpu_rsp_fire),
.full (mdata_full),
`UNUSED_PIN (empty)
@ -60,17 +60,17 @@ module VX_fpu_agent #(
// resolve dynamic FRM from CSR
wire [`INST_FRM_BITS-1:0] req_op_frm;
assign fpu_to_csr_if.read_wid = fpu_agent_if.wid;
assign req_op_frm = (fpu_agent_if.op_type != `INST_FPU_MISC
&& fpu_agent_if.frm == `INST_FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_agent_if.frm;
assign fpu_to_csr_if.read_wid = fpu_exe_if.wid;
assign req_op_frm = (fpu_exe_if.op_type != `INST_FPU_MISC
&& fpu_exe_if.frm == `INST_FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_exe_if.frm;
// submit FPU request
wire mdata_and_csr_ready = ~mdata_full && ~csr_pending;
wire valid_in, ready_in;
assign valid_in = fpu_agent_if.valid && mdata_and_csr_ready;
assign fpu_agent_if.ready = ready_in && mdata_and_csr_ready;
assign valid_in = fpu_exe_if.valid && mdata_and_csr_ready;
assign fpu_exe_if.ready = ready_in && mdata_and_csr_ready;
VX_skid_buffer #(
.DATAW (`INST_FPU_BITS + `INST_FMT_BITS + `INST_FRM_BITS + `NUM_THREADS * 3 * `XLEN + `FPU_REQ_TAG_WIDTH),
@ -80,8 +80,8 @@ module VX_fpu_agent #(
.reset (reset),
.valid_in (valid_in),
.ready_in (ready_in),
.data_in ({fpu_agent_if.op_type, fpu_agent_if.fmt, req_op_frm, fpu_agent_if.rs1_data, fpu_agent_if.rs2_data, fpu_agent_if.rs3_data, req_tag}),
.data_out ({fpu_bus_if.req_type, fpu_bus_if.req_fmt, fpu_bus_if.req_frm, fpu_bus_if.req_dataa, fpu_bus_if.req_datab, fpu_bus_if.req_datac, fpu_bus_if.req_tag}),
.data_in ({fpu_exe_if.op_type, fpu_exe_if.fmt, req_op_frm, fpu_exe_if.rs1_data, fpu_exe_if.rs2_data, fpu_exe_if.rs3_data, req_tag}),
.data_out ({fpu_bus_if.req_type, fpu_bus_if.req_fmt, fpu_bus_if.req_frm, fpu_bus_if.req_dataa, fpu_bus_if.req_datab, fpu_bus_if.req_datac, fpu_bus_if.req_tag}),
.valid_out (fpu_bus_if.req_valid),
.ready_out (fpu_bus_if.req_ready)
);

2
hw/rtl/fpu/VX_fpu_agent_if.sv → hw/rtl/fpu/VX_fpu_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_fpu_agent_if ();
interface VX_fpu_exe_if ();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;

2
hw/rtl/interfaces/VX_alu_req_if.sv → hw/rtl/interfaces/VX_alu_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_alu_req_if ();
interface VX_alu_exe_if ();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;

2
hw/rtl/interfaces/VX_csr_req_if.sv → hw/rtl/interfaces/VX_csr_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_csr_req_if ();
interface VX_csr_exe_if ();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;

2
hw/rtl/interfaces/VX_gpu_req_if.sv → hw/rtl/interfaces/VX_gpu_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_gpu_req_if();
interface VX_gpu_exe_if();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;

2
hw/rtl/interfaces/VX_lsu_req_if.sv → hw/rtl/interfaces/VX_lsu_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_lsu_req_if ();
interface VX_lsu_exe_if ();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;

26
hw/rtl/raster/VX_raster_agent.sv
View file

@ -7,7 +7,7 @@ module VX_raster_agent #(
input wire reset,
// Inputs
VX_raster_agent_if.slave raster_agent_if,
VX_raster_exe_if.slave raster_exe_if,
VX_raster_bus_if.slave raster_bus_if,
// Outputs
@ -23,7 +23,7 @@ module VX_raster_agent #(
// CSRs access
wire csr_write_enable = raster_bus_if.req_valid && raster_agent_if.valid && raster_rsp_ready;
wire csr_write_enable = raster_bus_if.req_valid && raster_exe_if.valid && raster_rsp_ready;
VX_raster_csr #(
.CORE_ID (CORE_ID)
@ -32,22 +32,22 @@ module VX_raster_agent #(
.reset (reset),
// inputs
.write_enable (csr_write_enable),
.write_uuid (raster_agent_if.uuid),
.write_wid (raster_agent_if.wid),
.write_tmask (raster_agent_if.tmask),
.write_uuid (raster_exe_if.uuid),
.write_wid (raster_exe_if.wid),
.write_tmask (raster_exe_if.tmask),
.write_data (raster_bus_if.req_stamps),
// outputs
.raster_csr_if (raster_csr_if)
);
// it is possible to have ready = f(valid) when using arbiters,
// because of that we need to decouple raster_agent_if and raster_commit_if handshake with a pipe register
// because of that we need to decouple raster_exe_if and raster_commit_if handshake with a pipe register
assign raster_agent_if.ready = raster_bus_if.req_valid && raster_rsp_ready;
assign raster_exe_if.ready = raster_bus_if.req_valid && raster_rsp_ready;
assign raster_bus_if.req_ready = raster_agent_if.valid && raster_rsp_ready;
assign raster_bus_if.req_ready = raster_exe_if.valid && raster_rsp_ready;
assign raster_rsp_valid = raster_agent_if.valid && raster_bus_if.req_valid;
assign raster_rsp_valid = raster_exe_if.valid && raster_bus_if.req_valid;
wire [`NUM_THREADS-1:0][31:0] response_data;
@ -62,7 +62,7 @@ module VX_raster_agent #(
.reset (reset),
.valid_in (raster_rsp_valid),
.ready_in (raster_rsp_ready),
.data_in ({raster_agent_if.uuid, raster_agent_if.wid, raster_agent_if.tmask, raster_agent_if.PC, raster_agent_if.rd, response_data}),
.data_in ({raster_exe_if.uuid, raster_exe_if.wid, raster_exe_if.tmask, raster_exe_if.PC, raster_exe_if.rd, response_data}),
.data_out ({raster_commit_if.uuid, raster_commit_if.wid, raster_commit_if.tmask, raster_commit_if.PC, raster_commit_if.rd, raster_commit_if.data}),
.valid_out (raster_commit_if.valid),
.ready_out (raster_commit_if.ready)
@ -73,16 +73,16 @@ module VX_raster_agent #(
`ifdef DBG_TRACE_RASTER
always @(posedge clk) begin
if (raster_agent_if.valid && raster_agent_if.ready) begin
if (raster_exe_if.valid && raster_exe_if.ready) begin
for (integer i = 0; i < `NUM_THREADS; ++i) begin
`TRACE(1, ("%d: core%0d-raster-stamp[%0d]: wid=%0d, PC=0x%0h, tmask=%b, done=%b, x=%0d, y=%0d, mask=%0d, pid=%0d, bcoords={{0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}, {0x%0h, 0x%0h, 0x%0h}} (#%0d)\n",
$time, CORE_ID, i, raster_agent_if.wid, raster_agent_if.PC, raster_agent_if.tmask,
$time, CORE_ID, i, raster_exe_if.wid, raster_exe_if.PC, raster_exe_if.tmask,
raster_bus_if.req_done,
raster_bus_if.req_stamps[i].pos_x, raster_bus_if.req_stamps[i].pos_y, raster_bus_if.req_stamps[i].mask, raster_bus_if.req_stamps[i].pid,
raster_bus_if.req_stamps[i].bcoords[0][0], raster_bus_if.req_stamps[i].bcoords[1][0], raster_bus_if.req_stamps[i].bcoords[2][0],
raster_bus_if.req_stamps[i].bcoords[0][1], raster_bus_if.req_stamps[i].bcoords[1][1], raster_bus_if.req_stamps[i].bcoords[2][1],
raster_bus_if.req_stamps[i].bcoords[0][2], raster_bus_if.req_stamps[i].bcoords[1][2], raster_bus_if.req_stamps[i].bcoords[2][2],
raster_bus_if.req_stamps[i].bcoords[0][3], raster_bus_if.req_stamps[i].bcoords[1][3], raster_bus_if.req_stamps[i].bcoords[2][3], raster_agent_if.uuid));
raster_bus_if.req_stamps[i].bcoords[0][3], raster_bus_if.req_stamps[i].bcoords[1][3], raster_bus_if.req_stamps[i].bcoords[2][3], raster_exe_if.uuid));
end
end
end

2
hw/rtl/raster/VX_raster_agent_if.sv → hw/rtl/raster/VX_raster_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_raster_define.vh"
interface VX_raster_agent_if ();
interface VX_raster_exe_if ();
wire valid;

30
hw/rtl/rop/VX_rop_agent.sv
View file

@ -7,7 +7,7 @@ module VX_rop_agent #(
input wire reset,
// Inputs
VX_rop_agent_if.slave rop_agent_if,
VX_rop_exe_if.slave rop_exe_if,
VX_gpu_csr_if.slave rop_csr_if,
// Outputs
@ -42,7 +42,7 @@ module VX_rop_agent #(
wire rop_rsp_valid, rop_rsp_ready;
// it is possible to have ready = f(valid) when using arbiters,
// because of that we need to decouple rop_agent_if and rop_commit_if handshake with a pipe register
// because of that we need to decouple rop_exe_if and rop_commit_if handshake with a pipe register
VX_skid_buffer #(
.DATAW (UUID_WIDTH + `NUM_THREADS * (1 + 2 * `ROP_DIM_BITS + 32 + `ROP_DEPTH_BITS + 1)),
@ -52,15 +52,15 @@ module VX_rop_agent #(
.reset (reset),
.valid_in (rop_req_valid),
.ready_in (rop_req_ready),
.data_in ({rop_agent_if.uuid, rop_agent_if.tmask, rop_agent_if.pos_x, rop_agent_if.pos_y, rop_agent_if.color, rop_agent_if.depth, rop_agent_if.face}),
.data_in ({rop_exe_if.uuid, rop_exe_if.tmask, rop_exe_if.pos_x, rop_exe_if.pos_y, rop_exe_if.color, rop_exe_if.depth, rop_exe_if.face}),
.data_out ({rop_bus_if.req_uuid, rop_bus_if.req_mask, rop_bus_if.req_pos_x, rop_bus_if.req_pos_y, rop_bus_if.req_color, rop_bus_if.req_depth, rop_bus_if.req_face}),
.valid_out (rop_bus_if.req_valid),
.ready_out (rop_bus_if.req_ready)
);
assign rop_req_valid = rop_agent_if.valid && rop_rsp_ready;
assign rop_agent_if.ready = rop_req_ready && rop_rsp_ready;
assign rop_rsp_valid = rop_agent_if.valid && rop_req_ready;
assign rop_req_valid = rop_exe_if.valid && rop_rsp_ready;
assign rop_exe_if.ready = rop_req_ready && rop_rsp_ready;
assign rop_rsp_valid = rop_exe_if.valid && rop_req_ready;
VX_skid_buffer #(
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32)
@ -69,7 +69,7 @@ module VX_rop_agent #(
.reset (reset),
.valid_in (rop_rsp_valid),
.ready_in (rop_rsp_ready),
.data_in ({rop_agent_if.uuid, rop_agent_if.wid, rop_agent_if.tmask, rop_agent_if.PC}),
.data_in ({rop_exe_if.uuid, rop_exe_if.wid, rop_exe_if.tmask, rop_exe_if.PC}),
.data_out ({rop_commit_if.uuid, rop_commit_if.wid, rop_commit_if.tmask, rop_commit_if.PC}),
.valid_out (rop_commit_if.valid),
.ready_out (rop_commit_if.ready)
@ -82,18 +82,18 @@ module VX_rop_agent #(
`ifdef DBG_TRACE_ROP
always @(posedge clk) begin
if (rop_agent_if.valid && rop_agent_if.ready) begin
`TRACE(1, ("%d: core%0d-rop-req: wid=%0d, PC=0x%0h, tmask=%b, x=", $time, CORE_ID, rop_agent_if.wid, rop_agent_if.PC, rop_agent_if.tmask));
`TRACE_ARRAY1D(1, rop_agent_if.pos_x, `NUM_THREADS);
if (rop_exe_if.valid && rop_exe_if.ready) begin
`TRACE(1, ("%d: core%0d-rop-req: wid=%0d, PC=0x%0h, tmask=%b, x=", $time, CORE_ID, rop_exe_if.wid, rop_exe_if.PC, rop_exe_if.tmask));
`TRACE_ARRAY1D(1, rop_exe_if.pos_x, `NUM_THREADS);
`TRACE(1, (", y="));
`TRACE_ARRAY1D(1, rop_agent_if.pos_y, `NUM_THREADS);
`TRACE_ARRAY1D(1, rop_exe_if.pos_y, `NUM_THREADS);
`TRACE(1, (", face="));
`TRACE_ARRAY1D(1, rop_agent_if.face, `NUM_THREADS);
`TRACE_ARRAY1D(1, rop_exe_if.face, `NUM_THREADS);
`TRACE(1, (", color="));
`TRACE_ARRAY1D(1, rop_agent_if.color, `NUM_THREADS);
`TRACE_ARRAY1D(1, rop_exe_if.color, `NUM_THREADS);
`TRACE(1, (", depth="));
`TRACE_ARRAY1D(1, rop_agent_if.depth, `NUM_THREADS);
`TRACE(1, (", face=%b (#%0d)\n", rop_agent_if.face, rop_agent_if.uuid));
`TRACE_ARRAY1D(1, rop_exe_if.depth, `NUM_THREADS);
`TRACE(1, (", face=%b (#%0d)\n", rop_exe_if.face, rop_exe_if.uuid));
end
end
`endif

2
hw/rtl/rop/VX_rop_agent_if.sv → hw/rtl/rop/VX_rop_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_rop_define.vh"
interface VX_rop_agent_if ();
interface VX_rop_exe_if ();
wire valid;

28
hw/rtl/tex/VX_tex_agent.sv
View file

@ -8,7 +8,7 @@ module VX_tex_agent #(
// Inputs
VX_gpu_csr_if.slave tex_csr_if,
VX_tex_agent_if.slave tex_agent_if,
VX_tex_exe_if.slave tex_exe_if,
// Outputs
VX_tex_bus_if.master tex_bus_if,
@ -51,7 +51,7 @@ module VX_tex_agent #(
wire mdata_full;
wire mdata_push = tex_agent_if.valid && tex_agent_if.ready;
wire mdata_push = tex_exe_if.valid && tex_exe_if.ready;
wire mdata_pop = tex_bus_if.rsp_valid && tex_bus_if.rsp_ready;
VX_index_buffer #(
@ -64,8 +64,8 @@ module VX_tex_agent #(
.write_addr (mdata_waddr),
.read_addr (mdata_raddr),
.release_addr (mdata_raddr),
.write_data ({tex_agent_if.wid, tex_agent_if.tmask, tex_agent_if.PC, tex_agent_if.rd}),
.read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd}),
.write_data ({tex_exe_if.wid, tex_exe_if.tmask, tex_exe_if.PC, tex_exe_if.rd}),
.read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd}),
.release_slot (mdata_pop),
.full (mdata_full),
`UNUSED_PIN (empty)
@ -74,10 +74,10 @@ module VX_tex_agent #(
// submit texture request
wire valid_in, ready_in;
assign valid_in = tex_agent_if.valid && ~mdata_full;
assign tex_agent_if.ready = ready_in && ~mdata_full;
assign valid_in = tex_exe_if.valid && ~mdata_full;
assign tex_exe_if.ready = ready_in && ~mdata_full;
wire [`TEX_REQ_TAG_WIDTH-1:0] req_tag = {tex_agent_if.uuid, mdata_waddr};
wire [`TEX_REQ_TAG_WIDTH-1:0] req_tag = {tex_exe_if.uuid, mdata_waddr};
VX_skid_buffer #(
.DATAW (`NUM_THREADS * (1 + 2 * 32 + `TEX_LOD_BITS) + `TEX_STAGE_BITS + `TEX_REQ_TAG_WIDTH),
@ -87,7 +87,7 @@ module VX_tex_agent #(
.reset (reset),
.valid_in (valid_in),
.ready_in (ready_in),
.data_in ({tex_agent_if.tmask, tex_agent_if.coords, tex_agent_if.lod, tex_agent_if.stage, req_tag}),
.data_in ({tex_exe_if.tmask, tex_exe_if.coords, tex_exe_if.lod, tex_exe_if.stage, req_tag}),
.data_out ({tex_bus_if.req_mask, tex_bus_if.req_coords, tex_bus_if.req_lod, tex_bus_if.req_stage, tex_bus_if.req_tag}),
.valid_out (tex_bus_if.req_valid),
.ready_out (tex_bus_if.req_ready)
@ -116,14 +116,14 @@ module VX_tex_agent #(
`ifdef DBG_TRACE_TEX
always @(posedge clk) begin
if (tex_agent_if.valid && tex_agent_if.ready) begin
`TRACE(1, ("%d: core%0d-tex-req: wid=%0d, PC=0x%0h, tmask=%b, u=", $time, CORE_ID, tex_agent_if.wid, tex_agent_if.PC, tex_agent_if.tmask));
`TRACE_ARRAY1D(1, tex_agent_if.coords[0], `NUM_THREADS);
if (tex_exe_if.valid && tex_exe_if.ready) begin
`TRACE(1, ("%d: core%0d-tex-req: wid=%0d, PC=0x%0h, tmask=%b, u=", $time, CORE_ID, tex_exe_if.wid, tex_exe_if.PC, tex_exe_if.tmask));
`TRACE_ARRAY1D(1, tex_exe_if.coords[0], `NUM_THREADS);
`TRACE(1, (", v="));
`TRACE_ARRAY1D(1, tex_agent_if.coords[1], `NUM_THREADS);
`TRACE_ARRAY1D(1, tex_exe_if.coords[1], `NUM_THREADS);
`TRACE(1, (", lod="));
`TRACE_ARRAY1D(1, tex_agent_if.lod, `NUM_THREADS);
`TRACE(1, (", stage=%0d, tag=0x%0h (#%0d)\n", tex_agent_if.stage, req_tag, tex_agent_if.uuid));
`TRACE_ARRAY1D(1, tex_exe_if.lod, `NUM_THREADS);
`TRACE(1, (", stage=%0d, tag=0x%0h (#%0d)\n", tex_exe_if.stage, req_tag, tex_exe_if.uuid));
end
if (tex_commit_if.valid && tex_commit_if.ready) begin
`TRACE(1, ("%d: core%0d-tex-rsp: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, texels=", $time, CORE_ID, tex_commit_if.wid, tex_commit_if.PC, tex_commit_if.tmask, tex_commit_if.rd));

2
hw/rtl/tex/VX_tex_agent_if.sv → hw/rtl/tex/VX_tex_exe_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_tex_define.vh"
interface VX_tex_agent_if ();
interface VX_tex_exe_if ();
wire valid;
wire [`UP(`UUID_BITS)-1:0] uuid;