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minor updates

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This commit is contained in:
Blaise Tine 2021-01-17 13:58:43 -08:00
parent 98945df5ae
commit ed216ab39d
9 changed files with 65 additions and 30 deletions
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2
hw/rtl/VX_ibuffer.v
View file

@ -54,6 +54,8 @@ module VX_ibuffer #(
.data_out (q_data_prev[i]),
`UNUSED_PIN (empty),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);

4
hw/rtl/afu/VX_avs_wrapper.v
View file

@ -85,6 +85,8 @@ module VX_avs_wrapper #(
.data_out (dram_rsp_tag),
`UNUSED_PIN (empty),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);
@ -101,6 +103,8 @@ module VX_avs_wrapper #(
.data_out (dram_rsp_data),
.empty (avs_rspq_empty),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);

2
hw/rtl/afu/vortex_afu.sv
View file

@ -738,6 +738,8 @@ VX_fifo_queue #(
.data_out (cci_rdq_dout),
.empty (cci_rdq_empty),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);

14
hw/rtl/cache/VX_bank.v vendored
View file

@ -459,7 +459,7 @@ module VX_bank #(
VX_fifo_queue #(
.DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE (CRSQ_SIZE),
.BUFFERED (1),
.BUFFERED (NUM_BANKS == 1),
.FASTRAM (1)
) core_rsp_queue (
.clk (clk),
@ -470,6 +470,8 @@ module VX_bank #(
.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
.empty (crsq_empty),
.full (crsq_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);
@ -508,10 +510,11 @@ module VX_bank #(
assign dreq_byteen = writeback ? dreq_byteen_unqual : {CACHE_LINE_SIZE{1'b1}};
VX_fifo_queue_xt #(
VX_fifo_queue #(
.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (DREQ_SIZE),
.ALM_FULL (DREQ_SIZE-1),
.BUFFERED (NUM_BANKS == 1),
.FASTRAM (1)
) dram_req_queue (
.clk (clk),
@ -521,10 +524,9 @@ module VX_bank #(
.data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}),
.data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
.empty (dreq_empty),
.almost_full (dreq_almost_full),
`UNUSED_PIN (full),
`UNUSED_PIN (data_out_next),
`UNUSED_PIN (empty_next),
.alm_full(dreq_almost_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);

6
hw/rtl/cache/VX_fifo_queue_xt.v vendored
View file

@ -30,10 +30,10 @@ module VX_fifo_queue_xt #(
reg [ADDRW-1:0] used_r;
always @(posedge clk) begin
if (reset) begin
used_r <= 0;
if (reset) begin
full_r <= 0;
almost_full_r <= 0;
almost_full_r <= 0;
used_r <= 0;
end else begin
assert(!push || !full);
assert(!pop || !empty_r);

6
hw/rtl/cache/VX_shared_mem.v vendored
View file

@ -157,6 +157,8 @@ module VX_shared_mem #(
per_bank_core_req_tag}),
.empty (creq_empty),
.full (creq_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);
@ -225,7 +227,9 @@ module VX_shared_mem #(
.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}),
.data_out({core_rsp_valid_tmask, core_rsp_data, core_rsp_tag}),
.empty (crsq_empty),
.full (crsq_full),
.full (crsq_full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);

2
hw/rtl/libs/VX_elastic_buffer.v
View file

@ -48,6 +48,8 @@ module VX_elastic_buffer #(
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
);

54
hw/rtl/libs/VX_fifo_queue.v
View file

@ -3,6 +3,8 @@
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY= 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter BUFFERED = 0,
@ -14,8 +16,10 @@ module VX_fifo_queue #(
input wire pop,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
output wire empty,
output wire full,
output wire empty,
output wire alm_empty,
output wire full,
output wire alm_full,
output wire [SIZEW-1:0] size
);
`STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!"))
@ -45,37 +49,47 @@ module VX_fifo_queue #(
end
end
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0);
assign size = size_r;
assign data_out = head_r;
assign empty = (size_r == 0);
assign alm_empty = 1'b1;
assign full = (size_r != 0);
assign alm_full = 1'b1;
assign size = size_r;
end else begin
reg empty_r;
reg full_r;
reg empty_r, alm_empty_r;
reg full_r, alm_full_r;
reg [ADDRW-1:0] used_r;
always @(posedge clk) begin
if (reset) begin
empty_r <= 1;
full_r <= 0;
used_r <= 0;
empty_r <= 1;
alm_empty_r <= 1;
full_r <= 0;
alm_full_r <= 0;
used_r <= 0;
end else begin
assert(!push || !full);
assert(!pop || !empty);
if (push) begin
if (!pop) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1)) begin
if (used_r == ADDRW'(ALM_EMPTY))
alm_empty_r <= 0;
if (used_r == ADDRW'(SIZE-1))
full_r <= 1;
end
if (used_r == ADDRW'(ALM_FULL-1))
alm_full_r <= 1;
end
end else if (pop) begin
full_r <= 0;
if (used_r == ADDRW'(1)) begin
full_r <= 0;
if (used_r == ADDRW'(ALM_FULL))
alm_full_r <= 0;
if (used_r == ADDRW'(1))
empty_r <= 1;
end;
if (used_r == ADDRW'(ALM_EMPTY+1))
alm_empty_r <= 1;
end
used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop)));
end
@ -169,9 +183,11 @@ module VX_fifo_queue #(
assign data_out = dout_r;
end
assign empty = empty_r;
assign full = full_r;
assign size = {full_r, used_r};
assign empty = empty_r;
assign alm_empty = alm_empty_r;
assign full = full_r;
assign alm_full = alm_full_r;
assign size = {full_r, used_r};
end
endmodule

5
hw/unit_tests/generic_queue/testbench.v
View file

@ -25,7 +25,10 @@ module testbench();
.pop(pop),
.data_out(data_out),
.empty(empty),
.full(full)
.full(full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_VAR (size)
);
always begin