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minor updates

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This commit is contained in:
Blaise Tine 2022-08-04 01:11:54 -07:00
parent c7e511ed1e
commit f28d3efe5c
50 changed files with 130 additions and 143 deletions
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2
hw/afu/opae/VX_avs_adapter.sv
View file

@ -7,7 +7,7 @@ module VX_avs_adapter #(
parameter AVS_BANKS = 1,
parameter REQ_TAG_WIDTH = 1,
parameter RD_QUEUE_SIZE = 1,
localparam AVS_BYTEENW = (AVS_DATA_WIDTH / 8)
parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8)
) (
input wire clk,
input wire reset,

4
hw/afu/opae/VX_mem_adapter.sv
View file

@ -7,8 +7,8 @@ module VX_mem_adapter #(
parameter DST_ADDR_WIDTH = 1,
parameter SRC_TAG_WIDTH = 1,
parameter DST_TAG_WIDTH = 1,
localparam SRC_DATA_SIZE = (SRC_DATA_WIDTH / 8),
localparam DST_DATA_SIZE = (DST_DATA_WIDTH / 8)
parameter SRC_DATA_SIZE = (SRC_DATA_WIDTH / 8),
parameter DST_DATA_SIZE = (DST_DATA_WIDTH / 8)
) (
input wire clk,
input wire reset,

4
hw/rtl/VX_alu_unit.sv
View file

@ -197,8 +197,6 @@ module VX_alu_unit #(
// send response
`RESET_RELAY (rsp_arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
@ -206,7 +204,7 @@ module VX_alu_unit #(
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (rsp_arb_reset),
.reset (reset),
.valid_in ({
alu_valid_out
`ifdef EXT_M_ENABLE

2
hw/rtl/VX_cluster.sv
View file

@ -460,7 +460,7 @@ module VX_cluster #(
// Generate all sockets
for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
`RESET_RELAY_EX (socket_reset, reset, (`NUM_SOCKETS > 1));
`RESET_RELAY (socket_reset, reset);
`BUFFER_DCR_WRITE_IF(socket_dcr_write_if, base_dcr_write_if, (`NUM_SOCKETS > 1));

4
hw/rtl/VX_gpu_unit.sv
View file

@ -290,8 +290,6 @@ module VX_gpu_unit #(
// response arbitration
`RESET_RELAY (rsp_arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
@ -299,7 +297,7 @@ module VX_gpu_unit #(
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (rsp_arb_reset),
.reset (reset),
.valid_in ({
wctl_rsp_valid
`ifdef EXT_TEX_ENABLE

5
hw/rtl/VX_mem_arb.sv
View file

@ -3,7 +3,7 @@
module VX_mem_arb #(
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
localparam DATA_SIZE = (DATA_WIDTH / 8),
parameter DATA_SIZE = (DATA_WIDTH / 8),
parameter ADDR_WIDTH = (32 - `CLOG2(DATA_SIZE)),
parameter TAG_WIDTH = 1,
parameter TAG_SEL_IDX = 0,
@ -98,7 +98,8 @@ module VX_mem_arb #(
VX_stream_switch #(
.NUM_OUTPUTS (NUM_REQS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
.BUFFERED (BUFFERED_RSP),
.MAX_FANOUT (4)
) rsp_switch (
.clk (clk),
.reset (reset),

11
hw/rtl/VX_platform.vh
View file

@ -142,14 +142,6 @@
end \
`TRACE(lvl, ("}"))
`define RESET_RELAY(dst, src) \
wire dst; \
VX_reset_relay __``dst ( \
.clk (clk), \
.reset (src), \
.reset_o (dst) \
)
`define RESET_RELAY_EX(dst, src, ENABLE) \
wire dst; \
VX_reset_relay #(.DEPTH(ENABLE)) __``dst ( \
@ -158,6 +150,9 @@
.reset_o (dst) \
)
`define RESET_RELAY(dst, src) \
`RESET_RELAY_EX (dst, src, 1)
`define POP_COUNT(out, in) \
VX_popcount #( \
.N ($bits(in)) \

2
hw/rtl/VX_socket.sv
View file

@ -318,7 +318,7 @@ module VX_socket #(
// Generate all cores
for (genvar i = 0; i < `SOCKET_SIZE; ++i) begin
`RESET_RELAY_EX (core_reset, reset, (`SOCKET_SIZE > 1));
`RESET_RELAY (core_reset, reset);
`BUFFER_DCR_WRITE_IF(core_dcr_write_if, dcr_write_if, (`SOCKET_SIZE > 1));

4
hw/rtl/VX_writeback.sv
View file

@ -35,8 +35,6 @@ module VX_writeback #(
wire wb_alu_ready_in;
wire wb_ld_ready_in;
`RESET_RELAY (rsp_arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (NUM_RSPS),
.DATAW (DATAW),
@ -44,7 +42,7 @@ module VX_writeback #(
.BUFFERED (2)
) rsp_arb (
.clk (clk),
.reset (rsp_arb_reset),
.reset (reset),
.valid_in ({
`ifdef EXT_F_ENABLE
fpu_commit_if.valid && fpu_commit_if.wb,

2
hw/rtl/Vortex.sv
View file

@ -139,7 +139,7 @@ module Vortex (
// Generate all clusters
for (genvar i = 0; i < `NUM_CLUSTERS; ++i) begin
`RESET_RELAY_EX (cluster_reset, reset, (`NUM_CLUSTERS > 1));
`RESET_RELAY (cluster_reset, reset);
`BUFFER_DCR_WRITE_IF(cluster_dcr_write_if, dcr_write_if, (`NUM_CLUSTERS > 1));

2
hw/rtl/Vortex_axi.sv
View file

@ -9,7 +9,7 @@ module Vortex_axi #(
parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH,
localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
)(
// Clock
input wire clk,

4
hw/rtl/cache/VX_bank.sv vendored
View file

@ -44,8 +44,8 @@ module VX_bank #(
// Memory request output register
parameter MEM_OUT_REG = 0,
localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE),
localparam WORD_SEL_BITS = `UP(`WORD_SEL_BITS)
parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE),
parameter WORD_SEL_BITS = `UP(`WORD_SEL_BITS)
) (
input wire clk,
input wire reset,

12
hw/rtl/cache/VX_cache.sv vendored
View file

@ -235,8 +235,6 @@ module VX_cache #(
// Core request dispatch
`RESET_RELAY (req_dispatch_reset, reset);
VX_req_dispatch #(
.LINE_SIZE (LINE_SIZE),
.WORD_SIZE (WORD_SIZE),
@ -247,7 +245,7 @@ module VX_cache #(
.TAG_WIDTH (TAG_WIDTH)
) req_dispatch (
.clk (clk),
.reset (req_dispatch_reset),
.reset (reset),
`ifdef PERF_ENABLE
.bank_stalls (perf_cache_if.bank_stalls),
`endif
@ -429,8 +427,6 @@ module VX_cache #(
// Core responce merge
`RESET_RELAY (rsp_merge_reset, reset);
VX_rsp_merge #(
.NUM_REQS (NUM_REQS),
.NUM_BANKS (NUM_BANKS),
@ -439,7 +435,7 @@ module VX_cache #(
.TAG_WIDTH (TAG_WIDTH)
) rsp_merge (
.clk (clk),
.reset (rsp_merge_reset),
.reset (reset),
.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
.per_bank_core_rsp_pmask (per_bank_core_rsp_pmask),
.per_bank_core_rsp_data (per_bank_core_rsp_data),
@ -479,15 +475,13 @@ module VX_cache #(
per_bank_mem_req_data[i]};
end
`RESET_RELAY (mem_req_arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (NUM_BANKS),
.DATAW (`MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + NUM_PORTS * (1 + WORD_SIZE + WORD_SEL_BITS + `WORD_WIDTH)),
.ARBITER ("R")
) mem_req_arb (
.clk (clk),
.reset (mem_req_arb_reset),
.reset (reset),
.valid_in (per_bank_mem_req_valid),
.ready_in (per_bank_mem_req_ready),
.data_in (data_in),

3
hw/rtl/cache/VX_cache_arb.sv vendored
View file

@ -140,7 +140,8 @@ module VX_cache_arb #(
.NUM_INPUTS (NUM_OUTPUTS),
.NUM_OUTPUTS (NUM_INPUTS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
.BUFFERED (BUFFERED_RSP),
.MAX_FANOUT (4)
) rsp_switch (
.clk (clk),
.reset (reset),

2
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -145,7 +145,7 @@ module VX_cache_cluster #(
`CACHE_RSP_FROM_MEM(arb_core_rsp_if[i], arb_core_rsp_m_if, j);
end
`RESET_RELAY_EX (cache_reset, reset, (NUM_CACHES > 1));
`RESET_RELAY (cache_reset, reset);
VX_cache_wrap #(
.INSTANCE_ID ($sformatf("%s%0d", INSTANCE_ID, i)),

10
hw/rtl/cache/VX_cache_req_if.sv vendored
View file

@ -1,11 +1,11 @@
`include "VX_cache_define.vh"
interface VX_cache_req_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1,
localparam ADDR_WIDTH = 32 - `CLOG2(WORD_SIZE),
localparam DATA_WIDTH = WORD_SIZE * 8
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1,
parameter ADDR_WIDTH = 32 - `CLOG2(WORD_SIZE),
parameter DATA_WIDTH = WORD_SIZE * 8
) ();
wire [NUM_REQS-1:0] valid;

2
hw/rtl/cache/VX_miss_resrv.sv vendored
View file

@ -23,7 +23,7 @@ module VX_miss_resrv #(
// core request tag size
parameter TAG_WIDTH = UUID_WIDTH + 1,
localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE)
parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE)
) (
input wire clk,
input wire reset,

6
hw/rtl/cache/VX_nc_bypass.sv vendored
View file

@ -18,9 +18,9 @@ module VX_nc_bypass #(
parameter UUID_WIDTH = 0,
localparam CORE_DATA_WIDTH = CORE_DATA_SIZE * 8,
localparam MEM_DATA_WIDTH = MEM_DATA_SIZE * 8,
localparam CORE_TAG_OUT_WIDTH = CORE_TAG_IN_WIDTH - NC_ENABLE
parameter CORE_DATA_WIDTH = CORE_DATA_SIZE * 8,
parameter MEM_DATA_WIDTH = MEM_DATA_SIZE * 8,
parameter CORE_TAG_OUT_WIDTH= CORE_TAG_IN_WIDTH - NC_ENABLE
) (
input wire clk,
input wire reset,

12
hw/rtl/cache/VX_req_dispatch.sv vendored
View file

@ -16,12 +16,12 @@ module VX_req_dispatch #(
// core request tag size
parameter TAG_WIDTH = 3,
localparam WORDS_PER_LINE = LINE_SIZE / WORD_SIZE,
localparam WORD_WIDTH = WORD_SIZE * 8,
localparam REQ_SEL_BITS = `CLOG2(NUM_REQS),
localparam WORD_SEL_BITS = `CLOG2(WORDS_PER_LINE),
localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS),
localparam LINE_ADDR_WIDTH = ADDR_WIDTH - BANK_SEL_BITS - WORD_SEL_BITS
parameter WORDS_PER_LINE = LINE_SIZE / WORD_SIZE,
parameter WORD_WIDTH = WORD_SIZE * 8,
parameter REQ_SEL_BITS = `CLOG2(NUM_REQS),
parameter WORD_SEL_BITS = `CLOG2(WORDS_PER_LINE),
parameter BANK_SEL_BITS = `CLOG2(NUM_BANKS),
parameter LINE_ADDR_WIDTH = ADDR_WIDTH - BANK_SEL_BITS - WORD_SEL_BITS
) (
input wire clk,
input wire reset,

4
hw/rtl/cache/VX_rsp_merge.sv vendored
View file

@ -12,8 +12,8 @@ module VX_rsp_merge #(
// core request tag size
parameter TAG_WIDTH = 1,
localparam WORD_WIDTH = WORD_SIZE * 8,
localparam REQ_SEL_BITS = `CLOG2(NUM_REQS)
parameter WORD_WIDTH = WORD_SIZE * 8,
parameter REQ_SEL_BITS = `CLOG2(NUM_REQS)
) (
input wire clk,
input wire reset,

3
hw/rtl/cache/VX_smem_switch.sv vendored
View file

@ -62,7 +62,8 @@ module VX_smem_switch #(
VX_stream_switch #(
.NUM_OUTPUTS (NUM_REQS),
.DATAW (REQ_DATAW),
.BUFFERED (BUFFERED_REQ)
.BUFFERED (BUFFERED_REQ),
.MAX_FANOUT (4)
) req_switch (
.clk (clk),
.reset (reset),

3
hw/rtl/fpu_unit/VX_fpu_arb.sv
View file

@ -130,7 +130,8 @@ module VX_fpu_arb #(
.NUM_INPUTS (NUM_OUTPUTS),
.NUM_OUTPUTS (NUM_INPUTS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
.BUFFERED (BUFFERED_RSP),
.MAX_FANOUT (4)
) rsp_switch (
.clk (clk),
.reset (reset),

4
hw/rtl/fpu_unit/VX_fpu_dpi.sv
View file

@ -395,8 +395,6 @@ module VX_fpu_dpi #(
assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
end
`RESET_RELAY (rsp_arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_ARB_DATAW),
@ -404,7 +402,7 @@ module VX_fpu_dpi #(
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (rsp_arb_reset),
.reset (reset),
.valid_in (per_core_valid_out),
.ready_in (per_core_ready_out),
.data_in (per_core_data_out),

4
hw/rtl/fpu_unit/VX_fpu_fpga.sv
View file

@ -193,8 +193,6 @@ module VX_fpu_fpga #(
assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]};
end
`RESET_RELAY (rsp_arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_ARB_DATAW),
@ -202,7 +200,7 @@ module VX_fpu_fpga #(
.BUFFERED (2)
) rsp_arb (
.clk (clk),
.reset (rsp_arb_reset),
.reset (reset),
.valid_in (per_core_valid_out),
.ready_in (per_core_ready_out),
.data_in (per_core_data_out),

2
hw/rtl/interfaces/VX_mem_req_if.sv
View file

@ -2,7 +2,7 @@
interface VX_mem_req_if #(
parameter DATA_WIDTH = 1,
localparam DATA_SIZE = DATA_WIDTH / 8,
parameter DATA_SIZE = DATA_WIDTH / 8,
parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
parameter TAG_WIDTH = 1
) ();

4
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -8,8 +8,8 @@ module VX_axi_adapter #(
parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
parameter VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
) (
input wire clk,
input wire reset,

6
hw/rtl/libs/VX_cyclic_arbiter.sv
View file

@ -2,9 +2,9 @@
`TRACING_OFF
module VX_cyclic_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_dp_ram.sv
View file

@ -11,7 +11,7 @@ module VX_dp_ram #(
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
localparam ADDRW = `LOG2UP(SIZE)
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire [BYTEENW-1:0] wren,

2
hw/rtl/libs/VX_fair_arbiter.sv
View file

@ -4,7 +4,7 @@
module VX_fair_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -8,7 +8,7 @@ module VX_fifo_queue #(
parameter ALM_EMPTY = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 1,
localparam SIZEW = $clog2(SIZE+1)
parameter SIZEW = $clog2(SIZE+1)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -5,7 +5,7 @@ module VX_generic_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter string TYPE = "P",
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_index_buffer.sv
View file

@ -5,7 +5,7 @@ module VX_index_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter LUTRAM = 1,
localparam ADDRW = `LOG2UP(SIZE)
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_lzc.sv
View file

@ -4,7 +4,7 @@
module VX_lzc #(
parameter N = 2,
parameter REVERSE = 0, // 0 -> leading zero, 1 -> trailing zero,
localparam LOGN = `LOG2UP(N)
parameter LOGN = `LOG2UP(N)
) (
input wire [N-1:0] data_in,
output wire [LOGN-1:0] data_out,

6
hw/rtl/libs/VX_matrix_arbiter.sv
View file

@ -2,9 +2,9 @@
`TRACING_OFF
module VX_matrix_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,

10
hw/rtl/libs/VX_mem_scheduler.sv
View file

@ -14,11 +14,11 @@ module VX_mem_scheduler #(
parameter CORE_OUT_REG = 0,
parameter MEM_OUT_REG = 0,
localparam BYTEENW = DATA_WIDTH / 8,
localparam NUM_BATCHES = (NUM_REQS + NUM_BANKS - 1) / NUM_BANKS,
localparam QUEUE_ADDRW = `CLOG2(QUEUE_SIZE),
localparam BATCH_SEL_BITS = `CLOG2(NUM_BATCHES),
localparam MEM_TAGW = UUID_WIDTH + QUEUE_ADDRW + BATCH_SEL_BITS
parameter BYTEENW = DATA_WIDTH / 8,
parameter NUM_BATCHES = (NUM_REQS + NUM_BANKS - 1) / NUM_BANKS,
parameter QUEUE_ADDRW = `CLOG2(QUEUE_SIZE),
parameter BATCH_SEL_BITS = `CLOG2(NUM_BATCHES),
parameter MEM_TAGW = UUID_WIDTH + QUEUE_ADDRW + BATCH_SEL_BITS
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_mux.sv
View file

@ -4,7 +4,7 @@
module VX_mux #(
parameter DATAW = 1,
parameter N = 1,
localparam LN = `LOG2UP(N)
parameter LN = `LOG2UP(N)
) (
input wire [N-1:0][DATAW-1:0] data_in,
input wire [LN-1:0] sel_in,

2
hw/rtl/libs/VX_onehot_encoder.sv
View file

@ -8,7 +8,7 @@ module VX_onehot_encoder #(
parameter N = 1,
parameter REVERSE = 0,
parameter MODEL = 1,
localparam LN = `LOG2UP(N)
parameter LN = `LOG2UP(N)
) (
input wire [N-1:0] data_in,
output wire [LN-1:0] data_out,

4
hw/rtl/libs/VX_pending_size.sv
View file

@ -2,8 +2,8 @@
`TRACING_OFF
module VX_pending_size #(
parameter SIZE = 1,
localparam SIZEW = $clog2(SIZE+1)
parameter SIZE = 1,
parameter SIZEW = $clog2(SIZE+1)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_popcount.sv
View file

@ -4,7 +4,7 @@
module VX_popcount #(
parameter MODEL = 1,
parameter N = 1,
localparam M = $clog2(N+1)
parameter M = $clog2(N+1)
) (
input wire [N-1:0] data_in,
output wire [M-1:0] data_out

6
hw/rtl/libs/VX_priority_arbiter.sv
View file

@ -2,9 +2,9 @@
`TRACING_OFF
module VX_priority_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_priority_encoder.sv
View file

@ -5,7 +5,7 @@ module VX_priority_encoder #(
parameter N = 1,
parameter REVERSE = 0,
parameter MODEL = 1,
localparam LN = `LOG2UP(N)
parameter LN = `LOG2UP(N)
) (
input wire [N-1:0] data_in,
output wire [N-1:0] onehot,

2
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -5,7 +5,7 @@ module VX_rr_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter MODEL = 1,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_sp_ram.sv
View file

@ -11,7 +11,7 @@ module VX_sp_ram #(
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
localparam ADDRW = `LOG2UP(SIZE)
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire [ADDRW-1:0] addr,

4
hw/rtl/libs/VX_stream_arb.sv
View file

@ -306,7 +306,7 @@ module VX_stream_arb #(
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (BUFFERED == 0),
@ -328,7 +328,7 @@ module VX_stream_arb #(
end else begin
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
for (genvar j = 0; j < NUM_LANES; ++j) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (BUFFERED == 0),

19
hw/rtl/libs/VX_stream_switch.sv
View file

@ -2,15 +2,16 @@
`TRACING_OFF
module VX_stream_switch #(
parameter NUM_INPUTS = 1,
parameter NUM_OUTPUTS = 1,
parameter NUM_LANES = 1,
parameter DATAW = 1,
parameter LOCK_ENABLE = 1,
parameter BUFFERED = 0,
parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? ((NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS) : ((NUM_OUTPUTS + NUM_INPUTS - 1) / NUM_INPUTS),
parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS),
localparam LOG_NUM_REQS = `CLOG2(NUM_REQS)
parameter NUM_INPUTS = 1,
parameter NUM_OUTPUTS = 1,
parameter NUM_LANES = 1,
parameter DATAW = 1,
parameter LOCK_ENABLE = 1,
parameter BUFFERED = 0,
parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? ((NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS) : ((NUM_OUTPUTS + NUM_INPUTS - 1) / NUM_INPUTS),
parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS),
parameter MAX_FANOUT = 8,
parameter LOG_NUM_REQS = `CLOG2(NUM_REQS)
) (
input wire clk,
input wire reset,

22
hw/rtl/raster_unit/VX_raster_unit.sv
View file

@ -40,11 +40,9 @@ module VX_raster_unit #(
raster_dcrs_t raster_dcrs;
`RESET_RELAY (raster_dcr_reset, reset);
VX_raster_dcr raster_dcr (
.clk (clk),
.reset (raster_dcr_reset),
.reset (reset),
.dcr_write_if(dcr_write_if),
.raster_dcrs(raster_dcrs)
);
@ -63,11 +61,11 @@ module VX_raster_unit #(
wire mem_unit_valid;
wire mem_unit_ready;
`RESET_RELAY (raster_mem_reset, reset);
`RESET_RELAY (mem_reset, reset);
// Start execution
always @(posedge clk) begin
mem_unit_start <= raster_mem_reset;
mem_unit_start <= mem_reset;
end
// Memory unit
@ -79,7 +77,7 @@ module VX_raster_unit #(
.QUEUE_SIZE (MEM_FIFO_DEPTH)
) raster_mem (
.clk (clk),
.reset (raster_mem_reset),
.reset (mem_reset),
.start (mem_unit_start),
.busy (mem_unit_busy),
@ -152,8 +150,6 @@ module VX_raster_unit #(
wire [NUM_PES-1:0][PRIM_DATA_WIDTH-1:0] pes_data_in;
wire [NUM_PES-1:0] pes_ready_in;
`RESET_RELAY (pe_req_arb_reset, reset);
VX_stream_arb #(
.NUM_OUTPUTS (NUM_PES),
.DATAW (PRIM_DATA_WIDTH),
@ -161,7 +157,7 @@ module VX_raster_unit #(
.BUFFERED (1)
) pe_req_arb (
.clk (clk),
.reset (pe_req_arb_reset),
.reset (reset),
.valid_in (pe_valid),
.ready_in (pe_ready),
.data_in ({pe_x_loc, pe_y_loc, pe_pid, pe_edges_e, pe_extents}),
@ -216,7 +212,7 @@ module VX_raster_unit #(
assign {pe_x_loc_in, pe_y_loc_in, pe_pid_in, pe_edges_in, pe_extents_in} = pes_data_in[i];
`RESET_RELAY (raster_pe_reset, reset);
`RESET_RELAY (pe_reset, reset);
VX_raster_pe #(
.INSTANCE_ID (INSTANCE_ID),
@ -226,7 +222,7 @@ module VX_raster_unit #(
.QUAD_FIFO_DEPTH (QUAD_FIFO_DEPTH)
) raster_pe (
.clk (clk),
.reset (raster_pe_reset),
.reset (pe_reset),
.dcrs (raster_dcrs),
@ -248,8 +244,6 @@ module VX_raster_unit #(
assign pe_raster_req_if[i].valid = pe_valid_out || pe_raster_req_if[i].empty;
end
`RESET_RELAY (raster_arb_reset, reset);
VX_raster_arb #(
.NUM_INPUTS (NUM_PES),
.NUM_LANES (OUTPUT_QUADS),
@ -257,7 +251,7 @@ module VX_raster_unit #(
.BUFFERED (2)
) raster_arb (
.clk (clk),
.reset (raster_arb_reset),
.reset (reset),
.req_in_if (pe_raster_req_if),
.req_out_if (raster_req_tmp_if)
);

16
hw/rtl/rop_unit/VX_rop_unit.sv
View file

@ -28,11 +28,9 @@ module VX_rop_unit #(
rop_dcrs_t rop_dcrs;
`RESET_RELAY (rop_dcr_reset, reset);
VX_rop_dcr rop_dcr (
.clk (clk),
.reset (rop_dcr_reset),
.reset (reset),
.dcr_write_if(dcr_write_if),
.rop_dcrs (rop_dcrs)
);
@ -61,13 +59,15 @@ module VX_rop_unit #(
wire mem_rsp_ready;
wire mem_write_notify;
`RESET_RELAY (mem_reset, reset);
VX_rop_mem #(
.INSTANCE_ID (INSTANCE_ID),
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (MEM_TAG_WIDTH)
) rop_mem (
.clk (clk),
.reset (reset),
.reset (mem_reset),
.dcrs (rop_dcrs),
@ -116,13 +116,15 @@ module VX_rop_unit #(
wire [NUM_LANES-1:0][`ROP_STENCIL_BITS-1:0] ds_stencil_out;
wire [NUM_LANES-1:0] ds_pass_out;
`RESET_RELAY (ds_reset, reset);
VX_rop_ds #(
.INSTANCE_ID (INSTANCE_ID),
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (DS_TAG_WIDTH)
) rop_ds (
.clk (clk),
.reset (reset),
.reset (ds_reset),
.dcrs (rop_dcrs),
@ -157,13 +159,15 @@ module VX_rop_unit #(
rgba_t [NUM_LANES-1:0] blend_dst_color;
rgba_t [NUM_LANES-1:0] blend_color_out;
`RESET_RELAY (blend_reset, reset);
VX_rop_blend #(
.INSTANCE_ID (INSTANCE_ID),
.NUM_LANES (NUM_LANES),
.TAG_WIDTH (BLEND_TAG_WIDTH)
) rop_blend (
.clk (clk),
.reset (reset),
.reset (blend_reset),
.dcrs (rop_dcrs),

3
hw/rtl/tex_unit/VX_tex_arb.sv
View file

@ -130,7 +130,8 @@ module VX_tex_arb #(
.NUM_INPUTS (NUM_OUTPUTS),
.NUM_OUTPUTS (NUM_INPUTS),
.DATAW (RSP_DATAW),
.BUFFERED (BUFFERED_RSP)
.BUFFERED (BUFFERED_RSP),
.MAX_FANOUT (4)
) rsp_switch (
.clk (clk),
.reset (reset),

18
hw/rtl/tex_unit/VX_tex_unit.sv
View file

@ -31,13 +31,11 @@ module VX_tex_unit #(
tex_dcrs_t tex_dcrs;
`RESET_RELAY (tex_dcr_reset, reset);
VX_tex_dcr #(
.NUM_STAGES (`TEX_STAGE_COUNT)
) tex_dcr (
.clk (clk),
.reset (tex_dcr_reset),
.reset (reset),
.dcr_write_if(dcr_write_if),
.stage (tex_req_if.stage),
.tex_dcrs (tex_dcrs)
@ -88,6 +86,8 @@ module VX_tex_unit #(
wire [NUM_LANES-1:0][31:0] mem_req_baseaddr;
wire [(TAG_WIDTH + `TEX_FORMAT_BITS)-1:0] mem_req_info;
wire mem_req_ready;
`RESET_RELAY (addr_reset, reset);
VX_tex_addr #(
.INSTANCE_ID (INSTANCE_ID),
@ -95,7 +95,7 @@ module VX_tex_unit #(
.NUM_LANES (NUM_LANES)
) tex_addr (
.clk (clk),
.reset (reset),
.reset (addr_reset),
// inputs
.req_valid (req_valid),
@ -128,7 +128,9 @@ module VX_tex_unit #(
wire mem_rsp_valid;
wire [NUM_LANES-1:0][3:0][31:0] mem_rsp_data;
wire [(TAG_WIDTH + `TEX_FORMAT_BITS + BLEND_FRAC_W)-1:0] mem_rsp_info;
wire mem_rsp_ready;
wire mem_rsp_ready;
`RESET_RELAY (mem_reset, reset);
VX_tex_mem #(
.INSTANCE_ID (INSTANCE_ID),
@ -136,7 +138,7 @@ module VX_tex_unit #(
.NUM_LANES (NUM_LANES)
) tex_mem (
.clk (clk),
.reset (reset),
.reset (mem_reset),
// memory interface
.cache_req_if (cache_req_if),
@ -166,13 +168,15 @@ module VX_tex_unit #(
wire [TAG_WIDTH-1:0] sampler_rsp_info;
wire sampler_rsp_ready;
`RESET_RELAY (sample_reset, reset);
VX_tex_sampler #(
.INSTANCE_ID (INSTANCE_ID),
.REQ_INFOW (TAG_WIDTH),
.NUM_LANES (NUM_LANES)
) tex_sampler (
.clk (clk),
.reset (reset),
.reset (sample_reset),
// inputs
.req_valid (mem_rsp_valid),

18
hw/syn/altera/opae/vortex_afu.qsf
View file

@ -23,13 +23,13 @@ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name USE_HIGH_SPEED_ADDER ON
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
#set_global_assignment -name MUX_RESTRUCTURE ON
#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name SEED 1
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#set_global_assignment -name SEED 1