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https://github.com/vortexgpgpu/vortex.git
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GPRs optimization - disabling BRAM's read-during-write bypass block.
This commit is contained in:
Blaise Tine
parent
12b8b4af24
commit
f3ba27b138
2 changed files with 108 additions and 106 deletions
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@ -17,71 +17,100 @@ module VX_gpr_stage #(
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (reset)
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localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
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// ensure r0 never gets written, which can happen before the reset
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wire write_enable = writeback_if.valid && (writeback_if.rd != 0);
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`ifdef EXT_F_ENABLE
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localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
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wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2, rdata3;
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wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2, raddr3;
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assign waddr = {writeback_if.wid, writeback_if.rd};
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assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
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assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2};
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assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3};
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wire [(`NUM_THREADS * 4)-1:0] wren;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign wren [i * 4 +: 4] = {4{write_enable && writeback_if.tmask[i]}};
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end
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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VX_dp_ram #(
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.RD_PORTS (3),
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.DATAW (32),
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.SIZE (RAM_SIZE),
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.INIT_ENABLE (1),
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.INIT_VALUE (0)
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) dp_ram (
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.clk (clk),
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.wren (write_enable && writeback_if.tmask[i]),
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.waddr (waddr),
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.wdata (writeback_if.data[i]),
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.rden (3'b111),
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.raddr ({raddr3, raddr2, raddr1}),
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.rdata ({rdata3[i], rdata2[i], rdata1[i]})
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);
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reg [`NUM_THREADS-1:0][31:0] last_wdata;
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reg [$clog2(RAM_SIZE)-1:0] last_waddr;
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reg [`NUM_THREADS-1:0] last_wmask;
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always @(posedge clk) begin
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last_wdata <= writeback_if.data;
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last_wmask <= {`NUM_THREADS{write_enable}} & writeback_if.tmask;
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last_waddr <= waddr;
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end
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assign gpr_rsp_if.rs1_data = rdata1;
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assign gpr_rsp_if.rs2_data = rdata2;
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assign gpr_rsp_if.rs3_data = rdata3;
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`else
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localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
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wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2;
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wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2;
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assign waddr = {writeback_if.wid, writeback_if.rd};
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assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
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assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2};
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`UNUSED_VAR (gpr_req_if.rs3)
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assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
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assign raddr2 = {gpr_req_if.wid, gpr_req_if.rs2};
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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VX_dp_ram #(
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.RD_PORTS (2),
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.DATAW (32),
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.SIZE (RAM_SIZE),
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.INIT_ENABLE (1),
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.INIT_VALUE (0)
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) dp_ram (
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.clk (clk),
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.wren (write_enable && writeback_if.tmask[i]),
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.waddr (waddr),
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.wdata (writeback_if.data[i]),
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.rden (2'b11),
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.raddr ({raddr2, raddr1}),
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.rdata ({rdata2[i], rdata1[i]})
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);
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VX_dp_ram #(
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.DATAW (32 * `NUM_THREADS),
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.SIZE (RAM_SIZE),
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.BYTEENW (`NUM_THREADS * 4),
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.INIT_ENABLE (1),
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.INIT_VALUE (0),
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.NO_RWCHECK (1)
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) dp_ram1 (
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.clk (clk),
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.wren (wren),
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.waddr (waddr),
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.wdata (writeback_if.data),
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.rden (1'b1),
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.raddr (raddr1),
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.rdata (rdata1)
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);
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VX_dp_ram #(
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.DATAW (32 * `NUM_THREADS),
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.SIZE (RAM_SIZE),
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.BYTEENW (`NUM_THREADS * 4),
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.INIT_ENABLE (1),
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.INIT_VALUE (0),
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.NO_RWCHECK (1)
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) dp_ram2 (
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.clk (clk),
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.wren (wren),
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.waddr (waddr),
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.wdata (writeback_if.data),
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.rden (1'b1),
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.raddr (raddr2),
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.rdata (rdata2)
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);
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign gpr_rsp_if.rs1_data[i] = (last_wmask[i] && (raddr1 == last_waddr)) ? last_wdata[i] : rdata1[i];
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assign gpr_rsp_if.rs2_data[i] = (last_wmask[i] && (raddr2 == last_waddr)) ? last_wdata[i] : rdata2[i];
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end
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`ifdef EXT_F_ENABLE
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wire [`NUM_THREADS-1:0][31:0] rdata3;
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wire [$clog2(RAM_SIZE)-1:0] raddr3;
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assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3};
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assign gpr_rsp_if.rs1_data = rdata1;
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assign gpr_rsp_if.rs2_data = rdata2;
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assign gpr_rsp_if.rs3_data = 0;
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VX_dp_ram #(
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.DATAW (32 * `NUM_THREADS),
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.SIZE (RAM_SIZE),
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.BYTEENW (`NUM_THREADS * 4),
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.INIT_ENABLE (1),
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.INIT_VALUE (0),
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.NO_RWCHECK (1)
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) dp_ram3 (
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.clk (clk),
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.wren (wren),
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.waddr (waddr),
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.wdata (writeback_if.data),
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.rden (1'b1),
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.raddr (raddr3),
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.rdata (rdata3)
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);
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign gpr_rsp_if.rs3_data[i] = (last_wmask[i] && (raddr3 == last_waddr)) ? last_wdata[i] : rdata3[i];
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end
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`else
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`UNUSED_VAR (gpr_req_if.rs3)
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assign gpr_rsp_if.rs3_data = 'x;
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`endif
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assign writeback_if.ready = 1'b1;
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@ -2,7 +2,6 @@
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`TRACING_OFF
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module VX_dp_ram #(
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parameter RD_PORTS = 1,
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter BYTEENW = 1,
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@ -14,18 +13,16 @@ module VX_dp_ram #(
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0
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) (
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input wire clk,
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input wire [BYTEENW-1:0] wren,
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input wire [ADDRW-1:0] waddr,
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input wire [DATAW-1:0] wdata,
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input wire [RD_PORTS-1:0] rden,
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input wire [RD_PORTS-1:0][ADDRW-1:0] raddr,
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output wire [RD_PORTS-1:0][DATAW-1:0] rdata
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input wire clk,
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input wire [BYTEENW-1:0] wren,
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input wire [ADDRW-1:0] waddr,
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input wire [DATAW-1:0] wdata,
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input wire rden,
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input wire [ADDRW-1:0] raddr,
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output wire [DATAW-1:0] rdata
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);
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`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
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`STATIC_ASSERT(!LUTRAM || (RD_PORTS == 1), ("multi-porting not supported on LUTRAM"))
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`define RAM_INITIALIZATION \
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if (INIT_ENABLE) begin \
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@ -94,7 +91,7 @@ module VX_dp_ram #(
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end
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end else begin
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if (OUTPUT_REG) begin
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reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
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reg [DATAW-1:0] rdata_r;
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if (BYTEENW > 1) begin
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reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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@ -106,10 +103,8 @@ module VX_dp_ram #(
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if (wren[i])
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ram[waddr][i] <= wdata[i * 8 +: 8];
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end
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for (integer i = 0; i < RD_PORTS; ++i) begin
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if (rden[i])
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rdata_r[i] <= ram[raddr[i]];
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end
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if (rden)
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rdata_r <= ram[raddr];
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end
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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@ -119,10 +114,8 @@ module VX_dp_ram #(
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always @(posedge clk) begin
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if (wren)
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ram[waddr] <= wdata;
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for (integer i = 0; i < RD_PORTS; ++i) begin
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if (rden[i])
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rdata_r[i] <= ram[raddr[i]];
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end
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if (rden)
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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@ -140,9 +133,7 @@ module VX_dp_ram #(
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ram[waddr][i] <= wdata[i * 8 +: 8];
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end
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end
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = ram[raddr[i]];
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end
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assign rdata = ram[raddr];
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end else begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
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@ -152,9 +143,7 @@ module VX_dp_ram #(
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if (wren)
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ram[waddr] <= wdata;
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end
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = ram[raddr[i]];
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end
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assign rdata = ram[raddr];
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end
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end else begin
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if (BYTEENW > 1) begin
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@ -168,9 +157,7 @@ module VX_dp_ram #(
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ram[waddr][i] <= wdata[i * 8 +: 8];
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end
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end
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = ram[raddr[i]];
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end
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assign rdata = ram[raddr];
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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@ -180,16 +167,14 @@ module VX_dp_ram #(
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if (wren)
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ram[waddr] <= wdata;
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end
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = ram[raddr[i]];
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end
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assign rdata = ram[raddr];
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end
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end
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end
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end
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`else
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if (OUTPUT_REG) begin
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reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
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reg [DATAW-1:0] rdata_r;
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if (BYTEENW > 1) begin
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reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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@ -200,10 +185,8 @@ module VX_dp_ram #(
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if (wren[i])
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ram[waddr][i] <= wdata[i * 8 +: 8];
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end
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for (integer i = 0; i < RD_PORTS; ++i) begin
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if (rden[i])
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rdata_r[i] <= ram[raddr[i]];
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end
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if (rden)
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rdata_r <= ram[raddr];
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end
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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@ -213,10 +196,8 @@ module VX_dp_ram #(
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always @(posedge clk) begin
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if (wren)
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ram[waddr] <= wdata;
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for (integer i = 0; i < RD_PORTS; ++i) begin
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if (rden[i])
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rdata_r[i] <= ram[raddr[i]];
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end
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if (rden)
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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@ -244,13 +225,9 @@ module VX_dp_ram #(
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`UNUSED_VAR (prev_write)
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`UNUSED_VAR (prev_data)
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`UNUSED_VAR (prev_waddr)
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = ram[raddr[i]];
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end
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assign rdata = ram[raddr];
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end else begin
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
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end
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assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
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end
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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@ -271,17 +248,13 @@ module VX_dp_ram #(
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`UNUSED_VAR (prev_write)
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`UNUSED_VAR (prev_data)
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`UNUSED_VAR (prev_waddr)
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = ram[raddr[i]];
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end
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assign rdata = ram[raddr];
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end else begin
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for (genvar i = 0; i < RD_PORTS; ++i) begin
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assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
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end
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assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
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end
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end
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end
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`endif
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`endif
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endmodule
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`TRACING_ON
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